CN105589821A - Device and method for preventing buses against deadlock - Google Patents
Device and method for preventing buses against deadlock Download PDFInfo
- Publication number
- CN105589821A CN105589821A CN201410558296.9A CN201410558296A CN105589821A CN 105589821 A CN105589821 A CN 105589821A CN 201410558296 A CN201410558296 A CN 201410558296A CN 105589821 A CN105589821 A CN 105589821A
- Authority
- CN
- China
- Prior art keywords
- bus
- signal
- processor
- delay unit
- peripheral
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 31
- 230000002093 peripheral effect Effects 0.000 claims abstract description 150
- 238000012544 monitoring process Methods 0.000 claims abstract description 100
- 238000012545 processing Methods 0.000 claims description 19
- 230000006870 function Effects 0.000 description 15
- 230000002265 prevention Effects 0.000 description 12
- 230000001934 delay Effects 0.000 description 8
- 230000004044 response Effects 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 5
- 230000006854 communication Effects 0.000 description 5
- 238000004891 communication Methods 0.000 description 4
- 230000003111 delayed effect Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000977 initiatory effect Effects 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
The invention discloses a device for preventing buses against deadlock. The device comprises a peripheral delay time unit used for monitoring bus states between buses and peripherals in order to obtain first bus state signal and sending the signal to a state monitoring unit, and performing reset operation on a first handshaking signal between buses and peripherals according to the received reset control instruction; a processor time-delay unit used for monitoring bus states between buses and peripherals in order to obtain a second bus state signal and sending the signal to the state monitoring state and performing reset operation on a second handshaking signal between buses and a processor according to the received reset control instruction; a state monitoring state used for sending a reset control instruction when the first bus state signal and/or the second bus state signal and/or counted and the time-keeping duration exceeds corresponding setting time so that peripheral delay time units and a processor delay time unit are used for resetting handshaking signals.Meanwhile, the invention further discloses a method for preventing chip buses against deadlock.
Description
Technical Field
The invention relates to the technical field of bus control, in particular to a device and a method for preventing a bus from being deadlocked.
Background
Electronic equipment is ubiquitous in various fields of social production and life, and productivity and living level of the society are greatly improved. With the advancement of technology, the chip design scale of electronic devices is increasing, and the chip design, the bus design for connecting each device in the chip, and the interaction between the bus and the processor or between the bus and the peripheral devices are also increasing in complexity. Here, the peripheral means a functional unit connected to a bus.
Generally, when a processor of an electronic device interacts with a peripheral device through a bus, the processor sends an operation instruction, and the peripheral device performs response operation on the operation instruction. During this operation, the processor and the peripheral are connected by a bus. When the peripheral completes response operation to the processor, a feedback signal is sent to the processor, and the feedback signal belongs to a part of the bus signal. The processor sends an operation instruction to the peripheral equipment, the operation instruction sends an effective signal to the peripheral equipment through the bus, but the response operation and the effective signal have different expression modes in different bus types, some are a group of signals or a signal, some are data packets and the like; this may cause an exception to the data transfer between the processor and the peripheral device, and therefore, a bus design is required for different types of signals.
At present, the data transfer between the processor and the peripheral device is abnormal mainly including two aspects: on one hand, when the bus is abnormally designed, the operation instruction sent by the processor cannot reach the peripheral correctly, so that the peripheral does not perform response operation; on the other hand, the peripheral receives the operation instruction sent by the processor, but the peripheral does not generate a response operation corresponding to the operation instruction due to the abnormality of the peripheral, or the response operation is abnormal when being transmitted in the bus, so that the processor is in a waiting state, a bus deadlock phenomenon occurs, and the processor cannot continue to execute subsequent instructions. Normally, a processor or peripheral can only be made to operate normally by powering down or resetting, but the powering down or resetting may cause a system failure. The existing solution for solving the bus deadlock is to add a detection circuit or add a coprocessor to process the bus exception, but the method cannot solve the problem of the bus deadlock fundamentally.
Disclosure of Invention
In view of the above, embodiments of the present invention are directed to an apparatus and a method for preventing a bus deadlock, which at least solve the technical problem of the existing bus deadlock.
The technical scheme of the embodiment of the invention is realized as follows:
the embodiment of the invention provides a device for preventing a bus from being deadlocked, which comprises:
the peripheral delay unit is used for monitoring the bus state between the bus and the peripheral to obtain a first bus state signal, sending the first bus state signal to the state monitoring unit, and resetting the first handshake signal between the bus and the peripheral according to the received reset control instruction;
the processor delay unit is used for monitoring the bus state between the bus and the processor, obtaining a second bus state signal, sending the second bus state signal to the state monitoring unit, and resetting a second handshake signal between the bus and the processor according to the received reset control instruction;
the state monitoring unit is used for timing the data signal in the first bus state signal to obtain first timing time, and when the first timing time exceeds first set time, a first reset control instruction is sent to the peripheral delay unit; the first reset control instruction is used for enabling the peripheral delay unit to reset the first handshake signal; and/or timing the data signal in the second bus state signal to obtain second timing time, and sending a second reset control instruction to the processor delay unit when the second timing time exceeds second set time; the second reset control instruction is used for enabling the processor delay unit to carry out reset operation on the second handshake signals.
In the above scheme, the apparatus includes:
the bus configuration unit is used for sending a first configuration signal to the peripheral delay unit, wherein the first configuration signal is used for enabling the peripheral delay unit to reset the first handshake signal; and/or sending a second configuration signal to the processor delay unit; the second configuration signal is used for enabling the processor delay unit to reset the second handshake signal.
In the foregoing solution, the peripheral delay unit includes:
the first bus state monitoring module is used for monitoring a first bus state signal between a bus and an external device and sending the first bus state signal to the state monitoring unit;
and the first reset module is used for delaying the first handshake signal between the bus and the peripheral equipment according to the first reset control instruction sent by the state monitoring unit and resetting the first handshake signal.
In the foregoing solution, the processor delay unit includes:
the second bus state monitoring module is used for monitoring a second bus state signal between the bus and the processor and sending the second bus state signal to the state monitoring unit;
and the second reset module is used for delaying the second handshake signal between the bus and the processor according to the second reset control instruction sent by the state monitoring unit and resetting the second handshake signal.
In the above scheme, the state monitoring unit includes:
the watchdog module is used for timing the data signal in the first bus state signal monitored by the peripheral delay unit to obtain first timing time; and/or timing the data signal in the second bus state signal monitored by the processor delay unit to obtain a second timing time;
the command sending module is used for sending a first reset control command to the peripheral delay unit when the first timing time exceeds a first set time and/or the second timing time exceeds a second set time; and/or sending a second reset control instruction to the processor delay unit; the first set time and the second set time are less than a bus deadlock time.
In the foregoing solution, the state monitoring unit further includes:
the interrupt processing module is used for receiving a third reset control instruction sent by the instruction sending module and forbidding the processor to carry out instruction operation on the bus according to the third reset control instruction; and allowing the processor to perform instruction operation on the bus after a third set time.
The embodiment of the invention also provides a method for preventing the deadlock of the chip bus, which comprises the following steps:
monitoring the bus state between the bus and the peripheral equipment to obtain a first bus state signal;
monitoring the bus state between the bus and the processor to obtain a second bus state signal;
timing the data signal in the first bus state signal to obtain first timing time; when the first timing time exceeds first set time, sending a first reset control instruction; and/or timing the data signal in the second bus state signal to obtain second timing time; when the second timing time exceeds second set time, sending a second reset control instruction;
resetting the first handshake signal according to the first reset control instruction; and/or resetting the second handshake signals according to the second reset control instruction.
In the above scheme, the method further comprises:
setting a first configuration signal and/or a second configuration signal, wherein the first configuration signal is used for enabling the reset operation of the first handshake signal; the second configuration signal is used to enable a reset operation on the second handshake signal.
In the above scheme, the method further comprises:
before the first handshake signal is reset, delaying the first handshake signal between a bus and a peripheral; and/or
And delaying the second handshake signals between the bus and the processor before resetting the second handshake signals.
In the above scheme, the method further comprises:
and prohibiting the instruction operation on the bus according to the reset control instruction, and allowing the instruction operation on the bus after a third set time.
According to the device and the method for preventing the deadlock of the bus, provided by the embodiment of the invention, the peripheral delay unit and the processor delay unit respectively monitor the bus state to obtain a first bus state signal and a second bus state signal; and when the timing time of the data signals in the first bus state signal and the second bus state signal exceeds a first set time, sending a reset control instruction to the peripheral delay unit and/or the processor delay unit, so that the peripheral delay unit and/or the processor delay unit resets the first handshake signal and/or the second handshake signal. The embodiment of the invention is provided with the first set time which is used for monitoring the time limit before deadlock occurs, and the first handshake signal and/or the second handshake signal can be reset through the peripheral delay unit and/or the processor delay unit before bus deadlock occurs, so that the processor and the peripheral can perform data transmission again, and bus deadlock is prevented.
Drawings
FIG. 1 is a schematic diagram of a structure of an apparatus for preventing deadlock of a bus according to embodiment 1 of the present invention;
FIG. 2 is a schematic diagram of a bus configuration unit added to the apparatus for preventing deadlock of a bus according to embodiment 1 of the present invention;
FIG. 3 is a flowchart illustrating an implementation of a method for preventing deadlock of a chip bus according to embodiment 2 of the present invention;
FIG. 4 is a structural view showing the constitution of an apparatus according to embodiment 3 of the present invention.
Detailed Description
The technical solution of the present invention is further described in detail with reference to the drawings and the specific embodiments of the specification.
Example 1
In order to solve the technical problem of bus deadlock, this embodiment provides an apparatus for preventing bus deadlock, which is applied to a system that performs data interaction with a processor and a peripheral device respectively through a bus, as shown in fig. 1, the apparatus of this embodiment includes: a peripheral delay unit 101, a processor delay unit 102 and a state monitoring unit 103; the peripheral delay unit 101 is arranged between the bus and the peripheral, and the processor delay unit 102 is arranged between the processor and the bus;
the peripheral delay unit 101 is configured to monitor a bus state between the bus and the peripheral, obtain a first bus state signal, send the first bus state signal to the state monitoring unit 103, and perform a reset operation on a first handshake signal between the bus and the peripheral according to a received reset control instruction;
typically, the bus includes a common on-chip bus, such as an amba (advanced microcontroller bus architecture) bus or the like; the handshake signals indicate that two devices adopt a certain communication specification (protocol) to exchange data, the communication process of the two devices is called 'handshake', and the signals for communication are called handshake signals; here, the first handshake signal refers to a handshake signal between a bus and a peripheral;
the processor delay unit 102 is configured to monitor a bus state between the bus and the processor, obtain a second bus state signal, send the second bus state signal to the state monitoring unit 103, and perform a reset operation on a second handshake signal between the bus and the processor according to the received reset control instruction;
here, the second handshake signal refers to a handshake signal between the bus and the processor;
the state monitoring unit 103 is configured to time a data signal in the first bus state signal to obtain a first timing time, and send a first reset control instruction to the peripheral delay unit when the first timing time exceeds a first set time; the first reset control instruction is used for enabling the peripheral delay unit 101 to reset the first handshake signal; and/or timing the data signal in the second bus state signal to obtain second timing time; when the first timing time exceeds a second set time, sending a second reset control instruction to the processor delay unit 102; the second reset control instruction is used for enabling the processor delay unit to carry out reset operation on the second handshake signals.
Here, the first reset control instruction is used to enable the peripheral delay unit 101 to perform a reset operation on the first handshake signal, and/or the second reset control instruction is used to enable the processor delay unit 102 to perform a reset operation on the second handshake signal; because the first setting time and the second setting time are less than the bus deadlock time, the corresponding handshake signals can be reset before the bus deadlock, and the processor and the peripheral equipment can perform signal transmission again.
The device for preventing the deadlock of the bus provided by the embodiment monitors the bus state through the peripheral delay unit 101 and the processor delay unit 102, and sends a first bus state signal and a second bus state signal obtained by monitoring to the state monitoring unit 103; the state monitoring unit 103 clocks the first bus state signal and/or the second bus state signal, and when the timing in the first bus state signal and/or the second bus state signal is timed out, a reset control instruction is issued, so that the peripheral delay unit 101 and/or the processor delay unit 102 reset the corresponding handshake signals. The first setting time and the second setting time set in this embodiment can reset the corresponding handshake signals through the peripheral delay unit 101 and/or the processor delay unit 102 before the bus is deadlock, so that the processor and the peripheral re-perform data transfer, thereby avoiding bus deadlock.
In addition, in order to selectively control the processor and the peripheral devices, the apparatus further includes a bus configuration unit 104, as shown in fig. 2, the bus configuration unit 104 is connected to the peripheral delay unit 101 and/or the processor delay unit 102, respectively.
A bus configuration unit 104, configured to send a first configuration signal to the peripheral delay unit 101, where the first configuration signal is used to enable the peripheral delay unit to reset the first handshake signal; and/or processor delay unit 102 sends the second configuration signal; the second configuration signal is used for enabling the processor delay unit to reset the second handshake signal;
here, the first configuration signal is used to enable the reset operation of the peripheral delay unit 101 on the first handshake signal, and the second configuration signal is used to enable the reset operation of the processor delay unit 102 on the second handshake signal.
Specifically, when the first configuration signal and/or the second configuration signal is at a high level, the peripheral delay unit 101 is allowed to reset the first handshake signal; and/or allowing the processor to delay the reset operation of the second handshake signal by the unit 102; when the first configuration signal and/or the second configuration signal is at a low level, the reset operation of the peripheral delay unit 101 on the first handshake signal is not allowed; and/or not allowing the processor to delay the reset operation of the unit 102 to the second handshake signal; thus, the processor and the peripheral device can be selectively controlled.
Specifically, the peripheral delay unit 101 includes:
a first bus state monitoring module, configured to monitor a first bus state signal between a bus and a peripheral device, and send the first bus state signal to the state monitoring unit 103;
and the first reset module is used for delaying the first handshake signal between the bus and the peripheral equipment according to the first reset control instruction sent by the state monitoring unit and resetting the first handshake signal.
Here, the delay is used for performing beat processing on related signals in the bus, so that the time sequences of the related signals are kept consistent; these correlation signals are then sent to the bus along with other signals.
In addition, if the device of this embodiment includes the bus configuration unit 104, the first configuration signal sent by the bus configuration unit 104 and the first reset control instruction sent by the status monitoring unit 103 need to be and-operated; enabling the first reset module to reset the first handshake signal only when the first configuration signal and the first reset control instruction are both high; when one of the first configuration signal and the first reset control instruction is at a low level, the first reset module cannot reset the first handshake signal.
The processor delay unit 102 includes:
the second bus state monitoring module is configured to monitor a second bus state signal between the bus and the processor, and send the second bus state signal to the state monitoring unit 103;
and the second reset module is used for delaying the second handshake signal between the bus and the processor according to the second reset control instruction sent by the state monitoring unit and resetting the second handshake signal.
Here, the delay is used for performing beat processing on all relevant signals in the bus, so that the time sequences of the relevant signals are kept consistent; these correlation signals are then sent to the bus along with other signals.
In addition, if the device of this embodiment includes the bus configuration unit 104, the second configuration signal sent by the bus configuration unit 104 and the second reset control instruction sent by the status monitoring unit 103 need to be and-operated; enabling the second reset module to perform reset operation on the second handshake signal only when the second configuration signal and the second reset control instruction are both at a high level; when one of the second configuration signal and the second reset control instruction is at a low level, the second reset module cannot perform a reset operation on the second handshake signal.
The state monitoring unit 103 includes:
the watchdog module is used for timing the data signal in the first bus state signal monitored by the peripheral delay unit 101 to obtain first timing time; and/or timing the data signal in the second bus state signal monitored by the processor delay unit 102 to obtain a second timing time;
specifically, the watchdog module comprises a timer, wherein the timer is used for timing data signals in the first bus state signal and/or the second bus state signal; when a plurality of external devices connected with the processor are provided, a plurality of timers are correspondingly provided.
The command sending module is used for sending a first reset control command to the peripheral delay unit when the first timing time exceeds a first set time and/or the second timing time exceeds a second set time; and/or sending a second reset control instruction to the processor delay unit;
here, the first setting time and the second setting time are less than a bus deadlock time; the first set time and the second set time are set through a register; the first reset control instruction is used for resetting the first handshake signal; the second reset control instruction is used for resetting the second handshake signal.
Further, to better solve the problem of bus deadlock, the state monitoring unit 103 may further include:
the interrupt processing module is used for receiving a third reset control instruction sent by the instruction sending module and forbidding the processor to carry out instruction operation on the bus according to the third reset control instruction; allowing the processor to perform instruction operation on the bus after a third set time;
here, the third set time is used to cause the processor to re-process the signal; the third setting time is usually short as long as it is ensured that the time is longer than the time for the second handshake signal to be reset by the second reset module of the processor delay unit 102.
Example 2
This embodiment is a method for preventing deadlock of a chip bus, which is implemented based on the apparatus in embodiment 1, and as shown in fig. 3, the method for preventing deadlock of a chip bus in this embodiment includes:
s201: monitoring the bus state between the bus and the peripheral equipment to obtain a first bus state signal;
this step can be accomplished by a peripheral delay unit 101 disposed between the bus and the peripheral; the first bus state signal includes the transmission state of all signals within the bus.
S202: monitoring the bus state between the bus and the processor to obtain a second bus state signal;
this step may be performed by a processor delay unit 102 disposed between the bus and the processor; the second bus state signal includes the transmission state of all signals in the bus.
In practical application, the execution sequence of step S201 and step S202 is not limited.
S203: timing the data signal in the first bus state signal to obtain first timing time; when the first timing time exceeds first set time, sending a first reset control instruction; and/or timing the data signal in the second bus state signal to obtain second timing time; when the second timing time exceeds second set time, sending a second reset control instruction;
this step may be performed by the status monitoring unit 103; the reset control instruction is sent to the peripheral delay unit and/or the processor delay unit by the state monitoring unit 103;
s204: resetting the first handshake signal according to the first reset control instruction; and/or resetting the second handshake signals according to the second reset control instruction.
In addition, in order to selectively control the processor and the peripheral, the method may further include: the first configuration signal and the second configuration signal are set. The first configuration signal is used for enabling the reset operation of the first handshake signal; and/or a second configuration signal for enabling a reset operation on the second handshake signal;
specifically, when the first configuration signal and/or the second configuration signal is at a high level, the peripheral delay unit is allowed to reset the first handshake signal; and/or allowing the processor delay unit to reset the second handshake signal; when the first configuration signal is in a low level, the reset operation of the peripheral delay unit on the first handshake signal is not allowed; and/or when the second configuration signal is in a low level, the processor delay unit is not allowed to reset the second handshake signal; thus, the processor and the peripheral device can be selectively controlled.
Here, setting the configuration signal may be done by the bus configuration unit 104;
in the above processing procedure, step S201 specifically includes: and a first bus state monitoring module of the peripheral delay unit monitors a first bus state signal between a bus and a peripheral and sends the first bus state signal to the state monitoring unit.
Step S202 specifically includes: and a second bus state monitoring module of the processor delay unit monitors a second bus state signal between the bus and the processor and sends the second bus state signal to the state monitoring unit.
Step S203 specifically includes:
s2031: a watchdog module of the state monitoring unit times a data signal in the first bus state signal monitored by the peripheral delay unit to obtain first timing time; and/or timing the data signal in the second bus state signal monitored by the processor delay unit to obtain second timing time; the instruction sending module is used for sending the first timing time and/or the second timing time to the state monitoring unit;
s2032: the instruction sending module sends a first reset control instruction to the peripheral delay unit and/or sends a second reset control instruction to the processor delay unit when the first timing time exceeds a first set time and/or the second timing time exceeds a second set time;
the first setting time and the second setting time are less than the bus deadlock time; the first set time and the second set time are set through a register; the first reset control instruction is used for resetting the first handshake signal; the second reset control instruction is used for resetting the second handshake signal.
Step S204 specifically includes:
s2041: a first reset module of the peripheral delay unit delays the first handshake signal and resets the first handshake signal;
here, the delay may keep timings of the data signal in the first bus state signal, the first timing time of which exceeds a first set time, and the data signal, the first timing time of which does not exceed the first set time, consistent;
s2042: a second reset module of the processor delay unit delays the second handshake signal and resets the second handshake signal;
here, the delay may keep timings of the data signal in the second bus state signal, the second timing time of which exceeds the first set time, and the data signal, the second timing time of which does not exceed the first set time, consistent.
In practical application, the execution sequence of step S2041 and step S2042 is not limited.
Further, to better solve the bus deadlock problem, step S204 may further include:
s2043: an interrupt processing module of the state monitoring unit receives a third reset control instruction sent by the instruction sending module, and prohibits the processor from carrying out instruction operation on a bus according to the third reset control instruction; and allowing the processor to perform instruction operation on the bus after a third set time.
Example 3
The present embodiment describes the present invention in detail through an actual scene. The processing of the present embodiment includes:
s301: monitoring the bus state between the bus and the peripheral equipment to obtain a first bus state signal;
a first bus state monitoring module of the peripheral delay unit monitors a first bus state signal between a bus and a peripheral and sends the first bus state signal to the state monitoring unit.
This step can be accomplished by a peripheral delay unit 101 disposed between the bus and the peripheral; the first bus state signal includes the transmission state of all signals within the bus.
The peripheral delay unit 101 is configured to control a first handshake signal of a bus connected to a peripheral. The number of the peripheral delay units 101 is set according to the number of the peripherals, generally, each peripheral chip needs to be correspondingly set with one peripheral delay unit, and the peripheral delay units can also be set for specific peripherals according to the needs; and no delay chip unit is arranged for unnecessary peripherals. The peripheral delay unit 101 receives a first configuration signal from the bus configuration unit 104 and a first reset control instruction of the state monitoring unit 103, and sends a first bus state signal to the state monitoring unit 103.
The peripheral delay unit 101 delays the first handshake signal while the bus deadlock prevention function is active. The first handshake signal is not delayed while the bus deadlock prevention function is disabled. The peripheral delay unit 101 and-operates the first configuration signal and the first reset control instruction. When the first configuration signal of the bus configuration unit 104 is at a high level and the first reset control instruction from the state monitoring unit 103 is at a high level, the first reset module of the peripheral delay unit 101 resets the first handshake signal to recover to a normal idle state, and the bus deadlock prevention function is effective. When the first configuration signal of the bus configuration unit 104 is at a low level or the first reset control instruction from the state monitoring unit 103 is at a low level, the first reset module of the peripheral delay unit 101 does not reset the first handshake signal, so as to prevent the bus deadlock mode from being invalid.
S302: monitoring the bus state between the bus and the processor to obtain a second bus state signal;
the second bus state monitoring module of the processor delay unit 102 monitors a second bus state signal between the bus and the processor, and sends the second bus state signal to the state monitoring unit.
This step may be performed by a processor delay unit 102 disposed between the bus and the processor; the second bus state signal includes the transmission state of all signals in the bus.
The processor delay unit 102 is configured to control a second handshake signal of a bus connected to the processor. The processor delay unit 102 receives the second configuration signal from the bus configuration unit 104 and the second reset control instruction from the status monitoring unit 103, and sends a second bus status signal to the status monitoring unit 103.
Processor delay unit 102 delays the second handshake signal while the bus deadlock prevention function is active. The second handshake signals are not delayed while the bus deadlock prevention function is disabled. The processor delay unit 102 ands the second configuration signal and the second reset control instruction. When the second configuration signal of the bus configuration unit 104 is at a high level and the second reset control instruction from the state monitoring unit 103 is at a high level, the second reset module of the processor delay unit 102 resets the second handshake signal to recover to a normal idle state, and the bus deadlock prevention function is effective. When the second configuration signal of the bus configuration unit 104 is at a low level or the second reset control instruction from the state monitoring unit 103 is at a low level, the second reset module of the processor delay unit 102 does not reset the second handshake signal, so as to prevent the bus deadlock mode from being invalid.
In practical application, the execution sequence of step S301 and step S302 is not limited.
S303: timing the data signal in the first bus state signal to obtain first timing time; when the first timing time exceeds first set time, sending a first reset control instruction; and/or timing the data signal in the second bus state signal to obtain second timing time; when the second timing time exceeds second set time, sending a second reset control instruction;
the step is realized by a state monitoring unit 103, wherein the state monitoring unit 103 comprises a watchdog module and an instruction sending module; wherein,
the watchdog module is used for timing a data signal in the first bus state signal monitored by the peripheral delay unit to obtain first timing time and/or timing a data signal in the second bus state signal monitored by the processor delay unit to obtain second timing time; the watchdog module comprises a timer for timing the data signal within the first bus state signal and/or the second bus state signal. When a plurality of external devices connected with the processing device are provided, a plurality of timers are correspondingly provided. The timing data bit width of the timer is set according to actual needs, the dog feeding time of the watchdog module is the timeout time (namely the first set time) of the bus deadlock, and the timeout time can be configured according to actual system requirements.
The instruction sending module is used for sending a first reset control instruction to the peripheral delay unit when the overtime of the bus reaches the dog feeding time; and/or sending a second reset control instruction to the processor delay unit; the first set time and the second set time are less than the bus deadlock time; the first set time and the second set time are set through a register; the first reset control instruction is used for controlling the peripheral delay unit to reset the first handshake signal; the second reset control instruction is used for controlling the processor delay unit to reset the handshake signals;
specifically, the method comprises the following steps:
s3031: the watchdog module of the state monitoring unit 103 times the data signal in the first bus state signal monitored by the peripheral delay unit 101 to obtain a first timing time; and/or the processor delay unit 102 counts time for the data signal in the second bus state signal to obtain a second timing time; an instruction sending module that sends the first timing time and/or the second timing time to the state monitoring unit 103;
s3032: the instruction sending module sends a first reset control instruction to the peripheral delay unit 101 when the first timing time exceeds a first set time; and/or when the second timing time exceeds a second set time, sending a second reset control instruction to the processor delay unit 102;
the first setting time and the second setting time are less than the bus deadlock time; the first set time and the second set time are set through a register; the first reset control instruction is used for resetting the first handshake signal; the second reset control instruction is used for resetting the second handshake signal.
This step may be performed by the status monitoring unit 103; the reset control instruction is sent to the peripheral delay unit and/or the processor delay unit by the state monitoring unit 103;
s304: resetting the first handshake signal according to the first reset control instruction; and/or the second reset control instruction performs reset operation on the second handshake signals.
S3041: a first reset module of the peripheral delay unit 101 delays the first handshake signal and resets the first handshake signal;
here, the delay may keep timings of the data signal in the first bus state signal, the first timing time of which exceeds a first set time, and the data signal, the first timing time of which does not exceed the first set time, consistent;
s3042: a second reset module of the processor delay unit 102 delays the second handshake signal and performs a reset operation on the second handshake signal;
here, the delay may keep timings of the data signal in the second bus state signal, the second timing time of which exceeds the first set time, and the data signal, the second timing time of which does not exceed the second set time, consistent.
In practical applications, the execution sequence of step S3041 and step S3042 is not limited.
Further, in order to better solve the problem of bus deadlock, relevant processing may also be performed by an interrupt processing module further included in the state monitoring unit 103.
The interrupt processing module is used for receiving a third reset control instruction sent by the instruction sending module and forbidding the processor to carry out instruction operation on the bus according to the third reset control instruction; and allowing the processor to perform instruction operation on the bus after a third set time. Here, the third set time is for causing the processor to re-process the signal; the third setting time is usually short as long as it is ensured that the time is longer than the time for the second handshake signal to be reset by the second reset module of the processor delay unit. When the bus deadlock occurs, the interrupt processing module controls the instruction of the processor to jump to a preset mode for execution, and the preset mode comprises instruction execution without initiating bus operation and the like. That is, step S304 may further include:
s3043: an interrupt processing module of the state monitoring unit receives a third reset control instruction sent by the instruction sending module, and prohibits the processor from carrying out instruction operation on a bus according to the third reset control instruction; and allowing the processor to perform instruction operation on the bus after a third set time.
An axi (advanced configurable interface) bus is taken as an example to explain, the data bit width of the bus is 64 bits, the address bit width is 32 bits, the bit widths of the three peripheral modules and the watchdog counter are 32 bits.
The specific device is shown in fig. 4, and comprises the following components in detail:
a first part: bus configuration unit 104
The bus configuration unit 104 performs a reset operation on a handshake signal of a bus connected with a peripheral through the peripheral delay unit 101 and/or the processor delay unit 102 performs a reset operation on a handshake signal of a bus connected with a processor, and the control is realized through the configuration signal. When the configuration signal is at a high level, the corresponding bus has the function of preventing the bus from deadlock; when the configuration signal is in low level, the corresponding bus channel is not provided with the function of preventing the bus deadlock.
A second part: peripheral delay unit 101
The embodiment comprises a first peripheral, a second peripheral and a third peripheral, and correspondingly, three peripheral delay units are provided, and the functions of the three peripheral delay units are the same.
The peripheral delay unit 101 implements handshake signal control of the first peripheral, the second peripheral, and the third peripheral. The handshake signals mainly include read address channel (ARREADY) signals, read data channel (RREADY) and RRESP signals.
The peripheral delay unit 101 is configured to control a first handshake signal of a bus connected to a peripheral. The number of the peripheral delay units 101 is set according to the number of the peripherals, generally, each peripheral chip needs to be correspondingly provided with one peripheral delay unit 101, and the peripheral delay units 101 can also be set for specific peripherals according to the needs; the delay unit 101 is not provided for unnecessary peripherals.
The peripheral delay unit 101 receives a first configuration signal from the bus configuration unit 104 and a first reset control instruction of the state monitoring unit 103, and sends a first bus state signal to the state monitoring unit 103. The peripheral delay unit 101 delays the first handshake signal while the bus deadlock prevention function is active. The first handshake signal is not delayed while the bus deadlock prevention function is disabled.
The peripheral delay unit 101 and-operates the first configuration signal and the first reset control instruction. When the first configuration signal of the bus configuration unit 104 is at a high level and the first reset control instruction from the state monitoring unit 103 is at a high level, the first reset module of the peripheral delay unit 101 resets the first handshake signal to recover to a normal idle state, and the bus deadlock prevention function is effective. When the first configuration signal of the bus configuration unit 104 is at a low level or the first reset control instruction from the state monitoring unit 103 is at a low level, the first reset module of the peripheral delay unit 101 does not reset the first handshake signal, so as to prevent the bus deadlock mode from being invalid.
And a third part: processor delay unit 102
Processor delay unit 102 implements a second handshake signal control of the bus connecting the processors. The handshake signals mainly include read address channel (ARREADY) signals, read data channel (RREADY) and RRESP signals.
The processor delay unit 102 is configured to control a second handshake signal of a bus connected to the processor.
The processor delay unit 102 receives the second configuration signal from the bus configuration unit 104 and the second reset control instruction from the status monitoring unit 103, and sends a second bus status signal to the status monitoring unit 103. Processor delay unit 102 delays the second handshake signal while the bus deadlock prevention function is active. The second handshake signals are not delayed while the bus deadlock prevention function is disabled.
The processor delay unit 102 ands the second configuration signal and the second reset control instruction. When the second configuration signal of the bus configuration unit 104 is at a high level and the second reset control instruction from the state monitoring unit 103 is at a high level, the second reset module of the processor delay unit 102 resets the second handshake signal to recover to a normal idle state, and the bus deadlock prevention function is effective. When the second configuration signal of the bus configuration unit 104 is at a low level or the second reset control instruction from the state monitoring unit 103 is at a low level, the second reset module of the processor delay unit 102 does not reset the second handshake signal, so as to prevent the bus deadlock mode from being invalid.
The fourth part: state monitoring unit 103
The state monitoring unit 103 includes a watchdog module, an instruction transmitting module, and an interrupt processing module.
1) Watchdog module
The processor delay unit 102 is configured to time a data signal in a first bus state signal monitored by the peripheral delay unit 101 to obtain a first timing time and/or time a data signal in a second bus state signal monitored by the processor delay unit 102 to obtain a second timing time; the watchdog module comprises a timer for timing the data signal within the first bus state signal and/or the second bus state signal. When a plurality of external devices connected with the processing device are provided, a plurality of timers are correspondingly provided.
The timing data bit width of the timer is 32 bits, and the dog feeding time is 10 microseconds.
2) Instruction sending module
When the overtime of the bus reaches a first set time, a first reset control instruction is sent to the peripheral delay unit 101; and/or when the bus timeout reaches a second set time, sending a second reset control instruction to the processor delay unit 102; the first set time and the second set time are less than the bus deadlock time; the first set time and the second set time are set through a register; the first reset control instruction is used for controlling the peripheral delay unit 101 to reset the first handshake signal; the second reset control instruction is used for controlling the second processor delay unit 102 to reset the second handshake signal;
3) interrupt handling module
The interrupt processing module is used for receiving a third reset control instruction sent by the instruction sending module and forbidding the processor to carry out instruction operation on the bus according to the third reset control instruction; and allowing the processor to perform instruction operation on the bus after a third set time. The third set time is used for enabling the processor to process the signal again. The third setting time is usually short as long as it is ensured that the reset operation of the handshake signals is longer than the time for the second reset module of the processor delay unit to reset. When the bus deadlock occurs, the interrupt processing module controls the instruction of the processor to jump to a preset mode for execution, and the preset mode comprises instruction execution without initiating bus operation and the like.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or other forms.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, all the functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may be separately used as one unit, or two or more units may be integrated into one unit; the integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
Those of ordinary skill in the art will understand that: all or part of the steps for implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer readable storage medium, and when executed, the program performs the steps including the method embodiments; and the aforementioned storage medium includes: various media that can store program codes, such as a removable memory device, a Read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk, and an optical disk.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. An apparatus for preventing deadlock of a bus, the apparatus comprising:
the peripheral delay unit is used for monitoring the bus state between the bus and the peripheral to obtain a first bus state signal, sending the first bus state signal to the state monitoring unit, and resetting the first handshake signal between the bus and the peripheral according to the received reset control instruction;
the processor delay unit is used for monitoring the bus state between the bus and the processor, obtaining a second bus state signal, sending the second bus state signal to the state monitoring unit, and resetting a second handshake signal between the bus and the processor according to the received reset control instruction;
the state monitoring unit is used for timing the data signal in the first bus state signal to obtain first timing time, and when the first timing time exceeds first set time, a first reset control instruction is sent to the peripheral delay unit; the first reset control instruction is used for enabling the peripheral delay unit to reset the first handshake signal; and/or timing the data signal in the second bus state signal to obtain second timing time, and sending a second reset control instruction to the processor delay unit when the second timing time exceeds second set time; the second reset control instruction is used for enabling the processor delay unit to carry out reset operation on the second handshake signals.
2. The apparatus of claim 1, wherein the apparatus comprises:
the bus configuration unit is used for sending a first configuration signal to the peripheral delay unit, wherein the first configuration signal is used for enabling the peripheral delay unit to reset the first handshake signal; and/or sending a second configuration signal to the processor delay unit; the second configuration signal is used for enabling the processor delay unit to reset the second handshake signal.
3. The apparatus of claim 1 or 2, wherein the peripheral delay unit comprises:
the first bus state monitoring module is used for monitoring a first bus state signal between a bus and an external device and sending the first bus state signal to the state monitoring unit;
and the first reset module is used for delaying the first handshake signal between the bus and the peripheral equipment according to the first reset control instruction sent by the state monitoring unit and resetting the first handshake signal.
4. The apparatus of claim 1 or 2, wherein the processor delay unit comprises:
the second bus state monitoring module is used for monitoring a second bus state signal between the bus and the processor and sending the second bus state signal to the state monitoring unit;
and the second reset module is used for delaying the second handshake signal between the bus and the processor according to the second reset control instruction sent by the state monitoring unit and resetting the second handshake signal.
5. The apparatus according to claim 1 or 2, wherein the state monitoring unit comprises:
the watchdog module is used for timing the data signal in the first bus state signal monitored by the peripheral delay unit to obtain first timing time; and/or timing the data signal in the second bus state signal monitored by the processor delay unit to obtain a second timing time;
the command sending module is used for sending a first reset control command to the peripheral delay unit when the first timing time exceeds a first set time and/or the second timing time exceeds a second set time; and/or sending a second reset control instruction to the processor delay unit; the first set time and the second set time are less than a bus deadlock time.
6. The apparatus of claim 5, wherein the condition monitoring unit further comprises:
the interrupt processing module is used for receiving a third reset control instruction sent by the instruction sending module and forbidding the processor to carry out instruction operation on the bus according to the third reset control instruction; and allowing the processor to perform instruction operation on the bus after a third set time.
7. A method for preventing deadlock of a chip bus, the method comprising:
monitoring the bus state between the bus and the peripheral equipment to obtain a first bus state signal;
monitoring the bus state between the bus and the processor to obtain a second bus state signal;
timing the data signal in the first bus state signal to obtain first timing time; when the first timing time exceeds first set time, sending a first reset control instruction; and/or timing the data signal in the second bus state signal to obtain second timing time; when the second timing time exceeds second set time, sending a second reset control instruction;
resetting the first handshake signal according to the first reset control instruction; and/or resetting the second handshake signals according to the second reset control instruction.
8. The method of claim 7, further comprising:
setting a first configuration signal and/or a second configuration signal, wherein the first configuration signal is used for enabling the reset operation of the first handshake signal; the second configuration signal is used to enable a reset operation on the second handshake signal.
9. The method according to claim 7 or 8, characterized in that the method further comprises:
before the first handshake signal is reset, delaying the first handshake signal between a bus and a peripheral; and/or
And delaying the second handshake signals between the bus and the processor before resetting the second handshake signals.
10. The method according to claim 7 or 8, characterized in that the method further comprises:
and prohibiting the instruction operation on the bus according to the reset control instruction, and allowing the instruction operation on the bus after a third set time.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410558296.9A CN105589821B (en) | 2014-10-20 | 2014-10-20 | A kind of device and method preventing bus deadlock |
| PCT/CN2015/078008 WO2016062057A1 (en) | 2014-10-20 | 2015-04-30 | Device and method for preventing bus from deadlocking, and computer storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410558296.9A CN105589821B (en) | 2014-10-20 | 2014-10-20 | A kind of device and method preventing bus deadlock |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105589821A true CN105589821A (en) | 2016-05-18 |
| CN105589821B CN105589821B (en) | 2019-03-12 |
Family
ID=55760201
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410558296.9A Active CN105589821B (en) | 2014-10-20 | 2014-10-20 | A kind of device and method preventing bus deadlock |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN105589821B (en) |
| WO (1) | WO2016062057A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109491856A (en) * | 2017-09-12 | 2019-03-19 | 中兴通讯股份有限公司 | Monitoring bus system, method and device |
| CN112783070A (en) * | 2021-01-20 | 2021-05-11 | 深圳市雷能混合集成电路有限公司 | Singlechip power-on processing method and device |
| CN116048849A (en) * | 2022-07-20 | 2023-05-02 | 荣耀终端有限公司 | Communication control method, device and equipment of I2C bus and storage medium |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118400224A (en) * | 2024-06-28 | 2024-07-26 | 宁波永新光学股份有限公司 | Half-duplex RS485 bus communication method for electric microscope |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101154210A (en) * | 2006-09-26 | 2008-04-02 | 联想(北京)有限公司 | Method and device for preventing dead lock of LPC bus line |
| CN101308477A (en) * | 2008-06-13 | 2008-11-19 | 华为技术有限公司 | System bus deadlock prevention method, device and on-chip system |
| EP2713680A1 (en) * | 2012-09-27 | 2014-04-02 | Vossloh-Schwabe Deutschland GmbH | Method for the determination of the availability of a bus-line and communication control unit |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6745273B1 (en) * | 2001-01-12 | 2004-06-01 | Lsi Logic Corporation | Automatic deadlock prevention via arbitration switching |
| CN102073613B (en) * | 2010-12-15 | 2013-05-08 | 创新科存储技术有限公司 | Device and method for removing deadlock of I<2>C (Inter-Integrated Circuit) bus |
| CN103810074B (en) * | 2012-11-14 | 2017-12-29 | 华为技术有限公司 | A kind of on-chip system chip and corresponding monitoring method |
-
2014
- 2014-10-20 CN CN201410558296.9A patent/CN105589821B/en active Active
-
2015
- 2015-04-30 WO PCT/CN2015/078008 patent/WO2016062057A1/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101154210A (en) * | 2006-09-26 | 2008-04-02 | 联想(北京)有限公司 | Method and device for preventing dead lock of LPC bus line |
| CN101308477A (en) * | 2008-06-13 | 2008-11-19 | 华为技术有限公司 | System bus deadlock prevention method, device and on-chip system |
| EP2713680A1 (en) * | 2012-09-27 | 2014-04-02 | Vossloh-Schwabe Deutschland GmbH | Method for the determination of the availability of a bus-line and communication control unit |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109491856A (en) * | 2017-09-12 | 2019-03-19 | 中兴通讯股份有限公司 | Monitoring bus system, method and device |
| CN109491856B (en) * | 2017-09-12 | 2022-08-02 | 中兴通讯股份有限公司 | Bus monitoring system, method and device |
| CN112783070A (en) * | 2021-01-20 | 2021-05-11 | 深圳市雷能混合集成电路有限公司 | Singlechip power-on processing method and device |
| CN112783070B (en) * | 2021-01-20 | 2024-05-07 | 深圳市雷能混合集成电路有限公司 | Singlechip power-on processing method and device |
| CN116048849A (en) * | 2022-07-20 | 2023-05-02 | 荣耀终端有限公司 | Communication control method, device and equipment of I2C bus and storage medium |
| CN116048849B (en) * | 2022-07-20 | 2023-11-07 | 荣耀终端有限公司 | Communication control method, device and equipment of I2C bus and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105589821B (en) | 2019-03-12 |
| WO2016062057A1 (en) | 2016-04-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105589821B (en) | A kind of device and method preventing bus deadlock | |
| CN110908841A (en) | I2C communication abnormity recovery method and device | |
| EP3203379B1 (en) | Hot swappable device and method | |
| TWI417731B (en) | Bus-handling device and method | |
| US8386908B2 (en) | Data transmission methods and universal serial bus host controllers utilizing the same | |
| TW200907688A (en) | Methods and apparatus of accessing memory units | |
| KR20170120559A (en) | Watchdog timer | |
| EP2832051A1 (en) | Method, device, and system for delaying packets during a network-triggered wake of a computing device | |
| CN112753197B (en) | Network management using wake-on-LAN | |
| CN105378650A (en) | Method and apparatus for controlling an operating mode of a processing module | |
| US20190146939A1 (en) | Communication device, communication method, program, and communication system | |
| CN106372019B (en) | A kind of processing method and timeout treatment device of system bus devices response timeout | |
| CN110543224B (en) | System and method for cooperatively resetting inner and outer multiple monitoring timers of master-slave MCU | |
| CN110609762B (en) | Method and device for preventing advanced high performance bus (AHB) from deadlock | |
| CN102025565B (en) | I2C bus communication detection method used among multiple devices | |
| US7506082B2 (en) | Data transferring system using USB and method thereof | |
| CN104834624B (en) | A kind of anti-interference method of iic bus interface | |
| CN101661318A (en) | System reset method, equipment, programmable logic device and CPU | |
| TW201820137A (en) | Device having restarting function | |
| JP6906369B2 (en) | Computer systems, their control methods, and programs | |
| CN118260223B (en) | Bus circuit of dual-master device, bus control method and device | |
| US7114022B2 (en) | Method for generating interrupt signal and media access controller utilizing the same | |
| CN118132301A (en) | Server and I2C bus hang dead self-recovery method, device and storage medium thereof | |
| CN104268081A (en) | Software running state monitoring method and device | |
| CN117251039A (en) | Equipment resetting method and device, storage medium and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20160518 Assignee: Xi'an Chris Semiconductor Technology Co. Ltd. Assignor: SHENZHEN ZTE MICROELECTRONICS TECHNOLOGY CO., LTD. Contract record no.: 2019440020036 Denomination of invention: Device and method for preventing buses against deadlock Granted publication date: 20190312 License type: Common License Record date: 20190619 |