CN105577181B

CN105577181B - A kind of DRAM clock synchronization system

Info

Publication number: CN105577181B
Application number: CN201610104422.2A
Authority: CN
Inventors: 刘成; 郭晓锋; 梁超
Original assignee: Xian Unilc Semiconductors Co Ltd
Current assignee: Xian Unilc Semiconductors Co Ltd
Priority date: 2016-02-26
Filing date: 2016-02-26
Publication date: 2018-10-16
Anticipated expiration: 2036-02-26
Also published as: CN105577181A

Abstract

The present invention discloses a kind of DRAM clock synchronization system, including receiver, DLL delay chains, DLL phase discriminators and DLL control circuits；Input clock signal line connects the first input end of the input terminal and DLL phase discriminators of receiver, the input terminal that the output end of receiver passes through DLL delay chains；Second input terminal of the output end connection DLL phase discriminators of DLL delay chains；The output end of DLL phase discriminators connects DLL delay chains by DLL control circuits.Present invention eliminates the feedback circuits that can cause synchronous error in the prior art, input clock and output clock dps are directly entered DLL phase discriminators, after DLL is locked, the rising edge alignment of the rising edge alignment of two input clocks of DLL phase discriminators, i.e. input clock and output clock.The present invention is not due to having feedback circuit, so the problem of delay time matching is also not present then meets the requirement of system clock synchronization as long as DLL can be locked correctly.

Description

A kind of DRAM clock synchronization system

Technical field

The present invention relates to DRAM technology field, more particularly to a kind of DRAM clock synchronization system.

Background technology

Refering to Figure 1, the operation principle that DRAM system clock synchronizes in the prior art is：

(X=0,1,2 ... n) and the rising edge alignment of dqs, i.e., by system requirements input clock and the dqX of output

T1+T2+T3+T4=N*TCK N are integer

Wherein, T1 is the delay time of receiver rcv, and T2 is the delay time of DLL delay chains, and T3 is the delay of Clock Tree Time, T4 are the delay times of transmitter OCD, and TCK is the clock cycle.If the rising of input clock and the dqX and dqs of output Along not being aligned, then will malfunction when system reads data in high-frequency work.

After DLL is locked, the rising edge of two input clocks of DLL phase discriminators is alignment, i.e.,

T2+T5=N*TCK

Wherein, T5 is the delay time of feedback circuit.If the delay time of feedback circuit

T5=T1+T3+T4

The requirement of system clock synchronization can so be met.

The considerations of for power consumption, feedback circuit are a simple copies to rcv, Clock Tree and OCD；So there are following Problem：If the voltage of DRAM system, temperature or technique change, the delay time of feedback circuit and the delay of real circuits Deviation will occur for the time, i.e.,

T5≠T1+T3+T4

Then the rising edge of input clock and the dqX and dqs of output are not aligned, and system reads data just in high-frequency work It can malfunction.

Invention content

The purpose of the present invention is to provide a kind of DRAM clock synchronization systems, to solve the above technical problems.

In order to solve the above-mentioned technical problem, the present invention adopts the following technical scheme that：

A kind of DRAM clock synchronization system, including receiver, DLL delay chains, DLL phase discriminators and DLL control circuits；Input Clock cable connects the first input end of the input terminal and DLL phase discriminators of receiver, the output end connection DLL delays of receiver The input terminal of chain；The output end of DLL delay chains connects Clock Tree, and the output end of Clock Tree connects several transmitter OCD；Several hairs The second input terminal for sending one output end in device OCD to connect DLL phase discriminators；The output end of DLL phase discriminators is controlled by DLL Circuit connects DLL delay chains.

Further, except a transmitter of the second input terminal of output end connection DLL phase discriminators in several transmitter OCD Outside OCD, the output end of remaining transmitter OCD is all connected with that there are one dummy loads.

Further, the size of dummy load is input to the increased load of institute in DLL phase discriminators equal to that will export clock.

Further, the load matched of several transmitter OCD.Compared with the existing technology, the present invention uses following skill Art scheme：

Compared with the existing technology, the invention has the advantages that：

Present invention eliminates the feedback circuits that can cause synchronous error in the prior art, by input clock and output clock Dqs is directly entered DLL phase discriminators, after DLL is locked, the rising edge alignment of two input clocks of DLL phase discriminators, that is, when inputting The rising edge alignment of clock and output clock.The present invention matched is asked due to not having feedback circuit so delay time is also not present Topic then meets the requirement of system clock synchronization as long as DLL can be locked correctly.Meanwhile the present invention has feedback relative to existing For the system of circuit, the accuracy higher of input clock and output rising edge clock alignment so that DRAM can be operated in ratio Under the higher frequency of the prior art, and it can ensure the stability and accuracy of work.

Further, present invention eliminates traditional feedback circuits, have effectively saved the area of DRAM.

Further, the present invention can increase a dummy load dummy on all dqX；The size etc. of the dummy load It is input to the increased load of caused dqs institutes in DLL phase discriminators in clock will be exported；Dqs can be eliminated in this way is sent directly into DLL Phase discriminator, the caused unmatched problem of output clock load.

Description of the drawings

Fig. 1 is existing DRAM clock synchronization system operation principle schematic diagram；

Fig. 2 is DRAM clock synchronization system operation principle schematic diagram of the present invention.

Specific implementation mode

It please refers to shown in Fig. 2, a kind of DRAM clock synchronization system of the present invention, including receiver rcv, DLL delay chain, clock Tree, DLL phase discriminators, DLL control circuits and several transmitter OCD.

Input clock signal line connects the first input end of receiver and DLL phase discriminators, and the output end of receiver passes through DLL Postpone the input terminal of chain link Clock Tree, the output end of Clock Tree connects several transmitter OCD；One in several transmitter OCD Second input terminal of a output end connection DLL phase discriminators；The output end of DLL phase discriminators connects DLL by DLL control circuits and prolongs Slow chain.DLL phase discriminators are used to compare the time difference of input clock and the rising edge of output clock dqs, and pass through DLL control circuit controls The length of DLL delay chains processed makes input clock and exports the rising edge alignment of clock dqs.

In the present invention, input clock and dqs are directly entered DLL phase discriminators, eliminate feedback circuit in the prior art.When After DLL lockings, the rising edge alignment of two input clocks of DLL phase discriminators, the i.e. rising edge pair of input clock and dqs and dqX Together.Due to there is no feedback circuit, so the problem of delay time matching is also not present, as long as DLL can be locked correctly, then meets The requirement that system clock synchronizes.

Since dqs can enter the input terminal of DLL phase discriminators, relative to original system, the load of dqs can increased, For the load matched of dqs and dqX, a dummy load dummy can be increased on all dqX；The size of the dummy load It is input to the increased load of caused dqs institutes in DLL phase discriminators equal to clock will be exported.

Claims

1. a kind of DRAM clock synchronization system, which is characterized in that controlled including receiver, DLL delay chains, DLL phase discriminators and DLL Circuit；

Input clock signal line connects the first input end of the input terminal and DLL phase discriminators of receiver, and the output end of receiver connects Connect the input terminal of DLL delay chains；The output end of DLL delay chains connects Clock Tree, and the output end of Clock Tree connects several transmitters OCD；

Second input terminal of one output end connection DLL phase discriminators in several transmitter OCD；

The output end of DLL phase discriminators connects DLL delay chains by DLL control circuits；

In several transmitter OCD in addition to output end connects a transmitter OCD of the second input terminal of DLL phase discriminators, remaining hair Sending the output end of device OCD to be all connected with, there are one dummy loads；

The size of dummy load is input to the increased load of institute in DLL phase discriminators equal to that will export clock；

The load matched of several transmitter OCD.