CN105576090B - The preparation method and LED epitaxial slice of LED epitaxial slice - Google Patents
The preparation method and LED epitaxial slice of LED epitaxial slice Download PDFInfo
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- CN105576090B CN105576090B CN201610045557.6A CN201610045557A CN105576090B CN 105576090 B CN105576090 B CN 105576090B CN 201610045557 A CN201610045557 A CN 201610045557A CN 105576090 B CN105576090 B CN 105576090B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract
The invention discloses a kind of preparation method of LED epitaxial slice and LED epitaxial slice, belong to technical field of semiconductors.Methods described includes：Substrate is provided；In the GaN layer of Grown one as low temperature buffer layer；The growth temperature of low temperature buffer layer is 530~560 DEG C；Another GaN layer is grown on low temperature buffer layer as high temperature buffer layer；The high temperature buffer layer includes the first high-temperature buffer sublayer and the second high-temperature buffer sublayer being sequentially laminated on the low temperature buffer layer；The growth temperature of the first high-temperature buffer sublayer is higher than the growth temperature of the second high-temperature buffer sublayer, and the growth temperature of the first high-temperature buffer sublayer is 1060~1090 DEG C, and the growth temperature of the second high-temperature buffer sublayer is 1030~1060 DEG C；And the growth rate of the first high-temperature buffer sublayer is slower than the growth rate of the second high-temperature buffer sublayer；Grow N-type layer, active layer, electronic barrier layer and P-type layer successively on the high temperature buffer layer, obtain LED epitaxial slice.
Description
Technical field
The present invention relates to technical field of semiconductors, the preparation method of more particularly to a kind of LED epitaxial slice and luminous
Diode epitaxial slice.
Background technology
Light emitting diode (English：Light Emitting Diode, abbreviation：LED) as a kind of efficient, environmental protection, green
New solid-state illumination light source, application is widely available rapidly, such as traffic lights, automobile interior exterior lamp, urban landscape
Illumination and cell phone back light source etc..
LED is to prepare LED chip.The existing method for preparing LED includes：First, with relatively low
Temperature (such as 500 DEG C~600 DEG C) is in the GaN layer of Grown one as low temperature buffer layer.Secondly, temperature is quickly raised,
One GaN layer is grown on low temperature buffer layer using higher temperature (such as 1060 DEG C~1100 DEG C) and is used as high temperature buffer layer.Then,
Grow N-type layer, active layer and P-type layer successively on high temperature buffer layer, obtain LED.
During the present invention is realized, inventor has found that prior art at least has problems with：Growing low temperature
, it is necessary to be rapidly heated to high growth temperature high temperature buffer layer after cushion.When being rapidly heated, the thermal stress formed on substrate is not
It can be released in time, warpage will occur for substrate.Warpage has greatly very much a negatively influencing to LED properties, for example wavelength is uniform
Property can be deteriorated, and antistatic effect can decline, and photoelectric properties can also be deteriorated.
The content of the invention
In order to alleviate warpage, the embodiments of the invention provide a kind of preparation method of LED epitaxial slice and luminous two
Pole pipe epitaxial wafer.The technical scheme is as follows：
On the one hand, there is provided a kind of preparation method of LED epitaxial slice, methods described include：
Substrate is provided；
A GaN layer is grown over the substrate as low temperature buffer layer；The growth temperature of the low temperature buffer layer be 530~
560℃；
Another GaN layer is grown on the low temperature buffer layer as high temperature buffer layer；The high temperature buffer layer is included successively
The the first high-temperature buffer sublayer and the second high-temperature buffer sublayer being layered on the low temperature buffer layer；First high-temperature buffer
The growth temperature of layer is higher than the growth temperature of the second high-temperature buffer sublayer, the growth temperature of the first high-temperature buffer sublayer
For 1060~1090 DEG C, the growth temperature of the second high-temperature buffer sublayer is 1030~1060 DEG C；And first high temperature delays
The growth rate of punching pin layer is slower than the growth rate of the second high-temperature buffer sublayer；
Grow N-type layer, active layer, electronic barrier layer and P-type layer successively on the high temperature buffer layer, obtain light-emitting diodes
Pipe epitaxial wafer, the growth rate of the second high-temperature buffer sublayer are the 1.5 of the growth rate of the first high-temperature buffer sublayer
~3 times.
If the growth rate of the second high-temperature buffer sublayer is less than 1.5 times of the growth rate of the first high-temperature buffer sublayer, just
It can grow slow because this layer of temperature is relatively low and influence crystal mass.If the growth rate of the second high-temperature buffer sublayer is more than first
3 times of the growth rate of high-temperature buffer sublayer, crystal mass will be influenceed because of the defects of too fast generation is more is growed.
Optionally, the growth pressure of the first high-temperature buffer sublayer is higher than the growth pressure of the second high-temperature buffer sublayer
Power, the growth pressure of the first high-temperature buffer sublayer are 200~350Torr, the growth pressure of the second high-temperature buffer sublayer
Power is 100~200Torr.
The growth pressure of second high-temperature buffer sublayer is higher than by the growth pressure of the first high-temperature buffer sublayer, then, first
The growth pressure of first high-temperature buffer of growth is of a relatively high, can further improve the crystal mass of epitaxial wafer.Specifically, it is raw
When long pressure is higher, GaN will be beneficial to and carry out three dimensional growth, make the size on GaN islands increase, and the reduction of island density, the merging on island are prolonged
Late, therefore the density of line defect can be reduced, improves the crystal mass of GaN epitaxy.The life of the second high-temperature buffer sublayer grown afterwards
Long pressure is relatively low, then, after the first high-temperature buffer sublayer has been grown, the high-temperature buffer sublayer of growth regulation two need to be depressured.
Decompression growth can be beneficial to GaN two-dimensional growths, and proceed by stable periodic swinging growth GaN lattices；Meanwhile decompression is logical
The gas for crossing filling in quick abstraction reaction chamber realizes that, when gas is quickly taken away inside reaction chamber, epitaxial wafer is relative
Bear gas and quickly taken away caused pressure, the pressure energy flattens epitaxial wafer, therefore can further alleviate extension
The change of piece warpage is excessive.
Optionally, the thickness of the first high-temperature buffer sublayer is 1~1.5 micron；The second high-temperature buffer sublayer
Thickness is 0.2~0.5 micron.
If the thickness of the first high-temperature buffer sublayer be less than 1 μm, can due to thickness is partially thin and influence merge, fill and lead up effect.If
The thickness of first high-temperature buffer sublayer is more than 1.5 μm, also due to the thicker increase warpage of thickness, can also increase total growth time,
Cost increase.If the thickness of the second high-temperature buffer sublayer be less than 0.2 μm, can due to thickness is too thin and do not have release stress so as to
Alleviate warpage and change excessive effect., can be relatively low again due to this layer of temperature if the thickness of the second high-temperature buffer sublayer is more than 0.5 μm
Grow very thick and influence crystal mass.
Optionally, the high temperature buffer layer also includes the third high temperature buffering being layered in the second high-temperature buffer sublayer
Sublayer；The growth temperature of third high temperature buffering sublayer is higher than the growth temperature of the first high-temperature buffer sublayer, and described the
The growth pressure of three high-temperature buffer sublayers is identical with the growth pressure of the first high-temperature buffer sublayer, the third high temperature buffering
The growth rate of sublayer is identical with the growth rate of the first high-temperature buffer sublayer.
Growth temperature of the growth temperature higher than the first high-temperature buffer sublayer of sublayer, third high temperature are buffered by third high temperature
The growth pressure of buffering sublayer is identical with the growth pressure of the first high-temperature buffer sublayer, and third high temperature buffers the growth rate of sublayer
It is identical with the growth rate of the first high-temperature buffer sublayer, so, compared to the second high-temperature buffer sublayer, third high temperature buffering sublayer
Growth pressure it is higher, growth temperature is higher, growth rate is slower；So, after the second high-temperature buffer sublayer has been grown, need
Boost and heat up and slow growth third high temperature buffering sublayer, boosting and heating are advantageous to lift crystal mass, this is to the
The poor growth quality of two high-temperature buffer sublayers has carried out certain compensation, finally cause this layer to fill and lead up effect preferable, prevent
The defects of more, upwardly extends.
Optionally, the growth temperature of the third high temperature buffering sublayer is 1070~1100 DEG C.
If the growth temperature of third high temperature buffering sublayer is less than 1070 DEG C, would not play to the second high-temperature buffer sublayer
The effect that poor growth quality compensates, will not also the defects of more be prevented to upwardly extend, if third high temperature buffers sublayer
Growth temperature be higher than 1100 DEG C, the more surface defect caused by temperature height can be produced, such as hexagonal, bright spot.
Optionally, the thickness of the third high temperature buffering sublayer is 0.5~1 micron.
If third high temperature buffering sublayer thickness be less than 0.5 μm, can due to thickness is partially thin and it is high to be unable to effective compensation second
The poor crystal mass of temperature buffering sublayer.If the thickness of third high temperature buffering sublayer is more than 1 μm, can be higher due to this layer of temperature
Risk that is thicker and producing surface defect and increase growth time are grown again.
Optionally, in third high temperature buffering sublayer mixed with Si, in the third high temperature buffering sublayer mixed with Si
Concentration be less than the N-type layer in mixed with Si concentration.
Sublayer is buffered by third high temperature and adulterates Si, the generation of defect can be stopped, improve crystal mass.
Optionally, in third high temperature buffering sublayer mixed with Si concentration be 5 × 1017/cm3~5 × 1018/cm3。
On the other hand, there is provided a kind of LED epitaxial slice, the LED epitaxial slice is by foregoing preparation side
It is prepared by method.
The beneficial effect that technical scheme provided in an embodiment of the present invention is brought is：
The growth temperature of second high-temperature buffer sublayer is higher than by the growth temperature of the first high-temperature buffer sublayer, and first is high
The growth rate of temperature buffering sublayer is slower than the growth rate of the second high-temperature buffer sublayer；So, the first high-temperature buffer first grown
The speed of growth it is relatively slow and growth temperature is higher, so, the first high-temperature buffer sublayer can play the work of conventional high-temperature cushion
With, that is, improve epitaxial wafer crystal mass.Specifically, when growth temperature is higher, mobility adds between causing reactant molecule
Cause that GaN material internal flaw is reduced, that is, improves crystal mass soon；When the speed of growth is slower, also filled and led up beneficial to GaN,
And start periodic swinging growth GaN lattices, improve crystal mass.The speed of growth of the second high-temperature buffer sublayer grown afterwards compared with
Fast and growth temperature is relatively low, and so, after the first high-temperature buffer sublayer has been grown, need to cool the high-temperature buffer of growth regulation two
Layer.Cooling can then discharge the stress that high growth temperature is brought, and alleviate warpage and change excessive and influence follow-up growth；And fast fast-growing
It is long then can prevent from producing the defects of excessive during low-temperature epitaxy and influenceing total crystal mass.
Brief description of the drawings
Technical scheme in order to illustrate the embodiments of the present invention more clearly, make required in being described below to embodiment
Accompanying drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for
For those of ordinary skill in the art, on the premise of not paying creative work, other can also be obtained according to these accompanying drawings
Accompanying drawing.
Fig. 1 is a kind of flow chart of the preparation method for LED epitaxial slice that first embodiment of the invention provides；
Fig. 2 is a kind of flow chart of the preparation method for LED epitaxial slice that second embodiment of the invention provides；
Fig. 3 is a kind of structural representation for LED epitaxial slice that third embodiment of the invention provides.
Embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to embodiment party of the present invention
Formula is described in further detail.
Fig. 1 shows a kind of preparation method for LED epitaxial slice that first embodiment of the invention provides, referring to figure
1, this method comprises the following steps：
Step 101, provide substrate.
Wherein, substrate can be Si, SiC, sapphire, ZnO, GaAs, GaP, MgO, Cu or W substrate.
Step 102, in the GaN layer of Grown one as low temperature buffer layer.
Wherein the growth temperature of low temperature buffer layer is 530~560 DEG C.
Step 103, another GaN layer is grown as high temperature buffer layer on low temperature buffer layer.
Wherein high temperature buffer layer includes the first high-temperature buffer sublayer and the second high temperature being sequentially laminated on low temperature buffer layer
Buffer sublayer.The growth temperature of first high-temperature buffer sublayer is higher than the growth temperature of the second high-temperature buffer sublayer, and the first high temperature delays
The growth temperature of punching pin layer is 1060~1090 DEG C, and the growth temperature of the second high-temperature buffer sublayer is 1030~1060 DEG C；And the
The growth rate of one high-temperature buffer sublayer is slower than the growth rate of the second high-temperature buffer sublayer.
Step 104, grow N-type layer, active layer, electronic barrier layer and P-type layer successively on high temperature buffer layer, lighted
Diode epitaxial slice.
When realizing, metallo-organic compound chemical gaseous phase deposition (English can be used：Metal Organic
Chemical Vapor Deposition, abbreviation：MOCVD) mode low temperature growth buffer layer, high temperature buffer layer, N-type layer, active
Layer, electronic barrier layer and P-type layer.
The embodiment of the present invention is higher than the growth of the second high-temperature buffer sublayer by the growth temperature of the first high-temperature buffer sublayer
Temperature, and the growth rate of the first high-temperature buffer sublayer is slower than the growth rate of the second high-temperature buffer sublayer；So, first grow
The speed of growth of first high-temperature buffer is relatively slow and growth temperature is higher, and so, the first high-temperature buffer sublayer can play traditional height
The effect of warm cushion, that is, improve the crystal mass of epitaxial wafer.Specifically, when growth temperature is higher, reactant molecule can be caused
Between mobility accelerate and cause GaN material internal flaw reduce, that is, improve crystal mass；When the speed of growth is slower, also it is beneficial to
GaN is filled and led up, and starts periodic swinging growth GaN lattices, improves crystal mass.The the second high-temperature buffer sublayer grown afterwards
The speed of growth it is very fast and growth temperature is relatively low, so, after the first high-temperature buffer sublayer has been grown, need to cool growth regulation two
High-temperature buffer sublayer.Cooling can then discharge the stress that high growth temperature is brought, and alleviate warpage and change excessive and influence follow-up life
It is long；And fast-growth can then prevent from producing the defects of excessive during low-temperature epitaxy and influenceing total crystal mass.
Fig. 2 shows a kind of preparation method for LED epitaxial slice that second embodiment of the invention provides.In this reality
Apply in example, exemplified by LED epitaxial slice will be prepared in a manner of MOCVD, the preparation method of first embodiment is situated between in detail
Continue.Referring to Fig. 2, this method comprises the following steps：
Step 201, provide substrate.
In this embodiment, substrate can be Sapphire Substrate.
In the present embodiment, using MOCVD low temperature growth buffers layer, high temperature buffer layer, N-type layer, active layer, electronic blocking
When layer and P-type layer, high-purity H can be used2(hydrogen) or high-purity N2(nitrogen) or high-purity H2And high-purity N2Mixed gas as carry
Gas, high-purity N H3As nitrogen source, trimethyl gallium (TMGa) and triethyl-gallium (TEGa) are used as gallium source, trimethyl indium (TMIn) conduct
Indium source, silane (SiH4) N type dopant and silicon source are used as, trimethyl aluminium (TMAl) is used as silicon source, two luxuriant magnesium (CP2Mg) it is used as p-type
Dopant.
Step 202, in the GaN layer of Grown one as low temperature buffer layer.
Wherein the growth temperature of low temperature buffer layer is 530~560 DEG C, and growth pressure is 200~500Torr, thickness 15
~30nm.
Specifically, on the long crystal face for being advantageous to crystal growth of low temperature buffer layer growth on a sapphire substrate.
As optional embodiment, before low temperature growth buffer layer, this step 202 also includes：First substrate is carried out
Pretreatment.The pretreatment mode includes：In a hydrogen atmosphere, high-temperature baking substrate.Wherein, baking temperature can be 1000~
1100 DEG C, baking pressure can be 200~500Torr, and baking time can be 5~6 minutes.
Specifically, MOCVD device can be used by toasting the equipment of substrate, and the model of MOCVD device can be Veeco C4
Or Veeco K465i.
Step 203, the high-temperature buffer sublayer of growth regulation one and the second high-temperature buffer sublayer successively on low temperature buffer layer.
Wherein, the growth temperature of the first high-temperature buffer sublayer is higher than the growth temperature of the second high-temperature buffer sublayer.
The growth temperature of first high-temperature buffer sublayer is 1060~1090 DEG C.If the growth temperature of the first high-temperature buffer sublayer
Less than 1060 degree, the mobility between reactant molecule can be influenceed and cause the increase of GaN material internal flaw, that is, reduce crystal matter
Amount.If the growth temperature of the first high-temperature buffer sublayer is more than 1090 DEG C, low temperature buffer layer can be baked because growth temperature is too high.
Preferably, the growth temperature of the first high-temperature buffer sublayer is 1065-1090 DEG C, so, both can guarantee that crystal mass was not deteriorated,
Low temperature buffer layer will not be baked.
The growth temperature of second high-temperature buffer sublayer is 1030~1060 DEG C.If the growth temperature of the second high-temperature buffer sublayer
Less than 1030 DEG C, crystal mass can be had a strong impact on because growth temperature is too low.If the growth temperature of the second high-temperature buffer sublayer
Higher than 1060 DEG C, release stress can not be had due to temperature drift again, so as to reduce the effect of warpage.Preferably, second is high
The growth temperature of temperature buffering sublayer is 1035-1055 DEG C, can both play the effect of release stress relief warpage, again will not be because of
Temperature is too low and influences crystal mass.
Further, the growth rate of the first high-temperature buffer sublayer is slower than the growth rate of the second high-temperature buffer sublayer.
Optionally, the growth rate of the second high-temperature buffer sublayer is the 1.5~3 of the growth rate of the first high-temperature buffer sublayer
Times., will be due to if the growth rate of the second high-temperature buffer sublayer is less than 1.5 times of growth rate of the first high-temperature buffer sublayer
This layer of temperature is relatively low and grows slow and influences crystal mass.If the growth rate of the second high-temperature buffer sublayer is delayed more than the first high temperature
3 times of the growth rate of punching pin layer, crystal mass will be influenceed because of the defects of too fast generation is more is growed.Preferably,
The growth rate of two high-temperature buffer sublayers is 1.6-2.8 times of the growth rate of the first high-temperature buffer sublayer, such growth speed
Rate can effective crystal mass.
Optionally, the growth pressure of the first high-temperature buffer sublayer be higher than the second high-temperature buffer sublayer growth pressure, first
The growth pressure of high-temperature buffer sublayer is 200~350Torr, the growth pressure of the second high-temperature buffer sublayer for 100~
200Torr。
If the growth pressure of the first high-temperature buffer sublayer is less than 200Torr, larger volume crystalline substance can be produced by just not having high pressure
The effect of kind, again can be because pressure is too high to influence follow-up conjunction if the growth pressure of the first high-temperature buffer sublayer is more than 350Torr
And, fill and lead up effect and cause defect.Preferably, the growth pressure of the first high-temperature buffer sublayer is 250-300Torr, can both be risen
To the effect of high pressure, defect will not be caused to cause poor crystal quality again.
If the growth pressure of the second high-temperature buffer sublayer is less than 100Torr, will cause because the too low growth of pressure is too thin
Two-dimensional growth effect is poor.If the growth pressure of the second high-temperature buffer sublayer is more than 200Torr, have can due to pressure it is too high without
Beneficial to two dimensional mode, merge, fill and lead up.Preferably, the growth pressure of the second high-temperature buffer sublayer is 100-
150Torr, can both play the effect that low pressure is beneficial to two-dimensional growth, be beneficial to merge again, fill and lead up and start stable periodicity and shake
Swing.
The growth pressure of second high-temperature buffer sublayer is higher than by the growth pressure of the first high-temperature buffer sublayer, then, first
The growth pressure of first high-temperature buffer of growth is of a relatively high, can further improve the crystal mass of epitaxial wafer.Specifically, it is raw
When long pressure is higher, GaN will be beneficial to and carry out three dimensional growth, make the size on GaN islands increase, and the reduction of island density, the merging on island are prolonged
Late, therefore the density of line defect can be reduced, improves the crystal mass of GaN epitaxy.The life of the second high-temperature buffer sublayer grown afterwards
Long pressure is relatively low, then, after the first high-temperature buffer sublayer has been grown, the high-temperature buffer sublayer of growth regulation two need to be depressured.
Decompression growth can be beneficial to GaN two-dimensional growths, and proceed by stable periodic swinging growth GaN lattices；Meanwhile decompression is logical
The gas for crossing filling in quick abstraction reaction chamber realizes that, when gas is quickly taken away inside reaction chamber, epitaxial wafer is relative
Bear gas and quickly taken away caused pressure, the pressure energy flattens epitaxial wafer, therefore can further alleviate extension
The change of piece warpage is excessive.
Wherein, the thickness of the first high-temperature buffer sublayer can be 1~1.5 micron；The thickness of second high-temperature buffer sublayer can
Think 0.2~0.5 micron.
If the thickness of the first high-temperature buffer sublayer be less than 1 μm, can due to thickness is partially thin and influence merge, fill and lead up effect.If
The thickness of first high-temperature buffer sublayer is more than 1.5 μm, also due to the thicker increase warpage of thickness, can also increase total growth time,
Cost increase.Preferably, the thickness of the first high-temperature buffer sublayer is 0.8-1.3 μm, and such thickness is both beneficial to merge, filled and led up,
Also warpage will not be increased.
If the thickness of the second high-temperature buffer sublayer be less than 0.2 μm, can due to thickness is too thin and do not have release stress so as to
Alleviate warpage and change excessive effect., can be relatively low again due to this layer of temperature if the thickness of the second high-temperature buffer sublayer is more than 0.5 μm
Grow very thick and influence crystal mass.Preferably, the thickness of the second high-temperature buffer sublayer is 0.25-0.45 μm, can both be ensured
The effect of stress is discharged, does not interfere with crystal mass again.
Wherein, the first high-temperature buffer sublayer and the second high-temperature buffer sublayer are GaN layer.
As optional embodiment, after the second high-temperature buffer sublayer has been grown, the step 203 also includes：
A GaN layer is grown in two high-temperature buffer sublayers and buffers sublayer as third high temperature.
Wherein, the growth temperature of third high temperature buffering sublayer is higher than the growth temperature of the first high-temperature buffer sublayer.
Optionally, the growth temperature of third high temperature buffering sublayer is 1070~1100 DEG C.If third high temperature buffering sublayer
Growth temperature is less than 1070 DEG C, would not play the effect compensated to the poor growth quality of the second high-temperature buffer sublayer
It fruit, will not also prevent the defects of more from upwardly extending, if the growth temperature of third high temperature buffering sublayer is higher than 1100 DEG C, can produce
The more surface defect caused by temperature height, such as hexagonal, bright spot.Preferably, the growth temperature of third high temperature buffering sublayer is
1075-1095 DEG C, the crystal mass of the second high-temperature buffer sublayer growth had both been can compensate for, will not produce surface because temperature is high again
Defect.
Further, the growth pressure of third high temperature buffering sublayer is identical with the growth pressure of the first high-temperature buffer sublayer,
And the growth rate of third high temperature buffering sublayer is identical with the growth rate of the first high-temperature buffer sublayer.
Specifically, the growth pressure of third high temperature buffering sublayer is 200-350Torr.If third high temperature buffers the life of sublayer
Long pressure is less than 200Torr, this layer can be caused to grow thin and cover the defects of not living the second high-temperature buffer sublayer, if third high temperature is delayed
The growth pressure of punching pin layer is more than 350Torr, can increase warpage due to growing too thick again, also due to pressure height is again sticking up
Qu Bian great.Preferably, the growth pressure of third high temperature buffering sublayer is 250-300Torr, can both ensure that suitable thickness covered
Defect, ensure that warpage will not increase again.
Growth temperature of the growth temperature higher than the first high-temperature buffer sublayer of sublayer, third high temperature are buffered by third high temperature
The growth pressure of buffering sublayer is identical with the growth pressure of the first high-temperature buffer sublayer, and third high temperature buffers the growth rate of sublayer
It is identical with the growth rate of the first high-temperature buffer sublayer, so, compared to the second high-temperature buffer sublayer, third high temperature buffering sublayer
Growth pressure it is higher, growth temperature is higher, growth rate is slower；So, after the second high-temperature buffer sublayer has been grown, need
Boost and heat up and slow growth third high temperature buffering sublayer, boosting and heating are advantageous to lift crystal mass, this is to the
The poor growth quality of two high-temperature buffer sublayers has carried out certain compensation, finally cause this layer to fill and lead up effect preferable, prevent
The defects of more, upwardly extends.
Optionally, the thickness of third high temperature buffering sublayer is 0.5~1 micron.If the thickness of third high temperature buffering sublayer is small
In 0.5 μm, the poor crystal mass of effective compensation the second high-temperature buffer sublayer can be unable to because thickness is partially thin.If the 3rd is high
The thickness of temperature buffering sublayer is more than 1 μm, can be because this layer of temperature is higher and growth risk that is thicker and producing surface defect and increasing
Add growth time.Preferably, the thickness of third high temperature buffering sublayer is 0.6-0.8 μm, can the high-temperature buffer of effective compensation second
The crystal mass of layer and the generation risk for avoiding surface defect.
Optionally, mixed with Si in third high temperature buffering sublayer, in third high temperature buffering sublayer mixed with Si concentration be less than N
In type layer mixed with Si concentration.
Optionally, third high temperature buffering sublayer in mixed with Si concentration be 5 × 1017/cm3~5 × 1018/cm3。
Sublayer is buffered by third high temperature and adulterates Si, the generation of defect can be stopped, improve crystal mass.
Step 204, grow N-type layer in the second high-temperature buffer sublayer.
N-type layer can be to mix Si GaN layer, and thickness can be 2-3 microns.
When growing N-type layer, growth temperature can be 1000-1100 DEG C, and growth pressure can be 200-300Torr.
If it should be noted that grown third high temperature buffering sublayer in step 203, this step 204 includes：
N-type layer is grown in three high-temperature buffer sublayers.
Step 205, active layer is grown in N-type layer.
Active layer can include the InGaN well layer and GaN barrier layer of some alternating growths.The layer of InGaN well layer and GaN barrier layer
Number can be 11-13.
Wherein, the thickness of InGaN well layer can be 2-3nm, and the thickness of GaN barrier layer can be 8-11nm., InGaN well layer
Gross thickness with GaN barrier layer can be 130-160nm.
Specifically, when growing active layer, growth pressure can be 200Torr.When growing InGaN well layer, growth temperature is
760-780℃.When growing GaN barrier layer, growth temperature is 860-890 DEG C.
Step 206, electronic barrier layer is grown on active layer.
Optionally, electronic barrier layer is to mix Al, mix Mg AlyGa1-yN (y is 0.15~0.25) layer, electronic barrier layer
Thickness can be 30-50nm.
Specifically, when growing electronic barrier layer, growth temperature can be 930-970 DEG C, and growth pressure can control
100Torr。
Step 207, the growing P-type layer on electronic barrier layer.
Optionally, P-type layer is doping Mg GaN layer, and the thickness of P-type layer can be 60-100nm.
Specifically, during growing P-type layer, growth temperature can be 940-970 DEG C, and growth pressure can be controlled in 200-
500Torr。
Step 208, activation P-type layer, obtain LED epitaxial slice.
The activation method of P-type layer includes：In a nitrogen atmosphere, P-type layer is toasted.Baking time can be 20-30 minutes, dry
Roasting temperature can be 650-750 DEG C.
It should be noted that activation P-type layer is mainly the Mg for activating and being adulterated in P-type layer, Mg is set to be produced after activating more
Hole, avoid causing Ohmic contact difference to cause chip brightness low and the high situation of voltage due to not activating.
Testing crew obtains two panels epitaxial wafer, the first sample and the second sample respectively.The high temperature buffer layer of first sample is
Grown using conventional high-temperature buffer growth method, the high temperature buffer layer of the second sample is the growth side provided using the present embodiment
Method grows.Thereafter 110nm tin indium oxide metal oxygen is plated under identical process conditions to the first sample and the second sample respectively
Compound (English：Indium Tin Oxides, abbreviation：ITO) layer, 120nm Cr/Pt/Au electrodes and 40nm SiO2Protection
Layer, and the core particles by the first sample after processing and the second sample grinding and cutting into 305 μm * 635 μm (12mi*25mil) respectively
With the core particles of 229 μm * 559 μm (9mi*22mil) totally two kinds of core particles.Then the first sample after treatment and the phase of the second sample
200 crystal grain are each selected with position, under identical process conditions, are packaged into white light LEDs.Finally existed respectively using integrating sphere
Test comes from the crystal grain of the first sample and comes from the photoelectricity of the crystal grain of the second sample under the conditions of driving current 120mA and 60mA
Performance.Result of the test shows that two kinds of crystal grain for coming from the second sample are compared with two kinds of crystal grain for coming from the first sample, light intensity
It is obviously improved respectively under 120mA and 60mA driving currents, antistatic effect is significantly raised, and this just illustrates to use the present embodiment
The structure crystal quality of the method growth of offer is preferable.
Fig. 3 shows a kind of LED epitaxial slice that third embodiment of the invention provides, the LED epitaxial
Piece uses the preparation method provided such as first embodiment or second embodiment to be prepared.Referring to Fig. 3, the LED epitaxial
Piece includes substrate 1 and stacks gradually low temperature buffer layer 2 on substrate 1, high temperature buffer layer 3, N-type layer 4, active layer 5, electricity
Sub- barrier layer 6 and P-type layer 7.
Wherein, high temperature buffer layer 3 includes the first high-temperature buffer sublayer 311 and the second high-temperature buffer sublayer 312.High-temperature buffer
Layer 3 can also include the third high temperature buffering sublayer 313 being layered in the second high-temperature buffer sublayer 312.
First high-temperature buffer sublayer 311 uses relatively-high temperature high pressure growth mode, and the second high-temperature buffer sublayer 312 is using low
Pressure, low temperature, fast-growth mode, third high temperature buffering sublayer 313 use relatively-high temperature high pressure and bradyauxesis mode.Wherein
The growth pressure of one high-temperature buffer sublayer 311 and third high temperature buffering sublayer 313 is higher than the growth of the second high-temperature buffer sublayer 312
Pressure, the growth temperature of third high temperature buffering sublayer 313 is higher than the growth temperature of the first high-temperature buffer sublayer 311 and higher than second
The growth temperature of high-temperature buffer sublayer 312；The thickness of first high-temperature buffer sublayer 311 is more than third high temperature buffering sublayer 313
The thickness of thickness and the second high-temperature buffer sublayer 312；The speed of growth of second high-temperature buffer sublayer 312 is higher than the first high-temperature buffer
The speed of growth of sublayer 311 and third high temperature buffering sublayer 313.
Optionally, the growth pressure of the first high-temperature buffer sublayer 311 and third high temperature buffering sublayer 313 is 200-
350Torr, the growth pressure of the second high-temperature buffer sublayer 312 is 100-200Torr.Preferably, the first high-temperature buffer sublayer 311
Growth pressure with third high temperature buffering sublayer 313 is 250-300Torr.The growth pressure of second high-temperature buffer sublayer 312 is
100-150Torr。
Optionally, the growth temperature of the first high-temperature buffer sublayer 311 is 1060-1090 DEG C, the second high-temperature buffer sublayer 312
Growth temperature be 1030-1060 DEG C, third high temperature buffering sublayer 313 growth temperature be 1070-1100 DEG C.Preferably,
The growth temperature of one high-temperature buffer sublayer 311 is 1065-1090 DEG C, and the growth temperature of the second high-temperature buffer sublayer 312 is 1035-
1055 DEG C, the growth temperature of third high temperature buffering sublayer 313 is 1075-1095 DEG C.
Optionally, the thickness of the first high-temperature buffer sublayer 311 is 1-1.5 μm, and the thickness of the second high-temperature buffer sublayer 312 is
0.2-0.5 μm, the thickness of third high temperature buffering sublayer 313 is 0.5-1 μm.Preferably, the thickness of the first high-temperature buffer sublayer 311
For 0.8-1.3 μm, the thickness of the second high-temperature buffer sublayer 312 is 0.25-0.45 μm, and third high temperature buffers the thickness of sublayer 313
For 0.6-0.8 μm.
Optionally, the speed of growth of the second high-temperature buffer sublayer 312 is that the first high-temperature buffer sublayer 311 and third high temperature are delayed
1.5-3 times of punching pin layer 313.Preferably, the speed of growth of the second high-temperature buffer sublayer 312 is the first high-temperature buffer sublayer 311
With 1.6-2.8 times of third high temperature buffering sublayer 313.
Wherein, the first high-temperature buffer sublayer 311, the second high-temperature buffer sublayer 312 are intrinsic GaN layers, and third high temperature is delayed
Punching pin layer 313 can be the GaN layer for adulterating a small amount of Si.
The embodiment of the present invention is higher than the growth of the second high-temperature buffer sublayer by the growth temperature of the first high-temperature buffer sublayer
Temperature, and the growth rate of the first high-temperature buffer sublayer is slower than the growth rate of the second high-temperature buffer sublayer；So, first grow
The speed of growth of first high-temperature buffer is relatively slow and growth temperature is higher, and so, the first high-temperature buffer sublayer can play traditional height
The effect of warm cushion, that is, improve the crystal mass of epitaxial wafer.Specifically, when growth temperature is higher, reactant molecule can be caused
Between mobility accelerate and cause GaN material internal flaw reduce, that is, improve crystal mass；When the speed of growth is slower, also it is beneficial to
GaN is filled and led up, and starts periodic swinging growth GaN lattices, improves crystal mass.The the second high-temperature buffer sublayer grown afterwards
The speed of growth it is very fast and growth temperature is relatively low, so, after the first high-temperature buffer sublayer has been grown, need to cool growth regulation two
High-temperature buffer sublayer.Cooling can then discharge the stress that high growth temperature is brought, and alleviate warpage and change excessive and influence follow-up life
It is long；And fast-growth can then prevent from producing the defects of excessive during low-temperature epitaxy and influenceing total crystal mass.
The foregoing is only presently preferred embodiments of the present invention, be not intended to limit the invention, it is all the present invention spirit and
Within principle, any modification, equivalent substitution and improvements made etc., it should be included in the scope of the protection.
Claims (9)
1. a kind of preparation method of LED epitaxial slice, it is characterised in that methods described includes：
Substrate is provided；
A GaN layer is grown over the substrate as low temperature buffer layer；The growth temperature of the low temperature buffer layer is 530~560
℃；
Another GaN layer is grown on the low temperature buffer layer as high temperature buffer layer；The high temperature buffer layer includes stacking gradually
The first high-temperature buffer sublayer and the second high-temperature buffer sublayer on the low temperature buffer layer；The first high-temperature buffer sublayer
Growth temperature is higher than the growth temperature of the second high-temperature buffer sublayer, and the growth temperature of the first high-temperature buffer sublayer is
1060~1090 DEG C, the growth temperature of the second high-temperature buffer sublayer is 1030~1060 DEG C；And first high-temperature buffer
The growth rate of sublayer is slower than the growth rate of the second high-temperature buffer sublayer；
Grow N-type layer, active layer, electronic barrier layer and P-type layer successively on the high temperature buffer layer, obtain outside light emitting diode
Prolong piece, the growth rate of the second high-temperature buffer sublayer is the 1.5~3 of the growth rate of the first high-temperature buffer sublayer
Times.
2. according to the method for claim 1, it is characterised in that the growth pressure of the first high-temperature buffer sublayer is higher than institute
State the growth pressure of the second high-temperature buffer sublayer, the growth pressure of the first high-temperature buffer sublayer is 200~350Torr, institute
The growth pressure for stating the second high-temperature buffer sublayer is 100~200Torr.
3. according to the method for claim 1, it is characterised in that the thickness of the first high-temperature buffer sublayer is 1~1.5 micro-
Rice；The thickness of the second high-temperature buffer sublayer is 0.2~0.5 micron.
4. according to the method for claim 1, it is characterised in that the high temperature buffer layer is also high including being layered in described second
Third high temperature buffering sublayer in temperature buffering sublayer；The growth temperature of the third high temperature buffering sublayer is higher than first high temperature
Buffer the growth temperature of sublayer, the growth pressure of the third high temperature buffering sublayer and the growth of the first high-temperature buffer sublayer
Pressure is identical, and the growth rate of the third high temperature buffering sublayer is identical with the growth rate of the first high-temperature buffer sublayer.
5. according to the method for claim 4, it is characterised in that the growth temperature of the third high temperature buffering sublayer is 1070
~1100 DEG C.
6. according to the method for claim 4, it is characterised in that the thickness of the third high temperature buffering sublayer is micro- for 0.5~1
Rice.
7. according to the method for claim 4, it is characterised in that mixed with Si in third high temperature buffering sublayer, described the
In three high-temperature buffer sublayers mixed with Si concentration be less than the N-type layer in mixed with Si concentration.
8. according to the method for claim 7, it is characterised in that in third high temperature buffering sublayer mixed with Si concentration
For 5 × 1017/cm3~5 × 1018/cm3。
9. a kind of LED epitaxial slice, it is characterised in that the LED epitaxial slice in claim 1 to 8 by appointing
It is prepared by the preparation method of the LED epitaxial slice described in one.
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| CN1677697A (en) * | 2004-03-29 | 2005-10-05 | 炬鑫科技股份有限公司 | Epitaxial structure of gallium nitride series compound semiconductor and mfg. method |
| CN104037287A (en) * | 2014-06-10 | 2014-09-10 | 广州市众拓光电科技有限公司 | LED epitaxial wafer grown on Si substrate and preparation method thereof |
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| KR101384071B1 (en) * | 2009-03-20 | 2014-04-10 | 주식회사 엘지실트론 | Nitride semiconductor substrate, method for fabricating the substrate and light emitting diode including the substrate |
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| CN1677697A (en) * | 2004-03-29 | 2005-10-05 | 炬鑫科技股份有限公司 | Epitaxial structure of gallium nitride series compound semiconductor and mfg. method |
| CN104037287A (en) * | 2014-06-10 | 2014-09-10 | 广州市众拓光电科技有限公司 | LED epitaxial wafer grown on Si substrate and preparation method thereof |
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