CN105575935A - CMOS driver wafer level package and manufacturing method thereof - Google Patents
CMOS driver wafer level package and manufacturing method thereof Download PDFInfo
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- CN105575935A CN105575935A CN201610104842.0A CN201610104842A CN105575935A CN 105575935 A CN105575935 A CN 105575935A CN 201610104842 A CN201610104842 A CN 201610104842A CN 105575935 A CN105575935 A CN 105575935A
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- resin bed
- wiring layer
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- layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a CMOS driver wafer level package and a manufacturing method thereof, and relates to the technical field of apparatuses or systems manufactured or processed in a substrate or on the substrate. The package comprises a driver wafer, a driver wafer pad is formed on parts of the area of the upper surface of the wafer, a passivation layer is formed on the upper surface of the wafer outside the pad area, and a first resin layer is formed on the upper surface of the passivation layer; a re-wiring layer is formed on parts of the upper surface of the first resin layer; a second resin layer is formed on the upper surface of the re-wiring layer and the upper surface of the first resin layer uncovered with the re-wiring layer; a direct under bump metal layer is formed on parts of the upper surface of the second resin layer; and metal bumps are formed on the surface of the direct under bump metal layer. The method disclosed in the invention is compatible with traditional semiconductor technologies, is suitable for batch production, effectively reduces the dimensions of driver chip packages, reduces the parasitic effect and improves the performances of the driver chip.
Description
Technical field
The present invention relates to device or the systems technology field of manufacture or process in substrate or on it, particularly relate to a kind of cmos driver wafer-level packaging and preparation method thereof.
Background technology
Semiconductor packages is the important branch of technical field of integrated circuits, is encapsulated as the protection that integrated circuit (IC) chip provides carrier supported, application interface and chip.Traditional chip package mainly first seals survey through cutting again, packing forms comprises plastic packaging and the encapsulation of cermet shell, chip by forming electrical connection after surface mount between Wire Bonding Technology and shell, and this kind of packing forms has the shortcomings such as volume is large, assembly technology is complicated.Information in driver is represented by binary code " 0 " and " 1 " low and high level, so improve constantly along with the operating frequency of circuit, have to consider whether " 0 " and " 1 " code stream is transferred to receiving terminal like clockwork, for the encapsulation of driver, its ghost effect frequency response characteristic often limits the reference clock frequency of circuit, the edge of signal, owing to receiving the impact of parasitic capacitance thus slowing down, affects the integrality of signal.Operating frequency is higher, and the impact of encapsulation parasitic parameter on circuit is more remarkable.Due to the restriction of technique, the pin of traditional driver encapsulation technology all can introduce larger stray inductance and parasitic capacitance, affects the performance of driver chip.
Wafer-level packaging (WLCSP) technology is in recent years in the technology that microelectronics Packaging field receives much attention, and its main feature first on full wafer wafer, carries out packaging and testing, then just cuts into unit one by one.Therefore wafer-level packaging mode reduces chip package size effectively, meets the compact property requirements of its application product; In performance, wafer-level packaging decreases transmission path, therefore reduces electric current consume and circuit parasitic parameter, improves speed and the stability of transfer of data.On the other hand, wafer-level packaging decreases plastics or the ceramic package of conventional seals, therefore chip heat operationally can dissipate effectively, and this feature contributes to the heat dissipation problem of machine system.In cost, although the processing cost of each step operation of wafer chip size package is relatively high, share cost on each wafer chip level chip then lower, be applicable to producing in enormous quantities.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of cmos driver wafer-level packaging and preparation method thereof, described method is mutually compatible with traditional semiconductor technology, be applicable to mass production, effectively reduce driver chip package dimension, reduce ghost effect, improve the performance of driver chip.
For solving the problems of the technologies described above, the technical solution used in the present invention is: a kind of cmos driver wafer-level packaging, it is characterized in that: comprise driver wafer, the upper surface part subregion of described wafer is formed with driver wafer pad, the upper surface of the wafer beyond described welding disking area is formed with passivation layer, the upper surface of described passivation layer is formed with the first resin bed, and the internal edge of the first resin bed extends to the upper surface of described pad, the part of the upper surface of described pad is covered by described first resin bed, and remainder exposes; The upper surface of described first resin bed of part is formed with wiring layer again, and described in part, wiring layer directly contacts with the exposed part of described pad upper surface again; The upper surface of the upper surface of described wiring layer again and the first resin bed of not covering again wiring layer is formed with the second resin bed; Described second resin bed is provided with via hole, and described via hole to make described in part wiring layer again expose; The upper surface of described second resin bed of part is formed with direct lower metal layer, and the described direct lower metal layer of part directly contacts with the exposed part of described wiring layer again; The upper surface of the direct lower metal layer on the upside of described via hole is formed with metal salient point.
Further technical scheme is: described first resin bed and the second resin bed adopt polyimide material.
Further technical scheme is: it is 200um that described metal salient point comprises diameter, and the copper post of high 20um and diameter are 200um, the tin post of high 30um.
The invention also discloses a kind of manufacture method of cmos driver wafer-level packaging, it is characterized in that comprising the steps:
At upper surface deposit passivation layer and first resin bed successively of driver wafer, and passivation layer and the first resin bed are etched, etch driver wafer welding disking area, then form driver wafer pad at above-mentioned zone;
The part of above-mentioned device upper surface sputters or deposits wiring layer again, described in making, wiring layer part contacts with described driver wafer pad again;
Wiring layer again deposits the second resin bed, etches the second resin bed, to make described in part wiring layer again expose, then the wiring layer again of exposed part is etched, form again the tie point on wiring layer, sputtering or deposition region array;
Make direct lower metal layer at the upper surface of part second resin bed, make described direct lower metal layer partially pass through described second resin bed and directly contact with wiring layer again;
Metal salient point is made at the upper surface of described direct lower metal layer.
Further technical scheme is: before described deposit passivation layer and the first resin bed, also comprise the step of cleaning described wafer.
Further technical scheme is: wiring layer carries out placement-and-routing in the mode connected up again again, ensures each pin reasonable distribution, ensures good electrical connectivity.
Further technical scheme is: redistribute actuator unit pin in wiring layer again, makes pin evenly and becomes array area array.
Further technical scheme is: described first resin bed and the second resin bed adopt polyimide material.
Adopt the beneficial effect that produces of technique scheme to be: described in be encapsulated on the basis of the stable electrical connection ensureing chip and wiring pads, in the mode redefining wiring, pin is reasonably redistributed; Use two layers of polyimide layer, the first polyimides is deposited upon on nude film, and keeps pad to be in the state of windowing; Peripheral-array is converted to area array by sputtering or electroplating by wiring layer again; Deposit the second polyimide layer subsequently, make direct lower metal layer; Finally above direct lower metal layer, make metal salient point.Described encapsulation ensure that stable between wafer and wiring layer and is electrically connected reliably, reduces the stray inductance due to encapsulation introducing and parasitic capacitance effect, improves the performance of chip, be more suitable for being applied in circuit system with the form of flip chip bonding.
Accompanying drawing explanation
Fig. 1 is that method described in the embodiment of the present invention is through step 2) after structural representation;
Fig. 2 is the structural representation of method described in the embodiment of the present invention after step 3);
Fig. 3 is the structural representation of method described in the embodiment of the present invention after step 4);
Fig. 4 is the structural representation of method described in the embodiment of the present invention after step 5);
Fig. 5 is the structural representation of method described in the embodiment of the present invention after step 6);
Fig. 6 is the plan structure schematic diagram of wiring layer again in the present invention;
Wherein: 1, driver wafer 2, driver wafer pad 3, passivation layer 4, first resin bed 5, again wiring layer 6, second resin bed 7, directly lower metal layer 8, metal salient point.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only a part of embodiment of the present invention, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public specific embodiment.
Embodiment one
As shown in Figure 5, the invention discloses a kind of cmos driver wafer-level packaging, comprise driver wafer 1, the upper surface part subregion of described wafer is formed with driver wafer pad 2, the upper surface of the wafer beyond described welding disking area is formed with passivation layer 3, the upper surface of described passivation layer 3 is formed with the first resin bed 4, and the internal edge of the first resin bed 4 extends to the upper surface of described pad, the part of the upper surface of described pad is covered by described first resin bed 4, remainder exposes, preferably, described first resin bed 4 adopts polyimide material to make.
The upper surface of described first resin bed 4 of part is formed with wiring layer 5 again, and described in part, wiring layer 5 directly contacts with the exposed part of described pad upper surface again; The upper surface of the upper surface of described wiring layer again 5 and the first resin bed 4 of not covering again wiring layer 5 is formed with the second resin bed 6; Described second resin bed 6 is provided with via hole, and described via hole to make described in part wiring layer 5 again expose; The upper surface of described second resin bed 6 of part is formed with direct lower metal layer 7, and the described direct lower metal layer 7 of part directly contacts with the exposed part of described wiring layer again 5; The upper surface of the direct lower metal layer 7 on the upside of described via hole is formed with metal salient point 8, and preferably, it is 200um that described metal salient point comprises diameter, and the copper post of high 20um and diameter are 200um, the tin post of high 30um.
Embodiment two
The invention also discloses a kind of manufacture method of cmos driver wafer-level packaging, comprise the steps:
1) get a driver wafer, wafer surface is cleaned.
2) at upper surface deposit passivation layer 3 and first resin bed 4 successively of driver wafer 1, and passivation layer 3 and the first resin bed 4 are etched, etch driver wafer welding disking area, then driver wafer pad 2 is formed at above-mentioned zone, preferably, described first resin bed adopts polyimide material to make, as shown in Figure 1;
3) sputter in the part of above-mentioned device upper surface or deposit wiring layer 5 again, described in making, wiring layer 5 part contacts with described driver wafer pad 2 again, as shown in Figure 2;
4) on wiring layer 5 again, deposit the second resin bed 6, etch the second resin bed 6, to make described in part wiring layer 5 again expose, then the wiring layer again 5 of exposed part is etched, form again the tie point on wiring layer, sputtering or deposition region array, as shown in Figure 3;
Wiring layer 5 carries out placement-and-routing in the mode connected up again again, ensures each pin reasonable distribution, ensures good electrical connectivity.In wiring layer 5 again, actuator unit pin is redistributed, make pin evenly and become array area array.
5) make direct lower metal layer 7 at the upper surface of part second resin bed 6, make described direct lower metal layer 7 partially pass through described second resin bed 6 and directly contact with wiring layer 5 again, as shown in Figure 4;
6) metal salient point 8 is made at the upper surface of described direct lower metal layer 7, as shown in Figure 5.
On the described basis being encapsulated in the stable electrical connection ensureing chip and wiring pads, in the mode redefining wiring, pin is reasonably redistributed; Use two layers of polyimide layer, the first polyimides is deposited upon on nude film, and keeps pad to be in the state of windowing; Peripheral-array is converted to area array by sputtering or electroplating by wiring layer again; Deposit the second polyimide layer subsequently, make direct lower metal layer; Finally above direct lower metal layer, make metal salient point.Described encapsulation ensure that stable between wafer and wiring layer and is electrically connected reliably, reduces the stray inductance due to encapsulation introducing and parasitic capacitance effect, improves the performance of chip, be more suitable for being applied in circuit system with the form of flip chip bonding.
Claims (8)
1. a cmos driver wafer-level packaging, it is characterized in that: comprise driver wafer (1), the upper surface part subregion of described wafer is formed with driver wafer pad (2), the upper surface of the wafer beyond described welding disking area is formed with passivation layer (3), the upper surface of described passivation layer (3) is formed with the first resin bed (4), and the internal edge of the first resin bed (4) extends to the upper surface of described pad, the part of the upper surface of described pad is covered by described first resin bed (4), and remainder exposes; The upper surface of described first resin bed (4) of part is formed with wiring layer (5) again, and described in part, wiring layer (5) directly contacts with the exposed part of described pad upper surface again; The upper surface of the upper surface of described wiring layer again (5) and the first resin bed (4) of not covering again wiring layer (5) is formed with the second resin bed (6); Described second resin bed (6) is provided with via hole, and described via hole to make described in part wiring layer (5) again expose; The upper surface of described second resin bed (6) of part is formed with direct lower metal layer (7), and the described direct lower metal layer of part (7) directly contacts with the exposed part of described wiring layer again (5); The upper surface of the direct lower metal layer (7) on the upside of described via hole is formed with metal salient point (8).
2. cmos driver wafer-level packaging as claimed in claim 1, is characterized in that: described first resin bed (4) and the second resin bed (6) adopt polyimide material.
3. cmos driver wafer-level packaging as claimed in claim 1, it is characterized in that: it is 200um that described metal salient point comprises diameter, the copper post of high 20um and diameter are 200um, the tin post of high 30um.
4. a manufacture method for cmos driver wafer-level packaging, is characterized in that comprising the steps:
At upper surface deposit passivation layer (3) and first resin bed (4) successively of driver wafer (1), and passivation layer (3) and the first resin bed (4) are etched, etch driver wafer welding disking area, then form driver wafer pad (2) at above-mentioned zone;
The part of above-mentioned device upper surface sputters or deposits wiring layer (5) again, described in making, wiring layer (5) part contacts with described driver wafer pad (2) again;
At upper deposition second resin bed (6) of wiring layer (5) again, etch the second resin bed (6), to make described in part wiring layer (5) again expose, then the wiring layer again (5) of exposed part is etched, form again the tie point on wiring layer, sputtering or deposition region array;
Make direct lower metal layer (7) at the upper surface of part second resin bed (6), make described direct lower metal layer (7) partially pass through described second resin bed (6) and directly contact with wiring layer (5) again;
Metal salient point (8) is made at the upper surface of described direct lower metal layer (7).
5. the manufacture method of cmos driver wafer-level packaging as claimed in claim 4, is characterized in that: before described deposit passivation layer (3) and the first resin bed (4), also comprise the step of cleaning described wafer.
6. the manufacture method of cmos driver wafer-level packaging as claimed in claim 4, is characterized in that: wiring layer (5) carries out placement-and-routing in the mode connected up again again.
7. the manufacture method of cmos driver wafer-level packaging as claimed in claim 4, is characterized in that: redistribute actuator unit pin in wiring layer (5) again, make pin evenly and become array area array.
8. the manufacture method of cmos driver wafer-level packaging as claimed in claim 4, is characterized in that: described first resin bed (4) and the second resin bed (6) adopt polyimide material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201610104842.0A CN105575935A (en) | 2016-02-25 | 2016-02-25 | CMOS driver wafer level package and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610104842.0A CN105575935A (en) | 2016-02-25 | 2016-02-25 | CMOS driver wafer level package and manufacturing method thereof |
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| CN201610104842.0A Pending CN105575935A (en) | 2016-02-25 | 2016-02-25 | CMOS driver wafer level package and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111668166A (en) * | 2019-03-08 | 2020-09-15 | Tdk株式会社 | Assembly of laminated elements and method for manufacturing same |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1922728A (en) * | 2004-12-03 | 2007-02-28 | 罗姆股份有限公司 | Semiconductor device |
| JP2007258438A (en) * | 2006-03-23 | 2007-10-04 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
| EP1036414B1 (en) * | 1997-10-20 | 2009-03-04 | FlipChip International L.L.C. | A method of forming a chip scale package using large ductile solder balls |
| CN101510536A (en) * | 2008-02-14 | 2009-08-19 | 株式会社瑞萨科技 | Semiconductor device and a method of manufacturing the sae |
| US20090294965A1 (en) * | 2003-12-26 | 2009-12-03 | Renesas Technology Corp. | Method of Manufacturing A Semiconductor Device |
| US20110204515A1 (en) * | 2010-02-22 | 2011-08-25 | Texas Instruments Incorporated | Ic die including rdl capture pads with notch having bonding connectors or its ubm pad over the notch |
| CN102810506A (en) * | 2011-06-03 | 2012-12-05 | 台湾积体电路制造股份有限公司 | Electrical connection for chip scale packaging |
| CN103035579A (en) * | 2011-10-05 | 2013-04-10 | 台湾积体电路制造股份有限公司 | Wafer level chip scale package and method of manufacturing the same |
| CN103222050A (en) * | 2010-11-01 | 2013-07-24 | 德克萨斯仪器股份有限公司 | Crack arrest vias for ic devices |
| CN103915374A (en) * | 2013-01-09 | 2014-07-09 | 台湾积体电路制造股份有限公司 | Post-passivation interconnect structure and methods for forming the same |
| CN104051429A (en) * | 2013-03-11 | 2014-09-17 | 台湾积体电路制造股份有限公司 | Methods and apparatus for wafer level packaging |
| CN104272457A (en) * | 2012-05-10 | 2015-01-07 | 德克萨斯仪器股份有限公司 | Wafer scale packaging die with offset redistribution layer capture pad |
| CN205376507U (en) * | 2016-02-25 | 2016-07-06 | 中国电子科技集团公司第十三研究所 | CMOS driver wafer -level package |
-
2016
- 2016-02-25 CN CN201610104842.0A patent/CN105575935A/en active Pending
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1036414B1 (en) * | 1997-10-20 | 2009-03-04 | FlipChip International L.L.C. | A method of forming a chip scale package using large ductile solder balls |
| US20090294965A1 (en) * | 2003-12-26 | 2009-12-03 | Renesas Technology Corp. | Method of Manufacturing A Semiconductor Device |
| CN1922728A (en) * | 2004-12-03 | 2007-02-28 | 罗姆股份有限公司 | Semiconductor device |
| JP2007258438A (en) * | 2006-03-23 | 2007-10-04 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
| CN101510536A (en) * | 2008-02-14 | 2009-08-19 | 株式会社瑞萨科技 | Semiconductor device and a method of manufacturing the sae |
| US20110204515A1 (en) * | 2010-02-22 | 2011-08-25 | Texas Instruments Incorporated | Ic die including rdl capture pads with notch having bonding connectors or its ubm pad over the notch |
| CN103222050A (en) * | 2010-11-01 | 2013-07-24 | 德克萨斯仪器股份有限公司 | Crack arrest vias for ic devices |
| CN102810506A (en) * | 2011-06-03 | 2012-12-05 | 台湾积体电路制造股份有限公司 | Electrical connection for chip scale packaging |
| CN103035579A (en) * | 2011-10-05 | 2013-04-10 | 台湾积体电路制造股份有限公司 | Wafer level chip scale package and method of manufacturing the same |
| CN104272457A (en) * | 2012-05-10 | 2015-01-07 | 德克萨斯仪器股份有限公司 | Wafer scale packaging die with offset redistribution layer capture pad |
| CN103915374A (en) * | 2013-01-09 | 2014-07-09 | 台湾积体电路制造股份有限公司 | Post-passivation interconnect structure and methods for forming the same |
| CN104051429A (en) * | 2013-03-11 | 2014-09-17 | 台湾积体电路制造股份有限公司 | Methods and apparatus for wafer level packaging |
| CN205376507U (en) * | 2016-02-25 | 2016-07-06 | 中国电子科技集团公司第十三研究所 | CMOS driver wafer -level package |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111668166A (en) * | 2019-03-08 | 2020-09-15 | Tdk株式会社 | Assembly of laminated elements and method for manufacturing same |
| CN111668166B (en) * | 2019-03-08 | 2023-08-08 | Tdk株式会社 | Assembly of laminated elements and method for manufacturing same |
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Application publication date: 20160511 |
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| RJ01 | Rejection of invention patent application after publication |