CN105575901B - The production method and semiconductor devices of semiconductor devices - Google Patents
The production method and semiconductor devices of semiconductor devices Download PDFInfo
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- CN105575901B CN105575901B CN201410542467.9A CN201410542467A CN105575901B CN 105575901 B CN105575901 B CN 105575901B CN 201410542467 A CN201410542467 A CN 201410542467A CN 105575901 B CN105575901 B CN 105575901B
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Abstract
This application discloses a kind of production method of semiconductor devices and semiconductor devices.Wherein, the production method of semiconductor devices includes: offer semiconductor substrate, and semiconductor substrate has first area and second area, and polysilicon gate and the dielectric layer around polysilicon gate setting are respectively formed on first area and second area；Form the first metal hard mask of covering polysilicon gate and dielectric layer；It is made annealing treatment, so that the first metal hard mask and polysilicon gate reaction generate metal silicide；Polysilicon gate and metal silicide in removal first area forms metal gates to form groove in a groove.In above-mentioned production method; since bond energy is greater than bond energy in polysilicon gate in metal silicide; so that the etch rate of metal silicide is less than the etch rate of polysilicon gate; therefore metal silicide as the protective layer of polysilicon gate, can reduce manufacturing process damage caused by polysilicon gate of metal gates.
Description
Technical field
This application involves the technical fields of semiconductor integrated circuit, in particular to a kind of production of semiconductor devices
Method and semiconductor devices.
Background technique
As the characteristic size of transistor constantly reduces, through frequently with metal gates in the manufacturing process of semiconductor devices
Replace polysilicon gate.This is because smaller with effective gate oxide thickness (EOT) using the formed transistor of metal gates,
Grid leakage current is lower and low power consumption and other advantages.Therefore, in the manufacturing process of semiconductor devices, it usually needs in performance requirement
Metal gates are formed on high device region, and form polysilicon gate on other device regions.
Fig. 1 to Fig. 3 shows the manufacturing process of existing semiconductor devices, comprising the following steps: firstly, providing includes first
The semiconductor substrate in region 11 ' and second area 13 ', the first area 11 ' include the first device region 111 ' and the second device again
Area 113 ', wherein the first device region 111 ' is above formed with the first polysilicon gate 21 ', the second device region 113 ' is above formed with second
Polysilicon gate 23 ', second area 13 ' are above formed with third polysilicon gate 25 ', and each first polysilicon gate 21 ', second
Polysilicon gate 23 ' and third polysilicon gate 25 ' are surrounded by dielectric layer 30 ', and structure is as shown in Figure 1；Then, etching removal
First polysilicon gate 21 ', to form the first groove, and the shape in the first groove on the position of the first polysilicon gate 21 '
At the first metal gates 41 ', and then form base structure as shown in Figure 2；Finally, etching the second polysilicon gate 23 ' of removal,
To form the second groove on the position of the second polysilicon gate 23 ', and the second metal gates 43 ' are formed in the second groove,
And then form base structure as shown in Figure 3.
Wherein, the step of forming the first metal gates 41 ' in above-mentioned first groove includes: to form the first groove of covering
First metal gates, 41 ' preparation layers, and planarization removal are located at the 41 ' preparation layers of the first metal gates on dielectric layer 30 ', and
41 ' the preparation layers of the first metal gates in the first groove will be located at as the first metal gates 41 '.The shape in above-mentioned second groove
It include: the 43 ' preparation layers of the second metal gates to form the second groove of covering at the step of the second metal gates 43 ', planarization is gone
Except the 43 ' preparation layers of the second metal gates being located on dielectric layer 30 ', and the second metal gates 43 ' in the second groove will be located at
Preparation layers are as the second metal gates 43 '.Above-mentioned flatening process twice can cause to damage to third polysilicon gate 25 ', example
The defects of such as generating pit.These defects to be easy to produce leakage current etc. in semiconductor devices, thereby reduce semiconductor device
The performance of part.In view of the above-mentioned problems, there is presently no effective solution methods.
Summary of the invention
The application is intended to provide the production method and semiconductor devices of a kind of semiconductor devices, to reduce the system of metal gates
Make process damage caused by polysilicon gate, and then improves the performance of semiconductor devices.
To achieve the goals above, this application provides a kind of production method of semiconductor devices, which includes:
Semiconductor substrate is provided, semiconductor substrate has first area and second area, and shape is distinguished on first area and second area
At the dielectric layer for having polysilicon gate and being arranged around polysilicon gate；Form the first gold medal of covering polysilicon gate and dielectric layer
Belong to hard exposure mask；It is made annealing treatment, so that the first metal hard mask and polysilicon gate reaction generate metal silicide；Removal the
Polysilicon gate and metal silicide in one region forms metal gates to form groove in a groove.
Further, in above-mentioned production method, the step of annealing in, treatment temperature is 250~450 DEG C, when processing
Between be 1~30s.
Further, in above-mentioned production method, the step of forming metal gates in a groove includes: in a groove with first
Metal gates preparation layers are formed on metal hard mask；Planarization process is carried out to metal gates preparation layers and the first metal hard mask
To the surface for exposing dielectric layer, and using residual metallic grid preparation layers as metal gates.
Remove polysilicon gate and metal silicide in first area；The position of polysilicon gate and in the first region
Metal gates preparation layers are formed on one metal hard mask；Planarization process is carried out, polysilicon gate in first area is located at removal
Part metals grid preparation layers on the position of pole, and the first metal hard mask and metal gates preparation on dielectric layer
Layer, and using residual metallic grid preparation layers as metal gates.
Further, in above-mentioned production method, the planarization process the step of in removal be located at polysilicon in second area
Metal silicide on the position of grid.
Further, in above-mentioned production method, first area includes the first device region and the second device region, polysilicon gate
Including be located at the first device region in the first polysilicon gate, positioned at the second device region the second polysilicon gate and be located at second
The third polysilicon gate in region；The step of forming metal gates includes: to form first on the position of the first polysilicon gate
Metal gates；The second metal gates, the first metal gates and the second metal gates are formed on the position of the second polysilicon gate
Form metal gates.
Further, in above-mentioned production method, formed the first metal gates the step of include: removal the first polysilicon gate
With the metal silicide on the first polysilicon gate to form the first groove；In the first groove and the first metallic hard is covered
The first metal gates preparation layers are formed on film；First time planarization is carried out to first grid preparation layers and the first metal hard mask layer
It handles to the surface for exposing dielectric layer, and using remaining first metal gates preparation layers as the first metal gates；Form second
The step of metal gates includes: to form the first metal gates of covering, the second polysilicon gate, third polysilicon gate and dielectric layer
The second metal hard mask；The second polysilicon gate and the metal silicide on the first polysilicon gate are removed to form
Two grooves；The second metal gates are formed in the second groove and on the second metal hard mask for layer；It is pre- to the second metal gates
Standby layer and the second metal hard mask carry out second of planarization process to the surface for exposing dielectric layer, and by remaining second metal
Grid preparation layers are as the second metal gates.
Further, in above-mentioned production method, the first time planarization process the step of in removal be located at the second polysilicon
Part metals silicide on grid and third polysilicon gate；Removal is located at third in second of planarization process the step of
Metal silicide on polysilicon gate.
Further, in above-mentioned production method, the first device region is the area PMOS, and the second device region is NMOS area；Or the
One device region is NMOS area, and the second device region is the area PMOS.
Further, in above-mentioned production method, the first metal hard mask is TiN.
Further, in above-mentioned production method, the material of metal gates is Al or Cu.
Present invention also provides a kind of semiconductor devices, the semiconductor devices by the application it is above-mentioned production method production and
At.
Using the technical solution of the application, the first of covering polysilicon gate is formed before the step of forming metal gates
Metal hard mask, and made annealing treatment so that the first metal hard mask and polysilicon gate reaction generate metal silicide.By
Bond energy is greater than bond energy in polysilicon gate in metal silicide, so that the etch rate of metal silicide is less than polysilicon gate
Etch rate, therefore metal silicide can reduce the manufacturing process of metal gates as the protective layer of polysilicon gate
It is damaged caused by polysilicon gate, and then improves the performance of semiconductor devices.
Detailed description of the invention
The accompanying drawings constituting a part of this application is used to provide further understanding of the present application, and the application's shows
Meaning property embodiment and its explanation are not constituted an undue limitation on the present application for explaining the application.In the accompanying drawings:
Fig. 1 is shown in the production method of existing semiconductor devices, and provided includes first area and second area
Semiconductor substrate the schematic diagram of the section structure；
Fig. 2 shows etchings to remove the first polysilicon gate shown in FIG. 1 to form the first groove, and in the first groove
The schematic diagram of the section structure of matrix after forming the first metal gates；
Fig. 3 shows etching and removes the second polysilicon gate shown in Fig. 2 to form the second groove, and in the second groove
The schematic diagram of the section structure of matrix after forming the second metal gates；
Fig. 4 shows the flow diagram of the production method of semiconductor devices provided by the application embodiment；
Fig. 5 is shown in the production method of the semiconductor devices provided by a kind of preferred embodiment of the application, is provided
Semiconductor substrate, semiconductor substrate has first area and second area, and is respectively formed on first area and second area
The schematic diagram of the section structure of polysilicon gate and the matrix after the dielectric layer of polysilicon gate setting；
Fig. 6 shows the first metal hard mask to be formed and cover polysilicon gate and dielectric layer shown in fig. 5, and is moved back
Fire processing, so that the first metal hard mask and polysilicon gate reaction generate the cross-section structure signal of the matrix after metal silicide
Figure；
Fig. 7, which is shown, removes polysilicon gate in first area shown in fig. 6 and metal silicide to form groove, and
The schematic diagram of the section structure of the matrix after metal gates is formed in a groove；
Fig. 7-1 shows removal the first polysilicon gate shown in fig. 6 and the metallic silicon on the first polysilicon gate
Compound is to form the schematic diagram of the section structure of the matrix after the first groove；
Fig. 7-2 shows in first groove shown in Fig. 7-1 and forms the first metal gate on the first metal hard mask
The schematic diagram of the section structure of matrix after the preparation layers of pole；
Fig. 7-3 shows the first metal gates preparation layers and the first metal hard mask and carries out first time planarization process to sudden and violent
Expose the surface of dielectric layer, and using remaining first metal gates preparation layers as the cross-section structure of the matrix after the first metal gates
Schematic diagram；
Fig. 7-4 shows to form the first metal gates, the second polysilicon gate shown in coverage diagram 7-3, third polysilicon
Second metal hard mask of grid and dielectric layer, and remove the second polysilicon gate and the metal on the first polysilicon gate
Silicide is to form the schematic diagram of the section structure of the matrix after the second groove；And
Fig. 7-5 shows in second groove shown in Fig. 7-4 and forms the second metal gate on the second metal hard mask
Extremely for the schematic diagram of the section structure of the matrix after layer.
Specific embodiment
It should be noted that in the absence of conflict, the features in the embodiments and the embodiments of the present application can phase
Mutually combination.The application is described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.
It should be noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to the illustrative embodiments of the application.As used herein, unless the context clearly indicates otherwise, otherwise singular
Also it is intended to include plural form, additionally, it should be understood that, when in the present specification using term "comprising" and/or " packet
Include " when, indicate existing characteristics, step, operation, device, component and/or their combination.
For ease of description, spatially relative term can be used herein, as " ... on ", " ... top ",
" ... upper surface ", " above " etc., for describing such as a device shown in the figure or feature and other devices or spy
The spatial relation of sign.It should be understood that spatially relative term is intended to comprising the orientation in addition to device described in figure
Except different direction in use or operation.For example, being described as if the device in attached drawing is squeezed " in other devices
It will be positioned as " under other devices or construction after part or construction top " or the device of " on other devices or construction "
Side " or " under other devices or construction ".Thus, exemplary term " ... top " may include " ... top " and
" in ... lower section " two kinds of orientation.The device can also be positioned with other different modes and (is rotated by 90 ° or in other orientation), and
And respective explanations are made to the opposite description in space used herein above.
As described in background technique, the manufacturing process of metal gates can cause to damage to polysilicon gate, in turn
Reduce the performance of semiconductor devices.Present inventor studies regarding to the issue above, proposes a kind of semiconductor devices
Production method.As shown in figure 4, the production method includes: offer semiconductor substrate, semiconductor substrate has first area and the
Two regions, and polysilicon gate and the medium around polysilicon gate setting are respectively formed on first area and second area
Layer；Form the first metal hard mask of covering polysilicon gate and dielectric layer；It is made annealing treatment, so that the first metal hard mask
It is reacted with polysilicon gate and generates metal silicide；Polysilicon gate and metal silicide in removal first area is recessed to be formed
Slot, and metal gates are formed in a groove.
In above-mentioned production method, the first metallic hard of covering polysilicon gate is formed before the step of forming metal gates
Exposure mask, and made annealing treatment so that the first metal hard mask and polysilicon gate reaction generate metal silicide.Due to metal
Bond energy is greater than bond energy in polysilicon gate in silicide, so that the etch rate of metal silicide is less than the etching of polysilicon gate
Rate, therefore metal silicide can reduce the manufacturing process of metal gates to polycrystalline as the protective layer of polysilicon gate
It is damaged caused by silicon gate, and then improves the performance of semiconductor devices.
The illustrative embodiments according to the application are described in more detail below.However, these illustrative embodiments
It can be implemented by many different forms, and should not be construed to be limited solely to embodiments set forth herein.It should
These embodiments that are to provide understood are in order to enable disclosure herein is thoroughly and complete, and by these exemplary realities
The design for applying mode is fully conveyed to those of ordinary skill in the art, in the accompanying drawings, for the sake of clarity, expands layer and region
Thickness, and make that identical device is presented with like reference characters, thus description of them will be omitted.
Fig. 5 to Fig. 7 is shown in the production method of semiconductor devices provided by a kind of preferred embodiment of the application, warp
Cross the schematic diagram of the section structure of the matrix obtained after each step.Below in conjunction with Fig. 5 to Fig. 7, further illustrate that the application should
The production method of provided semiconductor devices provided by preferred embodiment.
Firstly, providing semiconductor substrate, semiconductor substrate has first area 11 and second area 13, and first area 11
With the dielectric layer 30 for being respectively formed with polysilicon gate 20 on second area 13 and being arranged around polysilicon gate 20, structure is such as
Shown in Fig. 5.First area 11 and second area 13 can be divided according to the function of device, such as core space and peripheral circuit
Area.Dielectric layer 30 can be material common in this field, and dielectric layer 30 can be one or more layers.Form polysilicon gate
20 and the processing step of dielectric layer 30 can be carried out with the parameter prior art.It should be noted that can be with shape in semiconductor substrate
At other devices, such as groove isolation construction, strained silicon layer or gate lateral wall are layer by layer.
In a preferred embodiment, first area 11 includes the first device region 111 and the second device region 113, more
Polysilicon gate 20 includes the first polysilicon gate 21 being located in the first device region 111, positioned at more than the second of the second device region 113
Polysilicon gate 23 and third polysilicon gate 25 positioned at second area 13, structure is as shown in Figure 5.First device region, 111 He
Second device region 113 can be set according to the type of device.Preferably, the first device region 111 is the area PMOS, the second device
Area 113 is NMOS area；Or first device region 111 be NMOS area, the second device region 113 be the area PMOS.
After completing the step of semiconductor substrate is provided, the first metal of covering polysilicon gate 20 and dielectric layer 30 is formed
Hard exposure mask 51, and made annealing treatment, so that the first metal hard mask 51 and the reaction of polysilicon gate 20 generate metal silicide
60, and then form base structure as shown in FIG. 6.Wherein, the first metal hard mask 51 is that can generate metal with polycrystalline pasc reaction
The mask material of silicide 60, in a preferred embodiment, the first metal hard mask 51 are TiN.Form above-mentioned first
The technique of metal hard mask 51 can be chemical vapor deposition or sputtering etc., and above-mentioned technique is state of the art, herein not
It repeats again.
In the step of above-mentioned annealing, the technological parameter of annealing can be according to used first metal hard mask 51
Type is set.Preferably, in the step of annealing, treatment temperature is 250~450 DEG C, and the processing time is 1~30s.It moves back
The concrete mode of fire can be rapid thermal annealing or laser annealing etc..
It completes to form the first metal hard mask 51 for covering polysilicon gate 20 and dielectric layer 30, and is made annealing treatment,
So as to remove first area after the step of the first metal hard mask 51 and the reaction of polysilicon gate 20 generate metal silicide 60
Polysilicon gate 20 and metal silicide 60 in 11 forms metal gates 40 to form groove in a groove, and then is formed
Base structure as shown in Figure 7.The material of metal gates 40 can be grid metal material common in this field, in one kind
In preferred embodiment, the material of metal gates 40 is Al or Cu.
The production of above-mentioned metal gates 40 can be in different ways.In a preferred embodiment, gold is formed
The step of belonging to grid 40 include: in removal first area 11 polysilicon gate 20 and metal silicide 60 to form groove；Recessed
Metal gates preparation layers are formed in slot and on the first metal hard mask 51；To metal gates preparation layers and the first metal hard mask
51 carry out planarization process to the surface for exposing dielectric layer 30, and using residual metallic grid preparation layers as metal gates 40,
And then form base structure as shown in Figure 7.It should be noted that can be completely removed in the planarization process the step of (or
Removal a part) it is located at the metal silicide 60 in second area 13.
In another preferred embodiment, the step of forming metal gates 40 includes: removal shown in fig. 6 more than first
Polysilicon gate 21 and metal silicide 60 on the first polysilicon gate 21 form such as Fig. 7-to form the first groove
Base structure shown in 1；The first metal gates preparation layers 41 ' are formed on the first groove and the first metal hard mask 51, into
And form the base structure as shown in Fig. 7-2；First is carried out to the first metal gates preparation layers 41 ' and the first metal hard mask 51
Secondary planarization process is used as the first metal to the surface for exposing dielectric layer 30, and by remaining first metal gates preparation layers 41 '
Grid 41, and then form the base structure as shown in Fig. 7-3；Form the first metal gates more than 41, second shown in coverage diagram 7-3
Second metal hard mask 53 of polysilicon gate 23, third polysilicon gate 25 and dielectric layer 30, and remove the second polysilicon gate
23 and the metal silicide 60 on the first polysilicon gate 21 to form the second groove, and then formed as shown in Fig. 7-4
Base structure；The second metal gates are formed in the second groove and on the second metal hard mask 53 for layer 43 ', and then are formed such as
Base structure shown in Fig. 7-5；Second metal gates are carried out at second of planarization for layer 43 ' and the second metal hard mask 53
It manages to the surface for exposing dielectric layer, and regard remaining second metal gates preparation layers 43 ' as the second metal gates 43, and then shape
At base structure as shown in Figure 7.It should be noted that removal is located at the second polycrystalline in the first time planarization process the step of
Part metals silicide 60 on silicon gate 23 and third polysilicon gate 25；It can be in second of planarization process the step of
Removal (all or part) is located at the metal silicide 60 on third polysilicon gate 25.
In two kinds of preferred embodiments for forming above-mentioned metal gates 40, polysilicon gate 20 and metal silicide are removed
60 technique can be wet etching etc..Form metal gates preparation layers, the first metal gates preparation layers 41 ' and the second metal gate
The technique of pole preparation layers 43 ' can be chemical vapor deposition or sputtering etc..Above-mentioned planarization process can be chemically mechanical polishing,
Polishing fluid used by chemically-mechanicapolish polishing can be set according to the prior art, such as can be hydrogen peroxide solution or ozone
Solution etc..Above-mentioned technique is state of the art, and details are not described herein.
Meanwhile present invention also provides a kind of semiconductor devices, the semiconductor devices semiconductor devices above-mentioned by the application
The production method of part is made.It is damaged caused by polysilicon gate in the semiconductor devices as the manufacturing process of metal gates
It is reduced, and then improves the performance of semiconductor devices.
It can be seen from the above description that the application the above embodiments realize following technical effect: forming gold
The first metal hard mask of covering polysilicon gate is formed before the step of belonging to grid, and is made annealing treatment so that the first metal
Hard exposure mask and polysilicon gate reaction generate metal silicide.Since bond energy is greater than key in polysilicon gate in metal silicide
Can so that the etch rate of metal silicide be less than polysilicon gate etch rate, therefore metal silicide can be used as it is more
The protective layer of polysilicon gate reduces manufacturing process damage caused by polysilicon gate of metal gates, and then improves and partly lead
The performance of body device.
The foregoing is merely preferred embodiment of the present application, are not intended to limit this application, for the skill of this field
For art personnel, various changes and changes are possible in this application.Within the spirit and principles of this application, made any to repair
Change, equivalent replacement, improvement etc., should be included within the scope of protection of this application.
Claims (9)
1. a kind of production method of semiconductor devices, which is characterized in that the production method includes:
Semiconductor substrate is provided, the semiconductor substrate has first area and second area, and the first area and second
Polysilicon gate and the dielectric layer around polysilicon gate setting are respectively formed on region；
Form the first metal hard mask of the covering polysilicon gate and the dielectric layer；
It is made annealing treatment, so that first metal hard mask and polysilicon gate reaction generate metal silicide；
The polysilicon gate and metal silicide in the first area are removed to form groove, and the shape in the groove
At metal gates；In the step of annealing, treatment temperature is 250~450 DEG C, and the processing time is 1~30s, the gold
The material for belonging to grid is Al or Cu；The concrete mode of the annealing steps is rapid thermal annealing or laser annealing.
2. manufacturing method according to claim 1, which is characterized in that form the step of the metal gates in the groove
Suddenly include:
Metal gates preparation layers are formed in the groove and on first metal hard mask；
Planarization process is carried out to exposing the dielectric layer to the metal gates preparation layers and first metal hard mask
Surface, and using the remaining metal gates preparation layers as the metal gates.
3. production method according to claim 2, which is characterized in that remove and be located in the planarization process the step of
The metal silicide on the position of polysilicon gate described in the second area.
4. manufacturing method according to claim 1, which is characterized in that
The first area includes the first device region and the second device region, and the polysilicon gate includes being located at first device
The first polysilicon gate in area, the second polysilicon gate positioned at second device region and positioned at the second area
Three polysilicon gates；
The step of forming the metal gates include:
The first metal gates are formed on the position of first polysilicon gate；
The second metal gates, first metal gates and second gold medal are formed on the position of second polysilicon gate
Belong to grid and forms the metal gates.
5. production method according to claim 4, which is characterized in that
The step of forming first metal gates include:
First polysilicon gate and the metal silicide on first polysilicon gate are removed to form
One groove；
The first metal gates preparation layers are formed in first groove and on first metal hard mask；
First time planarization process is carried out to exposing to the first metal gates preparation layers and first metal hard mask
The surface of the dielectric layer, and using the remaining first metal gates preparation layers as first metal gates；
The step of forming second metal gates include:
It is formed and covers first metal gates, second polysilicon gate, the third polysilicon gate and the medium
Second metal hard mask of layer；
Second polysilicon gate and the metal silicide on first polysilicon gate are removed to form
Two grooves；
The second metal gates preparation layers are formed in second groove and on second metal hard mask；
Second of planarization process is carried out to exposing to the second metal gates preparation layers and second metal hard mask
The surface of the dielectric layer, and using the remaining second metal gates preparation layers as second metal gates.
6. production method according to claim 5, which is characterized in that
Removal is located at second polysilicon gate and third polysilicon gate in the first time planarization process the step of
On the part metal silicide；
Removal is located at the metal silication on the third polysilicon gate in second of planarization process the step of
Object.
7. production method according to claim 4, which is characterized in that
First device region is the area PMOS, and second device region is NMOS area；Or
First device region is NMOS area, and second device region is the area PMOS.
8. production method according to any one of claim 1 to 7, which is characterized in that first metal hard mask is
TiN。
9. a kind of semiconductor devices, which is characterized in that the semiconductor devices is by system described in any item of the claim 1 to 8
It is made as method.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103165429A (en) * | 2011-12-15 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Formation method of metal gates |
| CN103779279A (en) * | 2012-10-26 | 2014-05-07 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN103794483A (en) * | 2012-10-30 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device having metal gate |
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| US7544621B2 (en) * | 2005-11-01 | 2009-06-09 | United Microelectronics Corp. | Method of removing a metal silicide layer on a gate electrode in a semiconductor manufacturing process and etching method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103165429A (en) * | 2011-12-15 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Formation method of metal gates |
| CN103779279A (en) * | 2012-10-26 | 2014-05-07 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN103794483A (en) * | 2012-10-30 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device having metal gate |
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