CN105575834A - Wafer bonding method - Google Patents
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- CN105575834A CN105575834A CN201410528965.8A CN201410528965A CN105575834A CN 105575834 A CN105575834 A CN 105575834A CN 201410528965 A CN201410528965 A CN 201410528965A CN 105575834 A CN105575834 A CN 105575834A
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Abstract
The invention provides a wafer bonding method. The wafer bonding method is characterized in that S1, a first to-be-bonded wafer and a second to-be-bonded wafer can be provided, and the surface of the first to-be-bonded wafer is provided with a plurality of first Cu pads, and the surface of the second to-be-bonded wafer is provided with a plurality of second Cu pads, the positions of which are corresponding to that of the first Cu pads; S2, an adhesive layer is disposed on the surfaces of the first Cu pads and the surfaces of the second Cu pads, and then the back surface of the first to-be-bonded wafer or the second to-be-bonded wafer can be thinned; S3, the first Cu pads are aligned with the second Cu pads, and the first to-be-bonded wafer are bonded with the second to-be-bonded wafer. The wafer bonding method is advantageous in that before the wafer bonding, the adhesive layer can be formed on the surface of the Cu pads, and the back surface of the wafer can be thinned, and therefore the bonding force on the bonding area can be effectively enhanced, the damages on the bonding points during the wafer thinning process can be prevented, and the probability of the stripping of the bonded wafers can be reduced.
Description
Technical field
The invention belongs to IC manufacturing field, relate to a kind of wafer bonding method.
Background technology
Along with integrated level improves constantly, the device cell quantity on every sheet sharply increases, and chip area increases, and between unit, the growth of line not only affects circuit working speed but also take a lot of area, has a strong impact on integrated circuit and improves integrated level and operating rate further.So produce three dimensional integrated circuits to arise at the historic moment.Three dimensional integrated circuits is the integrated circuit with multilayer device structure, also known as stereo integrated circuit.Existing extensive stock integrated circuit is all planar structure, and namely the various unit components of integrated circuit distribute in one plane one by one, claims two-dimensional integrated circuit.And three dimensional integrated circuits (3D-IC) forms 3 D stereo sandwich construction.Three-dimensional integrated advantage is: 1. improve packaging density: multilayer device overlay structure can significantly improve chip integration; 2. circuit working speed is improved: overlay structure makes unit line shorten, and makes Parallel signal processing become possibility, thus the high speed operation of realizing circuit; 3. can realize Multifunction device and Circuits System: as the function elements such as photoelectric device and silicon integrated circuit are integrated, form New function system.Current countries in the world are all being devoted to study three dimensional integrated circuits, and have made the sandwich construction integrated circuit of some practicalities.
In semiconductor fabrication process, wafer bonding and reduction process are applied to three dimensional integrated circuits field more and more, and wherein bonding performance is the focus of people.Cause the reason of bonding failure to have a lot, modal a kind of inefficacy mechanism is that wafer is peeled off.After two panels wafer bonding completes, carry out wafer back part reduction process be easy to cause wafer to be peeled off.
At present, in Cu-Cu bonding technology, usually before bonding, carry out Cu depositing operation and Cu CMP (Chemical Mechanical Polishing) process, the depression problem caused due to Cu chemico-mechanical polishing and bonding technology self, be easy to cause bonding failure, be peeling problem.
Therefore, a kind of wafer bonding method is provided to be necessary to solve the problem.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of wafer bonding method, insecure for solving Cu-Cu bonding in prior art, the problem that after bonding, wafer is easily peeled off.
For achieving the above object and other relevant objects, the invention provides a kind of wafer bonding method, at least comprise the following steps:
S1: the first wafer to be bonded and the second wafer to be bonded are provided, described first crystal column surface to be bonded is formed with some Cu pads, and described second crystal column surface to be bonded is formed with the 2nd corresponding Cu pad of a some and described Cu pad locations;
S2: form adhesion layer in a described Cu bond pad surface or the 2nd Cu bond pad surface, and by described first wafer to be bonded or the second thinning back side of silicon wafer to be bonded;
S3: by a described Cu pad and the 2nd Cu pad alignment, by described first wafer to be bonded and the second wafer bonding to be bonded.
Alternatively, in described step S2, first by described first wafer to be bonded or the second thinning back side of silicon wafer to be bonded, and then form adhesion layer in a described Cu bond pad surface or the 2nd Cu bond pad surface.
Alternatively, in described step S2, first form adhesion layer in a described Cu bond pad surface or the 2nd Cu bond pad surface, and then by described first wafer to be bonded or the second thinning back side of silicon wafer to be bonded.
Alternatively, described adhesion layer is Ta/TaN composite bed.
Alternatively, in described step S2, physical gas-phase deposite method is utilized to form described adhesion layer.
Alternatively, in described step S2, adopt chemical and mechanical grinding method by described first wafer to be bonded or the second thinning back side of silicon wafer to be bonded.
Alternatively, with described step S3, bonding temperature scope is 23 ~ 28 DEG C, and bonding time is 8 ~ 15 seconds.
Alternatively, the thickness range of described adhesion layer is 100 ~ 300 dusts.
Alternatively, a described Cu pad and the 2nd Cu pad are circular or square.
As mentioned above, wafer bonding method of the present invention, has following beneficial effect: 1) the present invention formed adhesion layer in Cu bond pad surface before wafer bonding, and this adhesion layer can be used as protective layer, stop between the wafer of bonding and Cu diffusion occurs, and strengthen the bonding force of bond area; 2) the present invention is by thinning back side of silicon wafer before wafer bonding, can avoid the damage of para-linkage point in wafer thinning process.The present invention carries out above-mentioned process to wafer before wafer bonding effectively can strengthen bonding force between wafer, reduces damaged metal, and after reducing bonding, the probability peeled off occurs wafer.
Accompanying drawing explanation
Fig. 1 is shown as the process chart of wafer bonding method of the present invention.
Fig. 2 is shown as the process chart of wafer bonding method of the present invention in embodiment one.
Fig. 3 is shown as the generalized section of the first wafer to be bonded in wafer bonding method of the present invention.
Fig. 4 is shown as the generalized section of the second wafer to be bonded in wafer bonding method of the present invention.
Fig. 5 is shown as the schematic diagram forming adhesion layer in wafer bonding method of the present invention in a Cu bond pad surface.
Fig. 6 is shown as wafer bonding method of the present invention by the schematic diagram of the first thinning back side of silicon wafer to be bonded.
Fig. 7 is shown as wafer bonding method of the present invention by the schematic diagram of the first wafer to be bonded and the second wafer bonding to be bonded.
Fig. 8 is shown as the process chart of wafer bonding method of the present invention in embodiment two.
Fig. 9 is shown as wafer bonding method of the present invention by the schematic diagram of the first thinning back side of silicon wafer to be bonded.
One Cu bond pad surface of the first crystal column surface to be bonded that Figure 10 is shown as in wafer bonding method of the present invention after thinning forms the schematic diagram of adhesion layer.
Figure 11 is shown as the process chart of wafer bonding method of the present invention in embodiment three.
Figure 12 is shown as the schematic diagram forming adhesion layer in wafer bonding method of the present invention in the 2nd Cu bond pad surface.
Element numbers explanation
S1 ~ S4 step
1 first wafer to be bonded
2 the one Cu pads
3 adhesion layers
4 second wafers to be bonded
5 the 2nd Cu pads
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to Fig. 1 to Figure 12.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
The invention provides a kind of wafer bonding method, refer to Fig. 1, be shown as the process chart of the method, at least comprise the following steps:
Step S1: the first wafer to be bonded and the second wafer to be bonded are provided, described first crystal column surface to be bonded is formed with some Cu pads, and described second crystal column surface to be bonded is formed with the 2nd corresponding Cu pad of a some and described Cu pad locations;
Step S2: form adhesion layer in a described Cu bond pad surface or the 2nd Cu bond pad surface, and by described first wafer to be bonded or the second thinning back side of silicon wafer to be bonded;
Step S3: by a described Cu pad and the 2nd Cu pad alignment, by described first wafer to be bonded and the second wafer bonding to be bonded.
Concrete technical scheme of the present invention is described in detail below by specific embodiment.
Embodiment one
Refer to Fig. 2, the invention provides a kind of wafer bonding method, at least comprise the following steps:
Step S1: the first wafer to be bonded and the second wafer to be bonded are provided, described first crystal column surface to be bonded is formed with some Cu pads, and described second crystal column surface to be bonded is formed with the 2nd corresponding Cu pad of a some and described Cu pad locations;
Step S2: form adhesion layer in a described Cu bond pad surface;
Step S3: by described first thinning back side of silicon wafer to be bonded;
Step S4: by a described Cu pad and the 2nd Cu pad alignment, by described first wafer to be bonded and the second wafer bonding to be bonded.
First step S1 is performed: refer to Fig. 1 and Fig. 2, be shown as the sectional structure chart of the first wafer 1 to be bonded and the second wafer 2 to be bonded respectively, described first wafer 1 surface to be bonded is formed with some Cu pads 2, and described second wafer 4 surface to be bonded is formed with the 2nd corresponding Cu pad 5 of some and described Cu pad 2 position.
Concrete, described first wafer 1 to be bonded and the second wafer 2 to be bonded include but not limited to the conventional semiconductor wafers such as Si, Ge, SOI, GOI, silicon integrated circuit or photoelectric device etc. is formed with, for being combined into three dimensional integrated circuits in described first wafer 1 to be bonded and the second wafer 2 to be bonded.A described Cu pad 2 and the 2nd Cu pad 5 include but not limited to the shapes such as circular or square, as the bonding point of follow-up bonding.
Then perform step S2: refer to Fig. 5, form adhesion layer 3 on described Cu pad 2 surface.
Concrete, by physical vaporous deposition (PVD) as the methods such as sputtering, evaporation as described in adhesion layer 3 as described in a Cu pad 2 surface formation, the thickness range of described adhesion layer 3 is 100 ~ 300 dusts.Described adhesion layer 3 is preferably Ta/TaN composite bed; can as protective layer; phase counterdiffusion occurs between a Cu pad with the 2nd Cu pad after preventing bonding causes bonding face to weaken; described adhesion layer 3 can also strengthen the bonding force of a Cu pad and the 2nd Cu pad in bonding process, makes a Cu pad be combined more tight with the 2nd Cu pad.
Perform step S3 again: refer to Fig. 6, by described first wafer 1 thinning back side to be bonded.
Because some in three dimensional integrated circuits layer or all layers all need to make on independent wafer respectively complete, and then carry out bonding.Because accurate initial wafer thickness is thicker, therefore need to carry out thinning to its back side further, retain the device layer in front simultaneously.In this step, a wafer, i.e. described first wafer 1 thinning back side to be bonded above inciting somebody to action before two panels wafer bonding, can effectively prevent the damage of thinning process to Cu-Cu bonding.
In addition, described second wafer 1 to be bonded still can retain thicker back side thickness, is beneficial to supporting device.Described second wafer 1 to be bonded can comprise one or more layers device layer, and described multilayer device layer can be formed by the wafer bonding that multi-disc is comprised device layer in advance, also can be made by front device technology and back side device technology in same wafer.
Concrete, adopt chemical and mechanical grinding method by described first wafer 1 thinning back side to be bonded.Cmp (ChemicalMechanicalPolishing, CMP) technique is also referred to as chemical-mechanical planarization (ChemicalMechanicalPlanarization), it is a complicated technical process, it is contacted with the lapped face of grinding pad by crystal column surface, then, by the relative motion between crystal column surface and lapped face by flattening wafer surface, usual employing chemical-mechanical grinding device, carries out chemical mechanical milling tech also referred to as grinder station or polishing machine platform.Cmp can obtain the surface of relative smooth.
Finally perform step S4: refer to Fig. 7, aimed at the 2nd Cu pad 5 by a described Cu pad 2, by described first wafer 1 to be bonded and the second wafer 4 bonding to be bonded.
Concrete, certain pressure is applied to described first wafer 1 to be bonded and the second wafer 4 to be bonded, bonding temperature scope is 23 ~ 28 DEG C, bonding time is 8 ~ 15 seconds, make good contact between a described Cu pad 2 and the 2nd Cu pad 5, form bonding point, described first wafer 1 to be bonded and the second wafer 4 to be bonded are firmly combined into three dimensional integrated circuits.
Wafer bonding method of the present invention carried out a series of process to wafer to be bonded before wafer bonding, wherein, form adhesion layer in Cu bond pad surface before bonding, this adhesion layer can be used as protective layer, stop between bonding point and Cu diffusion occurs, and strengthen the bonding force of bond area; The present invention is also before bonding by thinning back side of silicon wafer, the damage of para-linkage point in wafer thinning process can be avoided, therefore, the present invention effectively can strengthen the bonding force between wafer, reduce damaged metal, after reducing bonding there is the probability peeled off in wafer, thus obtain three dimensional integrated circuits of good performance.
Embodiment two
The present embodiment adopts substantially identical technical scheme with embodiment one, and difference is it is first form adhesion layer in a described Cu bond pad surface in embodiment one, and then by described first thinning back side of silicon wafer to be bonded; And in the present embodiment, be first by described first thinning back side of silicon wafer to be bonded, and then form adhesion layer in a described Cu bond pad surface.
Refer to Fig. 8, the invention provides a kind of wafer bonding method, at least comprise the following steps:
Step S1: the first wafer to be bonded and the second wafer to be bonded are provided, described first crystal column surface to be bonded is formed with some Cu pads, and described second crystal column surface to be bonded is formed with the 2nd corresponding Cu pad of a some and described Cu pad locations;
Step S2: by described first thinning back side of silicon wafer to be bonded;
Step S3: form adhesion layer in a described Cu bond pad surface;
Step S4: by a described Cu pad and the 2nd Cu pad alignment, by described first wafer to be bonded and the second wafer bonding to be bonded.
First step S1 is performed: refer to Fig. 1 and Fig. 2, be shown as the sectional structure chart of the first wafer 1 to be bonded and the second wafer 2 to be bonded respectively, described first wafer 1 surface to be bonded is formed with some Cu pads 2, and described second wafer 4 surface to be bonded is formed with the 2nd corresponding Cu pad 5 of some and described Cu pad 2 position.
Concrete, described first wafer 1 to be bonded and the second wafer 2 to be bonded include but not limited to the conventional semiconductor wafers such as Si, Ge, SOI, GOI, silicon integrated circuit or photoelectric device etc. is formed with, for being combined into three dimensional integrated circuits in described first wafer 1 to be bonded and the second wafer 2 to be bonded.A described Cu pad 2 and the 2nd Cu pad 5 are the shape such as circular or square, as the bonding point of follow-up bonding.
Then step S2 is performed: refer to Fig. 9, by described first wafer 1 thinning back side to be bonded.
Because some in three dimensional integrated circuits layer or all layers all need to make on independent wafer respectively complete, and then carry out bonding.Because accurate initial wafer thickness is thicker, therefore need to carry out thinning to its back side further, retain the device layer in front simultaneously.In this step, a wafer, i.e. described first wafer 1 thinning back side to be bonded above inciting somebody to action before two panels wafer bonding, can effectively prevent the damage of thinning process to Cu-Cu bonding.
In addition, described second wafer 1 to be bonded still can retain thicker back side thickness, is beneficial to supporting device.Described second wafer 1 to be bonded can comprise one or more layers device layer, and described multilayer device layer can be formed by the wafer bonding that multi-disc is comprised device layer in advance, also can be made by front device and back side device technology in same wafer.
Concrete, adopt chemical and mechanical grinding method by described first wafer 1 thinning back side to be bonded, obtain the surface of relative smooth.
Perform step S3 again: refer to Figure 10, form adhesion layer 3 on described Cu pad 2 surface.
One Cu pad 2 surface of this step the first crystal column surface to be bonded after thinning forms adhesion layer 3, can reduce the probability that described adhesion layer 3 is contaminated or damage, more be conducive to forming the second best in quality bonding point in follow-up bonding process.
Concrete, form described adhesion layer 3 by physical vaporous deposition (PVD) on described Cu pad 2 surface, the thickness range of described adhesion layer 3 is 100 ~ 300 dusts.Described adhesion layer 3 is preferably Ta/TaN composite bed; can as protective layer; phase counterdiffusion occurs between a Cu pad with the 2nd Cu pad after preventing bonding causes bonding face to weaken; described adhesion layer 3 can also strengthen the bonding force of a Cu pad and the 2nd Cu pad in bonding process, makes a Cu pad be combined more tight with the 2nd Cu pad.
Finally perform step S4: refer to Fig. 7, aimed at the 2nd Cu pad 5 by a described Cu pad 2, by described first wafer 1 to be bonded and the second wafer 4 bonding to be bonded.
Concrete, certain pressure is applied to described first wafer 1 to be bonded and the second wafer 4 to be bonded, bonding temperature scope is 23 ~ 28 DEG C, bonding time is 8 ~ 15 seconds, make good contact between a described Cu pad 2 and the 2nd Cu pad 5, form bonding point, described first wafer 1 to be bonded and the second wafer 4 to be bonded are firmly combined into three dimensional integrated circuits.
Wafer bonding method of the present invention carried out a series of process to wafer to be bonded before wafer bonding, wherein, by thinning back side of silicon wafer before bonding, can avoid the damage of para-linkage point in wafer thinning process, and the present invention forms adhesion layer in Cu bond pad surface after thinning, before bonding, can prevent adhesion layer in thinning process contaminated or damage, this adhesion layer can be used as protective layer, stops between bonding point and Cu diffusion occurs, and strengthen the bonding force of bond area; Therefore, the present invention effectively can strengthen the bonding force between wafer, reduces damaged metal, and after reducing bonding, the probability peeled off occurs wafer, obtains three dimensional integrated circuits of good performance.
Embodiment three
The present embodiment and embodiment one and embodiment two are based on identical inventive concept, difference is pointed out to be, in embodiment one and embodiment two, form adhesion layer, carry out thinning back side of silicon wafer and all operate on same a slice wafer to be bonded, and in the present embodiment, form adhesion layer and carry out thinning back side of silicon wafer and operate respectively on two panels wafer to be bonded.
Refer to Figure 11, the invention provides a kind of wafer bonding method, at least comprise the following steps:
Step S1: the first wafer to be bonded and the second wafer to be bonded are provided, described first crystal column surface to be bonded is formed with some Cu pads, and described second crystal column surface to be bonded is formed with the 2nd corresponding Cu pad of a some and described Cu pad locations;
Step S2: form adhesion layer in described 2nd Cu bond pad surface, and by described first thinning back side of silicon wafer to be bonded;
Step S3: by a described Cu pad and the 2nd Cu pad alignment, by described first wafer to be bonded and the second wafer bonding to be bonded.
First step S1 is performed: refer to Fig. 1 and Fig. 2, be shown as the sectional structure chart of the first wafer 1 to be bonded and the second wafer 2 to be bonded respectively, described first wafer 1 surface to be bonded is formed with some Cu pads 2, and described second wafer 4 surface to be bonded is formed with the 2nd corresponding Cu pad 5 of some and described Cu pad 2 position.
Concrete, described first wafer 1 to be bonded and the second wafer 2 to be bonded include but not limited to the conventional semiconductor wafers such as Si, Ge, SOI, GOI, silicon integrated circuit or photoelectric device etc. is formed with, for being combined into three dimensional integrated circuits in described first wafer 1 to be bonded and the second wafer 2 to be bonded.A described Cu pad 2 and the 2nd Cu pad 5 are the shape such as circular or square, as the bonding point of follow-up bonding.
Then perform step S2: refer to Figure 12, form adhesion layer 3 on described 2nd Cu pad 5 surface, and by described first wafer 1 thinning back side (as shown in Figure 9) to be bonded.
Concrete, form described adhesion layer 3 by physical vaporous deposition (PVD) on described Cu pad 2 surface, the thickness range of described adhesion layer 3 is 100 ~ 300 dusts.Described adhesion layer 3 is preferably Ta/TaN composite bed; can as protective layer; phase counterdiffusion occurs between a Cu pad with the 2nd Cu pad after preventing bonding causes bonding face to weaken; described adhesion layer 3 can also strengthen the bonding force of a Cu pad and the 2nd Cu pad in bonding process, makes a Cu pad be combined more tight with the 2nd Cu pad.
Because some in three dimensional integrated circuits layer or all layers all need to make on independent wafer respectively complete, and then carry out bonding.Because accurate initial wafer thickness is thicker, therefore need to carry out thinning to its back side further, retain the device layer in front simultaneously.In this step, a wafer, i.e. described first wafer 1 thinning back side to be bonded above inciting somebody to action before two panels wafer bonding, can effectively prevent the damage of thinning process to Cu-Cu bonding.
In addition, described second wafer 1 to be bonded still can retain thicker back side thickness, is beneficial to supporting device.Described second wafer 1 to be bonded can comprise one or more layers device layer, and described multilayer device layer can be formed by the wafer bonding that multi-disc is comprised device layer in advance, also can be made by front device and back side device technology in same wafer.
Concrete, adopt chemical and mechanical grinding method by described first wafer 1 thinning back side to be bonded, obtain the surface of relative smooth.
Finally perform step S3: refer to Fig. 7, aimed at the 2nd Cu pad 5 by a described Cu pad 2, by described first wafer 1 to be bonded and the second wafer 4 bonding to be bonded.
Concrete, certain pressure is applied to described first wafer 1 to be bonded and the second wafer 4 to be bonded, bonding temperature scope is 23 ~ 28 DEG C, bonding time is 8 ~ 15 seconds, make good contact between a described Cu pad 2 and the 2nd Cu pad 5, form bonding point, described first wafer 1 to be bonded and the second wafer 4 to be bonded are firmly combined into three dimensional integrated circuits.
Wafer bonding method of the present invention processes two panels wafer to be bonded respectively before wafer bonding, wherein, form adhesion layer in the 2nd Cu bond pad surface before bonding, this adhesion layer can be used as protective layer, stop between bonding point and Cu diffusion occurs, and strengthen the bonding force of bond area; Further, the present invention, before bonding by the first thinning back side of silicon wafer to be bonded, can avoid the damage of para-linkage point in wafer thinning process.Therefore, the present invention effectively can strengthen the bonding force between wafer, reduces damaged metal, and after reducing bonding, the probability peeled off occurs wafer, obtains three dimensional integrated circuits of good performance.
In sum, wafer bonding method of the present invention, has following beneficial effect: 1) the present invention formed adhesion layer in Cu bond pad surface before wafer bonding, and this adhesion layer can be used as protective layer, stop between the wafer of bonding and Cu diffusion occurs, and strengthen the bonding force of bond area; 2) the present invention is by thinning back side of silicon wafer before wafer bonding, can avoid the damage of para-linkage point in wafer thinning process.The present invention carries out above-mentioned process to wafer before wafer bonding effectively can strengthen bonding force between wafer, reduces damaged metal, and after reducing bonding, the probability peeled off occurs wafer, thus improves the performance of three dimensional integrated circuits device.So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (9)
1. a wafer bonding method, is characterized in that, at least comprises the following steps:
S1: the first wafer to be bonded and the second wafer to be bonded are provided, described first crystal column surface to be bonded is formed with some Cu pads, and described second crystal column surface to be bonded is formed with the 2nd corresponding Cu pad of a some and described Cu pad locations;
S2: form adhesion layer in a described Cu bond pad surface or the 2nd Cu bond pad surface, and by described first wafer to be bonded or the second thinning back side of silicon wafer to be bonded;
S3: by a described Cu pad and the 2nd Cu pad alignment, by described first wafer to be bonded and the second wafer bonding to be bonded.
2. wafer bonding method according to claim 1, it is characterized in that: in described step S2, first by described first wafer to be bonded or the second thinning back side of silicon wafer to be bonded, and then adhesion layer is formed in a described Cu bond pad surface or the 2nd Cu bond pad surface.
3. wafer bonding method according to claim 1, it is characterized in that: in described step S2, first adhesion layer is formed in a described Cu bond pad surface or the 2nd Cu bond pad surface, and then by described first wafer to be bonded or the second thinning back side of silicon wafer to be bonded.
4. wafer bonding method according to claim 1, is characterized in that: described adhesion layer is Ta/TaN composite bed.
5. wafer bonding method according to claim 1, is characterized in that: in described step S2, utilizes physical gas-phase deposite method to form described adhesion layer.
6. wafer bonding method according to claim 1, is characterized in that: in described step S2, adopts chemical and mechanical grinding method by described first wafer to be bonded or the second thinning back side of silicon wafer to be bonded.
7. wafer bonding method according to claim 1, is characterized in that: with described step S3, and bonding temperature scope is 23 ~ 28 DEG C, and bonding time is 8 ~ 15 seconds.
8. wafer bonding method according to claim 1, is characterized in that: the thickness range of described adhesion layer is 100 ~ 300 dusts.
9. wafer bonding method according to claim 1, is characterized in that: a described Cu pad and the 2nd Cu pad are for circular or square.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298452A (en) * | 2016-08-29 | 2017-01-04 | 中国科学院微电子研究所 | Wafer bonding method based on array type point pressure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050003652A1 (en) * | 2003-07-02 | 2005-01-06 | Shriram Ramanathan | Method and apparatus for low temperature copper to copper bonding |
| CN101656217A (en) * | 2008-08-18 | 2010-02-24 | 中芯国际集成电路制造(上海)有限公司 | System-in-package method |
| US20130270328A1 (en) * | 2010-07-21 | 2013-10-17 | Commissariat A L'energie Atomique Et Aux Ene Alt | Process for direct bonding two elements comprising copper portions and portions of dielectric materials |
| CN103794522A (en) * | 2014-01-24 | 2014-05-14 | 清华大学 | Wafer-wafer, chip-wafer and chip-chip bonding methods |
-
2014
- 2014-10-10 CN CN201410528965.8A patent/CN105575834A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050003652A1 (en) * | 2003-07-02 | 2005-01-06 | Shriram Ramanathan | Method and apparatus for low temperature copper to copper bonding |
| CN101656217A (en) * | 2008-08-18 | 2010-02-24 | 中芯国际集成电路制造(上海)有限公司 | System-in-package method |
| US20130270328A1 (en) * | 2010-07-21 | 2013-10-17 | Commissariat A L'energie Atomique Et Aux Ene Alt | Process for direct bonding two elements comprising copper portions and portions of dielectric materials |
| CN103794522A (en) * | 2014-01-24 | 2014-05-14 | 清华大学 | Wafer-wafer, chip-wafer and chip-chip bonding methods |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298452A (en) * | 2016-08-29 | 2017-01-04 | 中国科学院微电子研究所 | Wafer bonding method based on array type point pressure |
| CN106298452B (en) * | 2016-08-29 | 2019-05-17 | 中国科学院微电子研究所 | Wafer bonding method based on array type point pressure |
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Application publication date: 20160511 |