CN105575420B - Static RAM - Google Patents
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- CN105575420B CN105575420B CN201410538416.9A CN201410538416A CN105575420B CN 105575420 B CN105575420 B CN 105575420B CN 201410538416 A CN201410538416 A CN 201410538416A CN 105575420 B CN105575420 B CN 105575420B
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Abstract
This application discloses a kind of storages of static random.Wherein, the static random storage includes：First bit line；The first transistor is connected to by source electrode and drain electrode between the first bit line and power supply or ground；N number of storage unit, each in N number of storage unit are used for memory level state, and level state includes high level and low level, and N is more than or equal to 1；N number of second transistor is corresponded with N number of storage unit, each in N number of second transistor is connected to by source electrode and drain electrode between corresponding storage unit and the grid of the first transistor；N number of first wordline is corresponded with N number of second transistor, each in N number of first wordline is connected to the grid of corresponding second transistor, and level state is read for controlling from corresponding storage unit.Present application addresses the low problems of Static RAM read data operation stability.
Description
Technical field
This application involves memory areas, in particular to a kind of Static RAM.
Background technology
Quick read/write operation may be implemented in Static RAM (SRAM).Fig. 1 is a kind of 6T according to prior art
The schematic diagram of Static RAM, as shown in Figure 1, each memory module of the 6T Static RAM includes 6 crystal
Pipe, is transistor PG-1, transistor PG-2, transistor PU-1, transistor PD-1, transistor PU-2 and transistor PD-2 respectively.
Transistor PU-1, transistor PD-1, transistor PU-2, transistor PD-2, power vd D and ground VSS collectively form storage unit, use
In memory level state, i.e. high level state and low level state, which includes two memory nodes, is storage respectively
Node Q and memory node QN, memory node Q and a pair of opposite level state of memory node QN storages.Wordline WL is connected to crystalline substance
The grid of body pipe PG-1 and transistor PG-2, for controlling from storage unit reading level state or electricity being written to storage unit
Level state.Transistor PG-1 is connected to by source electrode and drain electrode between the memory node Q of storage unit and bit line BL, transistor
PG-2 is connected to by source electrode and drain electrode between the memory node QN of storage unit and bit line BLB.
When wordline WL is high level, transistor PG-1 and transistor PG-2 are simultaneously turned on, and bit line BL can read and deposit
The level state of node Q is stored up, bit line BLB can read the level state of memory node QN, realize from storage unit and read number
According to.Likewise, for example to storage unit write-in high level " 1 ", high level is added in bit line BL first, corresponding bit line BLB adds
Enter low level, when wordline WL be high level when, transistor PG-1 and transistor PG-2 are simultaneously turned on, bit line BL, bit line BLB electricity
Level state is transmitted separately to memory node Q and memory node QN so that memory node Q is high level state " 1 ", corresponding to store
Node QN is low level state " 0 ", realizes to storage unit and data are written.
The 6T Static RAM can only realize single port read/write, and read-write efficiency is relatively low, and the T static randoms are deposited
The storage node voltage of reservoir can be influenced by read operation, and static noise margin value is smaller, and memory stability is too low.
Fig. 2 is a kind of dual-port static random access memory schematic diagram according to prior art, as shown in Fig. 2, the dual-port
On the basis of Static RAM 6T Static RAM shown in Fig. 1, transistor PGA2 and transistor are increased
PGB2 and bit line BL2, BL1B and wordline WLB, wherein transistor PGA2 is connected to bit line BL2 by source electrode or drain electrode,
Transistor PGB2 is connected to bit line BL1B by source electrode or drain electrode, and transistor PGA2 and transistor PGB2 grids are connected to wordline
WLB.Other elements are corresponding with element in Fig. 1 respectively in figure, and bit line BL1 corresponds to bit line BL, and bit line BL2B corresponds to bit line
BLB, transistor PGA1 correspond to transistor PG-1, and transistor PGB1 corresponds to transistor PG-2, and wordline WLA corresponds to wordline
WL。
The dual-port static random access memory may be implemented simultaneously from two port read/write, you can be held simultaneously from two
Mouth is written data or reads data from two ports, and read-write efficiency is improved, but the dual-port static random storage
The read-write operation of two ports of device can influence each other, and stability is also lower than traditional 6T Static RAM.
In order to improve the static noise margin and stability of Static RAM, manufactured 8T Static RAM and
10T Static RAM, Fig. 3 are that a kind of 8T Static RAM schematic diagram, Fig. 4 are according to existing according to prior art
A kind of 10T Static RAM schematic diagram of technology.
As shown in figure 3,8T Static RAM on the basis of 6T Static RAM shown in Fig. 1 by increasing
Transistor RPD and transistor RPG, bit line RBL are connected to memory node QN, transistor via transistor RPD and transistor RPG
The grid of RPG is connected to wordline RWL, and wordline RWL reads data, transistor PG-1 for controlling from Static RAM
It is connected to wordline WWL with transistor PG-2, data are written into Static RAM for controlling by bit line WWL, and the 8T is static
Random access memory other parts are the same as 6T Static RAM shown in FIG. 1.Due to the presence of transistor RPD and transistor RPG,
So that read port voltage does not interfere with the voltage of memory node QN, it is improved to the stability of Static RAM,
Static noise margin value becomes larger, but the 8T Static RAM can only execute single port read operation, and reading efficiency is relatively low.
As shown in figure 4,10T Static RAM is improved on the basis of 8T Static RAM, in crystal
Pipe RPD and the symmetrical positions transistor RPG increase two transistors, and the two transistors are connected to wordline RWL and position
Line RBL, bit line RBLB correspond to the bit line RBL in Fig. 3.The other parts of the 10T Static RAM are the same as 8T shown in Fig. 3
Static RAM.Differential type reading may be implemented in the 10T Static RAM, improves the access speed of memory,
And have higher stability, but each storage unit of 10T Static RAM include 10 transistors, area compared with
Greatly, it is unfavorable for Integrated manufacture.
To sum up, quick read/write operation may be implemented in static memory (SRAM), but reads static noise margin (RSNM)
Become worse and worse, stability is lower and lower.The reading static noise margin of dual-port (2RW, 2 reading-writing ports) static memory
It is more worse than traditional 6T static memories, although dual-port (2RW) static memory has faster access speed.For reality
It is existing high to read static noise margin, invent 8T static memories and 10T static memories, but its access speed and unit
Area is difficult to meet the requirements.
For the low problem of Static RAM read data operation stability in the prior art, not yet propose have at present
The solution of effect.
Invention content
The embodiment of the present application provides a kind of Static RAM, to solve Static RAM read data operation
The low problem of stability.
According to the one side of the embodiment of the present application, a kind of Static RAM is provided, including：First bit line；The
One transistor is connected to by source electrode and drain electrode between the first bit line and power supply or ground；N number of storage unit, N number of storage unit
In each be used for memory level state, level state includes high level and low level, and N is more than or equal to 1；N number of second crystal
Pipe is corresponded with N number of storage unit, each in N number of second transistor is connected to corresponding deposit by source electrode and drain electrode
Between storage unit and the grid of the first transistor；N number of first wordline corresponds, N number of first wordline with N number of second transistor
In each be connected to the grid of corresponding second transistor, read level state for controlling from corresponding storage unit.
Further, each storage unit in N number of storage unit includes：First memory node, for store with it is each
Level state of the level state of storage unit with phase；Second memory node, for storing and the level shape of each storage unit
The level state of state reverse phase；Wherein, each in N number of second transistor is connected to corresponding storage list by source electrode and drain electrode
Between the first memory node in member and the grid of the first transistor, alternatively, each in N number of second transistor passes through source electrode
And drain electrode is connected between the second memory node in corresponding storage unit and the grid of the first transistor.
Further, each storage unit in N number of storage unit includes：First phase inverter is connected to the first storage section
Between point and the second memory node；Second phase inverter is oppositely connected to the first memory node and relative to the first phase inverter
Between two memory nodes.
Further, each storage unit in N number of storage unit includes：First PMOS, is connected by source electrode and drain electrode
Between power supply and the first memory node, the grid of the first PMOS is connected to the second memory node；First NMOS, by source electrode and
Drain electrode is connected between the first memory node and ground, and the grid of the first NMOS is connected to the second memory node；2nd PMOS, passes through
Source electrode and drain electrode is connected between power supply and the second memory node, and the grid of the 2nd PMOS is connected to the first memory node；Second
NMOS is connected to by source electrode and drain electrode between the second memory node and ground, and the grid of the 2nd NMOS is connected to the first storage section
Point.
Further, which further includes：Second bit line；N number of third transistor, with N number of storage unit
It corresponds, each in N number of third transistor is connected to corresponding storage unit and the second bit line by source electrode and drain electrode
Between；N number of second wordline is corresponded with N number of third transistor, each in N number of second wordline is connected to corresponding the
Level state is written for controlling to corresponding storage unit in the grid of three transistors.
Further, which further includes：Third bit line；N number of 4th transistor, with N number of storage unit
It corresponds, each in N number of 4th transistor is connected to corresponding storage unit and third bit line by source electrode and drain electrode
Between；N number of third wordline is corresponded with N number of 4th transistor, each in N number of third wordline is connected to corresponding the
Level state is written for controlling to corresponding storage unit in the grid of four transistors.
Further, which further includes：Processor connects the first bit line and N number of first wordline, is used for
Any first wordline output control signal into N number of first wordline, and read and any first wordline pair from the first bit line
The level state for the storage unit answered, control signal are used to control source electrode and the leakage of the corresponding second transistor of any first wordline
Conducting between pole.
Further, the first transistor and second transistor are NMOS.
In Static RAM provided by the present application, the first transistor is controlled by the first wordline and second transistor is real
It now reads to keep the level state of storage unit constant when static memory data, has reached raising Static RAM and read number
According to the purpose of operational stability, and then solves the low technical problem of Static RAM read data operation stability.
Description of the drawings
Attached drawing described herein is used for providing further understanding of the present application, constitutes part of this application, this Shen
Illustrative embodiments and their description please do not constitute the improper restriction to the application for explaining the application.In the accompanying drawings：
Fig. 1 is a kind of schematic diagram of 6T Static RAM according to prior art；
Fig. 2 is a kind of dual-port static random access memory schematic diagram according to prior art；
Fig. 3 is a kind of 8T Static RAM schematic diagram according to prior art；
Fig. 4 is a kind of 10T Static RAM schematic diagram according to prior art；
Fig. 5 is the schematic diagram according to the Static RAM of the embodiment of the present application；And
Fig. 6 is the schematic diagram according to the memory module of the embodiment of the present application.
Specific implementation mode
The application is described in detail below with reference to attached drawing and in conjunction with the embodiments.It should be noted that not conflicting
In the case of, the features in the embodiments and the embodiments of the present application can be combined with each other.
In order to make those skilled in the art more fully understand application scheme, below in conjunction in the embodiment of the present application
Attached drawing, technical solutions in the embodiments of the present application are clearly and completely described, it is clear that described embodiment is only
The embodiment of the application part, instead of all the embodiments.Based on the embodiment in the application, ordinary skill people
The every other embodiment that member is obtained without making creative work should all belong to the model of the application protection
It encloses.
It should be noted that term " first " in the description and claims of this application and above-mentioned attached drawing, "
Two " etc. be for distinguishing similar object, without being used to describe specific sequence or precedence.It should be appreciated that using in this way
Data can be interchanged in the appropriate case, so as to embodiments herein described herein can in addition to illustrating herein or
Sequence other than those of description is implemented.In addition, term " comprising " and " having " and their any deformation, it is intended that cover
It includes to be not necessarily limited to for example, containing the process of series of steps or unit, method, system, product or equipment to cover non-exclusive
Those of clearly list step or unit, but may include not listing clearly or for these processes, method, product
Or the other steps or unit that equipment is intrinsic.
According to the embodiment of the present application, a kind of Static RAM is provided, Fig. 5 is the static state according to the embodiment of the present application
Random access memory schematic diagram.
As shown in figure 5, the Static RAM includes：First bit line 20, the first transistor 10, N number of storage unit, N
A second transistor and N number of first wordline.
The first transistor 10 is connected to by source electrode and drain electrode between first bit line 20 and power supply or ground；
N number of storage unit, each in N number of storage unit are used for memory level state, and level state includes high level
And low level, N are more than or equal to 1；
N number of second transistor is corresponded with N number of storage unit, each in N number of second transistor by source electrode and
Drain electrode is connected between corresponding storage unit and the grid of the first transistor 10；
N number of first wordline is corresponded with N number of second transistor, each in N number of first wordline is connected to corresponding
The grid of second transistor reads level state for controlling from corresponding storage unit.
As shown in figure 5, the static random access memory includes N memory modules, each memory module in N number of memory module
30 include storage unit 301, second transistor 302 and the first wordline 303.A following storage according in N number of storage unit
The present embodiment is illustrated for module 30.
The source electrode of the first transistor 10 is grounded, which is connected to second transistor via internal wiring IL
The drain electrode of 302 source electrode, the first transistor 10 is connected to the first bit line 20, and the first bit line 20 is used as output line, with external electricity
Road (not shown) is connected, and the data by being stored in 20 output storage of the first bit line or writes outer input data
Enter to memory.The drain electrode of second transistor 302 is connected to storage unit 301, and grid is connected to the first wordline 303, this second
Read operation transmission channel of the transistor 302 as memory, when the first 303 high level of wordline, which leads
Logical, the data that storage unit 301 stores just are transmitted to the first bit line 20 by second transistor 302, realize memory data
Read operation.
In the data procedures for reading the Static RAM, when the first 303 high level of wordline, second transistor
302 conductings, the level state of storage unit 301 can be read from the first bit line 20, due to 10 grid of the first transistor and source
It is off-state between pole, the grid of the first transistor 10 does not have electric current to flow through, therefore brilliant by second transistor 302 and first
The read operation that body pipe 10 executes can keep the level state of storage unit 301 constant, improve from Static RAM
It is low to solve the problems, such as that Static RAM reads data operational stability for the stability for reading data.
Optionally, each storage unit 301 in above-mentioned N number of storage unit includes：First memory node 3013 and second
Memory node 3014.
First memory node 3013, for storing the level shape with the level state of above-mentioned each storage unit 301 with phase
State.
Second memory node 3014, for storing and the level shape of the level state reverse phase of above-mentioned each storage unit 301
State；Wherein, each in above-mentioned N number of second transistor 302 is connected to by source electrode and drain electrode in corresponding storage unit 301
The first memory node 3013 and the grid of the first transistor 10 between.
It realizes and stores from figure 5 it can be seen that second transistor 302 is connected to the second memory node 3014 by drain electrode
The connection of unit.Storage unit 301 stores level state identical with the storage unit 301 by the first memory node 3013,
Second memory node 3014 is used to store and the level state of 301 reverse phase of storage unit, for example, what storage unit 301 stored
When level state is " 1 ", then the level state of the first memory node 3013 storage is " 1 ", the storage of the second memory node 3014
Level state is " 0 ".
Preferably, the first memory node 3013 and the second memory node 3014 of realization storage unit 301 for convenience
Level state be level state opposite each other, each storage unit 301 in above-mentioned N number of storage unit includes：First is anti-
Phase device 3011 and the second phase inverter 3012.
First phase inverter 3011 is connected between the first memory node 3013 and the second memory node 3014.
Second phase inverter 3012 is oppositely connected to the first memory node 3013 and second relative to the first phase inverter 3011
Between memory node 3014.
The first end of first phase inverter 3011 is connected to the first memory node 3013, and the second end of the first phase inverter 3011 connects
It is connected to the second memory node 3014.And the first end of the second phase inverter 3012 is connected to the second memory node 3014, the second reverse phase
The second end of device 3012 is connected to the first memory node 3013, realizes the reverse phase of the first phase inverter 3011 and the second phase inverter 3012
Connection.The level state reverse phase that phase inverter is used to input, for example, level state " 1 " obtains level state via phase inverter
“0”.Two opposite level states can be easily obtained by phase inverter, realize the storage of the first memory node 3013 and second
The reverse phase of the level state of node 3014.
The concrete structure of memory module in Fig. 5 is as shown in fig. 6, as shown in fig. 6, the memory module includes storage unit
301.Preferably, in order to reduce the power consumption of Static RAM, each storage unit 301 in above-mentioned N number of storage unit is wrapped
It includes：First PMOS transistor PU-1, the first NMOS transistor PD-1, the second PMOS transistor PU-2 and the second NMOS transistor
PD-2。
First PMOS transistor PU-1 is connected to by source electrode and drain electrode between power vd D and the first memory node Q, the
The grid of one PMOS transistor PU-1 is connected to the second memory node QN.
First NMOS transistor PD-1 is connected to by source electrode and drain electrode between the first memory node Q and ground VSS, first
The grid of NMOS transistor PD-1 is connected to the second memory node QN.
Second PMOS transistor PU-2, by source electrode and drain electrode be connected to power vd D and the second memory node QN it
Between, the grid of the second PMOS transistor PU-2 is connected to the first memory node Q；
Second NMOS transistor PD-2 is connected to by source electrode and drain electrode between the second memory node QN and ground VSS,
The grid of the second NMOS transistor PD-2 is connected to the first memory node Q.
As shown in fig. 6, storage unit 301 includes：First PMOS transistor PU-1, the first NMOS transistor PD-1, second
PMOS transistor PU-2, the second NMOS transistor PD-2, power vd D and ground VSS.Wherein, the first PMOS transistor PU-1 and
The grid of one NMOS transistor PD-1 is commonly connected to the second memory node QN, and the drain electrode of the first PMOS transistor PU-1 is connected to
The source electrode of power vd D, the first PMOS transistor PU-1 are connected to the first memory node Q, the drain electrode of the first NMOS transistor PD-1
It is connected to the first memory node Q, the source electrode of the first NMOS transistor PD-1 is connected to the ground VSS.Likewise, the second PMOS transistor
The drain electrode that the grid of PU-2 and the second NMOS transistor PD-2 are connected to the first memory node Q, the second PMOS transistor PU-2 connects
It is connected to power vd D, the drain electrode of the source electrode of the second PMOS transistor PU-2 and the second NMOS transistor PD-2 is connected to the second storage
Node QN, the source electrode of the second NMOS transistor PD-2 are connected to the ground VSS.
It is interconnected to constitute by the first PMOS transistor PU-1, the first NMOS transistor PD-1, power vd D and ground VSS
One CMOS inverter so that the level state reverse phase of the first memory node Q obtains the level state of the second memory node QN.Together
Sample, the second PMOS transistor PU-2, the second NMOS transistor PD-2, power vd D and ground VSS, which are connected with each other, also constitutes one
CMOS inverter so that the level state reverse phase of the second memory node QN obtains the level state of the first memory node Q.CMOS is anti-
Phase device quiescent dissipation is low, and strong antijamming capability, and storage unit can reduce entire static random using CMOS inverter and deposit
The power consumption and anti-interference ability of reservoir.
Preferably, in order to further increase the efficiency of the data writing operation into Static RAM, which deposits
Reservoir further includes：Second bit line 308, N number of third transistor and N number of second wordline.
N number of third transistor is corresponded with N number of storage unit, each in N number of third transistor by source electrode and
Drain electrode is connected between corresponding storage unit and the second bit line 308；
N number of second wordline is corresponded with N number of third transistor, each in N number of second wordline is connected to corresponding
Level state is written for controlling to corresponding storage unit in the grid of third transistor 304.
As shown in figure 5, the grid of third transistor 304 is connected to the second wordline 306, which passes through source
Pole is connected to the second bit line 308, and the drain electrode of the third transistor 304 is connected to the first memory node 3013.Second wordline 306 is used
Data are written to storage unit 301 in control.When the second wordline 306 is high level, third transistor 304 is connected, and becomes one
At this time level state can be written into storage unit 301 by the second bit line 308 in a transmission path.By above-mentioned quiet
Increase the access of a third transistor 306 and the second bit line 308 composition in state random access memory as write port, end is write by this
Data are written to Static RAM in mouth, have reached the efficiency for improving and data being written into Static RAM.
Preferably, in order to further increase to Static RAM be written data speed, the Static RAM
Further include：Third bit line 309, N number of 4th transistor and N number of third wordline.
N number of 4th transistor is corresponded with N number of storage unit, each in N number of 4th transistor by source electrode and
Drain electrode is connected between corresponding storage unit and third bit line 309；
N number of third wordline is corresponded with N number of 4th transistor, each in N number of third wordline is connected to corresponding
The grid of 4th transistor is deposited for controlling to read level state from corresponding storage unit 301, and/or control to corresponding
Level state is written in storage unit.
The grid of 4th transistor 305 is connected to third wordline 307, and the drain electrode of the 4th transistor 305 is connected to second
The source electrode of memory node 3014, the 4th transistor 305 is connected to third bit line 309.Third wordline 307 is brilliant by control the 4th
The conducting of body pipe 305, which reaches to control to read level state from storage unit 301, and/or control to storage unit 301 with cut-off, to be write
Enter level state.When third wordline 307 is high level, the conducting of the 4th transistor 305 becomes a data path, by this
Data can be written to storage unit 301, to increase a memory write port namely the 4th transistor 305 in data path
It is used as write port with third bit line 309, data are written into Static RAM by the write port, are improved to static random
The rate of write-in data in memory.
Optionally, which further includes：Processor connects the first bit line 20 and N number of first wordline, is used for
Any first wordline output control signal into N number of first wordline, and read and any first wordline from the first bit line 20
The level state of corresponding storage unit, control signal be used for control the corresponding second transistor of any first wordline source electrode and
Conducting between drain electrode.
Preferably, the first transistor 10 and second transistor 302 are NMOS.
The power consumption of CMOS transistor is less than the power consumption of TTL transistors, and has stronger anti-interference.CMOS transistor
Including NMOS transistor and PMOS transistor, wherein NMOS transistor is connected it is required that the voltage difference of grid and source electrode is more than
Certain value could be connected, and be suitable for the case where source electrode is grounded, and the electricity it is required that grid and source electrode is connected in PMOS transistor
Pressure difference, which is less than certain value, to be connected, and power supply is connect suitable for source electrode.In addition, NMOS transistor conducting resistance is less than PMOS crystal
The conducting resistance of pipe is less than the conduction loss of PMOS transistor to the conduction loss of NMOS transistor, therefore uses accordingly
NMOS transistor can reduce the loss of Static RAM.
This application provides a kind of preferred embodiments further to be explained to the application, but noticeable
It is that the preferred embodiment is intended merely to preferably describe the application, does not constitute and improperly limits the application.
It can be seen from the above description that the application realizes following technique effect：
1) by the way that the grid of the first transistor to be connected to the source electrode of second transistor via internal wiring ILB so that from quiet
In state random access memory read data when the voltage of the second memory node of storage unit can be kept to remain unchanged, improve from
The stability that data are read in Static RAM solves and reads that data stability is low asks from Static RAM
Topic.
2) Static RAM may be implemented 2 ports while write data, first, controlling three by the second wordline 306
Transistor 304 is realized, and data are written into static memory, are realized second is that controlling the 4th transistor 305 by third wordline 307
Data are written into static memory, two ports can data be written into random access memory simultaneously, improve static random
The efficiency of data is written in memory.There is Static RAM 1 data reading port, the static memory to pass through the first bit line
20 control second transistors 302 and the first transistor 10 are realized from memory read data.In addition, the Static RAM packet
The transistor number contained is few, and size is small, and the stability of memory is identical as 8T Static RAM in the prior art.
3) transistor of the Static RAM is formed using MOS transistor, and power consumption is relatively low, reduces static random and deposits
The power consumption of reservoir.
The foregoing is merely the preferred embodiments of the application, are not intended to limit this application, for the skill of this field
For art personnel, the application can have various modifications and variations.Within the spirit and principles of this application, any made by repair
Change, equivalent replacement, improvement etc., should be included within the protection domain of the application.
Claims (8)
1. a kind of Static RAM, which is characterized in that including：
First bit line；
The first transistor is connected to by source electrode and drain electrode between first bit line and power supply or ground；
N number of storage unit, each in N number of storage unit are used for memory level state, and the level state includes height
Level and low level, N are more than or equal to 1；
N number of second transistor is corresponded with N number of storage unit, each in N number of second transistor passes through source
Pole and drain electrode are connected between corresponding storage unit and the grid of the first transistor；
The first wordline of N items is corresponded with the N number of second transistor, and each in first wordline of N items is connected to pair
The grid for the second transistor answered reads level state for controlling from corresponding storage unit.
2. Static RAM according to claim 1, which is characterized in that each in N number of storage unit deposits
Storage unit includes：
First memory node, for storing the level state with the level state of each storage unit with phase；
Second memory node, for storing and the level state of the level state reverse phase of each storage unit；Wherein,
Each in N number of second transistor is connected to the first storage in corresponding storage unit by source electrode and drain electrode
Between node and the grid of the first transistor, alternatively, each in N number of second transistor passes through source electrode and drain electrode
It is connected to the second memory node in corresponding storage unit and between the grid of the first transistor.
3. Static RAM according to claim 2, which is characterized in that each in N number of storage unit deposits
Storage unit includes：
First phase inverter is connected between first memory node and second memory node；
Second phase inverter is oppositely connected to first memory node relative to first phase inverter and is stored with described second
Between node.
4. Static RAM according to claim 2, which is characterized in that each in N number of storage unit deposits
Storage unit includes：
First PMOS is connected to by source electrode and drain electrode between power supply and first memory node, the grid of the first PMOS
Pole is connected to second memory node；
First NMOS is connected to by source electrode and drain electrode between first memory node and ground, the grid of the first NMOS
It is connected to second memory node；
2nd PMOS is connected to by source electrode and drain electrode between power supply and second memory node, the grid of the 2nd PMOS
Pole is connected to first memory node；
2nd NMOS is connected to by source electrode and drain electrode between second memory node and ground, the grid of the 2nd NMOS
It is connected to first memory node.
5. Static RAM according to claim 1, which is characterized in that further include：
Second bit line；
N number of third transistor is corresponded with N number of storage unit, each in N number of third transistor passes through source
Pole and drain electrode are connected between corresponding storage unit and second bit line；
The second wordline of N items is corresponded with the N number of third transistor, and each in second wordline of N items is connected to pair
Level state is written for controlling to corresponding storage unit in the grid for the third transistor answered.
6. Static RAM according to any one of claim 1 to 5, which is characterized in that further include：
Third bit line；
N number of 4th transistor is corresponded with N number of storage unit, each in N number of 4th transistor passes through source
Pole and drain electrode are connected between corresponding storage unit and the third bit line；
N third wordline is corresponded with N number of 4th transistor, and each in the N third wordline is connected to pair
Level state is written for controlling to corresponding storage unit in the grid for the 4th transistor answered.
7. Static RAM according to any one of claim 1 to 5, which is characterized in that further include：
Processor connects first bit line and first wordline of N items, for any the into described N articles the first wordline
One wordline output control signal, and read from first bit line electricity of storage unit corresponding with any first wordline
Level state, the control signal are used to control between the source electrode and drain electrode of the corresponding second transistor of any first wordline
Conducting.
8. Static RAM according to any one of claim 1 to 5, which is characterized in that the first transistor
It is NMOS with the second transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410538416.9A CN105575420B (en) | 2014-10-13 | 2014-10-13 | Static RAM |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410538416.9A CN105575420B (en) | 2014-10-13 | 2014-10-13 | Static RAM |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105575420A CN105575420A (en) | 2016-05-11 |
| CN105575420B true CN105575420B (en) | 2018-08-03 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102047339A (en) * | 2008-06-19 | 2011-05-04 | 德克萨斯仪器股份有限公司 | Memory cell employing reduced voltage |
| CN103544986A (en) * | 2013-10-09 | 2014-01-29 | 上海交通大学 | Design method of low-power-consumption 8-pipe SRAM (static random access memory) chip based on electric charge recycle and bit line classification |
| CN103915112A (en) * | 2013-01-02 | 2014-07-09 | 台湾积体电路制造股份有限公司 | Dual-Port SRAM Connection Structure |
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| CN102047339A (en) * | 2008-06-19 | 2011-05-04 | 德克萨斯仪器股份有限公司 | Memory cell employing reduced voltage |
| CN103915112A (en) * | 2013-01-02 | 2014-07-09 | 台湾积体电路制造股份有限公司 | Dual-Port SRAM Connection Structure |
| CN103544986A (en) * | 2013-10-09 | 2014-01-29 | 上海交通大学 | Design method of low-power-consumption 8-pipe SRAM (static random access memory) chip based on electric charge recycle and bit line classification |
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