CN105574295A - Method and device for acquiring state expression of JK trigger - Google Patents

Method and device for acquiring state expression of JK trigger Download PDF

Info

Publication number
CN105574295A
CN105574295A CN201610074394.4A CN201610074394A CN105574295A CN 105574295 A CN105574295 A CN 105574295A CN 201610074394 A CN201610074394 A CN 201610074394A CN 105574295 A CN105574295 A CN 105574295A
Authority
CN
China
Prior art keywords
state
pin
karnaugh map
expression formula
flip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610074394.4A
Other languages
Chinese (zh)
Inventor
石广
唐涛
王硕
刘海林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Inspur Beijing Electronic Information Industry Co Ltd
Original Assignee
Inspur Beijing Electronic Information Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inspur Beijing Electronic Information Industry Co Ltd filed Critical Inspur Beijing Electronic Information Industry Co Ltd
Priority to CN201610074394.4A priority Critical patent/CN105574295A/en
Publication of CN105574295A publication Critical patent/CN105574295A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Measuring Or Testing Involving Enzymes Or Micro-Organisms (AREA)

Abstract

The invention discloses a method and device for acquiring the state expression of a JK trigger. The method includes the steps that a next state karnaugh map of a pin to be resolved is acquired on a next state karnaugh map of a sequential logic circuit; the next state karnaugh map of the pin to be resolved is segmented into a first segment and a second segment, wherein the first segment is a next state karnaugh map corresponding to Qn=0, the second segment is a next state karnaugh map corresponding to Qn=1, Qn is the tab of the n<th> pin to be resolved, and n is a positive integer larger than or equal to 0. Thus, by means of the method, it is unnecessary to convert the state expression of the pin to be resolved, and efficiency is improved. The invention further discloses a device for acquiring the state expression of the JK trigger.

Description

A kind of method and device obtaining the state expression formula of JK flip-flop
Technical field
The present invention relates to electronic technology field, particularly relate to a kind of method and the device that obtain the state expression formula of JK flip-flop.
Background technology
The science and technology of current social constantly develops, the electronic product that people use also more and more high-tech, and in these electronic products sequential logical circuit application very extensive.There is an important step to be select the type of trigger in Design of Sequential Logic Circuit Based step, and then obtain the driving equation of circuit, state equation and output equation.And the characteristic equation of Different Logic function trigger is different, the state equation so finally write out according to state transition graph and selected state encoding is also different.As long as the state equation write out is consistent with the characteristic equation form of trigger, then can avoid because expression formula is out of shape some the unnecessary mistakes caused, and the determination of driving equation also can be more accurately simple.
At present method of the same race is all being adopted for the trigger selected, namely writing out the simplest flip-flop states equation according to the abbreviation principle of Next_State Karnaugh Map and Karnaugh map, thus the characteristic equation of the selected trigger of contrast obtains driving equation.If select JK flip-flop, often inconsistent with the form of trigger behavior equation according to the simplest state equation (state expression formula) that Next_State Karnaugh Map writes out, also state equation must be deformed into the canonical form of JK flip-flop characteristic equation by handy equation, this adds unnecessary trouble undoubtedly.
As can be seen here, how by Next_State Karnaugh Map expeditiously, the state expression formula obtaining JK flip-flop is easily those skilled in the art's problem demanding prompt solutions.
Summary of the invention
The object of this invention is to provide a kind of method and the device that obtain the state expression formula of JK flip-flop, for by Next_State Karnaugh Map expeditiously, obtain the state expression formula of JK flip-flop easily.
For solving the problems of the technologies described above, the invention provides a kind of method obtaining the state expression formula of JK flip-flop, comprising:
The Next_State Karnaugh Map of sequential logical circuit obtains the Next_State Karnaugh Map of pin to be solved;
First partitioning portion and the second partitioning portion are divided into the Next_State Karnaugh Map of described pin to be solved;
Wherein, described first partitioning portion is Q nthe Next_State Karnaugh Map of=0 correspondence, described second partitioning portion is and Q nthe Next_State Karnaugh Map of=1 correspondence; Q nbe the label of the n-th pin to be solved, n be more than or equal to 0 integer.
Preferably, also comprise:
The Next_State Karnaugh Map corresponding according to described first partitioning portion and Next_State Karnaugh Map corresponding to described second partitioning portion obtain the state expression formula of the n-th pin to be solved.
Preferably, also comprise:
The characteristic equation of JK flip-flop corresponding to described n-th pin to be solved is calculated according to the state expression formula of described n-th pin to be solved.
Preferably, the number of pin to be solved is 4.
Obtain a device for the state expression formula of JK flip-flop, comprising:
First acquiring unit, for obtaining the Next_State Karnaugh Map of pin to be solved on the Next_State Karnaugh Map of sequential logical circuit;
Cutting unit, for being divided into the first partitioning portion and the second partitioning portion to the Next_State Karnaugh Map of described pin to be solved;
Wherein, described first partitioning portion is Q nthe Next_State Karnaugh Map of=0 correspondence, described second partitioning portion is and Q nthe Next_State Karnaugh Map of=1 correspondence; Q nbe the label of the n-th pin to be solved, n be more than or equal to 0 positive integer.
Preferably, also comprise:
Second acquisition unit, for obtaining the state expression formula of the n-th pin to be solved according to Next_State Karnaugh Map corresponding to described first partitioning portion and Next_State Karnaugh Map corresponding to described second partitioning portion.
Preferably, also comprise:
Computing unit, for calculating the characteristic equation of JK flip-flop corresponding to described n-th pin to be solved according to the state expression formula of described n-th pin to be solved.
Preferably, the number of pin to be solved is 4.
The method of the state expression formula of acquisition JK flip-flop provided by the present invention and device, by being divided into the first partitioning portion and the second partitioning portion to the Next_State Karnaugh Map of pin to be solved, the Next_State Karnaugh Map after making according to segmentation directly just obtains the state expression formula corresponding with the form of the characteristic equation of JK flip-flop.As can be seen here, by said method, without the need to changing the state expression formula of pin to be solved, improve efficiency.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention, simple introduction is done below by the accompanying drawing used required in embodiment, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
A kind of process flow diagram obtaining the method for the state expression formula of JK flip-flop that Fig. 1 provides for embodiment one;
Fig. 2 is the Next_State Karnaugh Map of sequential logical circuit provided by the invention;
Fig. 3 is pin Q to be solved provided by the invention 3next_State Karnaugh Map;
Fig. 4 is pin Q to be solved provided by the invention 3segmentation after Next_State Karnaugh Map;
Fig. 5 is a kind of structural drawing obtaining the device of the state expression formula of JK flip-flop provided by the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiment.Based on the embodiment in the present invention, those of ordinary skill in the art are not making under creative work prerequisite, and the every other embodiment obtained, all belongs to scope.
Core of the present invention is to provide a kind of process flow diagram obtaining the method for the state expression formula of JK flip-flop.
In order to make those skilled in the art person understand the present invention program better, below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Embodiment one
A kind of process flow diagram obtaining the method for the state expression formula of JK flip-flop that Fig. 1 provides for embodiment one.Obtain the method for the state expression formula of JK flip-flop, comprising:
S10: the Next_State Karnaugh Map obtaining pin to be solved on the Next_State Karnaugh Map of sequential logical circuit;
S11: the first partitioning portion and the second partitioning portion are divided into the Next_State Karnaugh Map of pin to be solved;
Wherein, the first partitioning portion is Q nthe Next_State Karnaugh Map of=0 correspondence, the second partitioning portion is and Q nthe Next_State Karnaugh Map of=1 correspondence; Q nbe the label of the n-th pin to be solved, n be more than or equal to 0 integer.
In concrete enforcement, sequential logical circuit includes multiple pin, be designated as Q respectively 0, Q 1, Q 2... Q n.The Next_State Karnaugh Map of the sequential logical circuit obtained obtains the Next_State Karnaugh Map of some pins to be solved.In order to the method allowing those skilled in the art more understand the state expression formula of the acquisition JK flip-flop that the present embodiment provides.Illustrate with a concrete application scenarios below.Such as, if sequential logical circuit comprises 4 pins, Q is respectively 0, Q 1, Q 2, Q 3.Fig. 2 is the Next_State Karnaugh Map of sequential logical circuit provided by the invention.Fig. 3 is pin Q to be solved provided by the invention 3next_State Karnaugh Map.In step s 11, the first partitioning portion and the second partitioning portion are divided into the Next_State Karnaugh Map of pin to be solved, as shown in Figure 4.Fig. 4 is pin Q to be solved provided by the invention 3segmentation after Next_State Karnaugh Map.
As preferably, the Next_State Karnaugh Map corresponding according to the first partitioning portion and Next_State Karnaugh Map corresponding to the second partitioning portion obtain the state expression formula of the 3rd pin to be solved.
If when method is not conventionally split, the state expression formula of Q3 is:
Q 3 * = Q 2 Q 1 &OverBar; Q 0 + Q 3 Q 2 &OverBar;
Obviously in above formula, the state expression formula of Q3 is not corresponding with the form of JK flip-flop characteristic equation, needs further simplification just can obtain the state expression formula corresponding with JK flip-flop characteristic equation.
JK flip-flop characteristic equation is:
Q n + 1 = J Q n &OverBar; + K &OverBar; Q n
As shown in Figure 4, when adopting method provided by the invention to split, the state expression formula of Q3 is:
Q 3 * = Q 3 &OverBar; Q 2 Q 1 &OverBar; Q 0 + Q 3 Q 2 &OverBar;
Those skilled in the art are known, and this state expression formula is consistent with the characteristic equation form of JK flip-flop.
As preferably, calculate the characteristic equation of the 3rd JK flip-flop that pin to be solved is corresponding according to the state expression formula of the 3rd pin to be solved.
Contrast characteristic equation can be easy to obtain:
J 3 = Q 2 Q 1 &OverBar; Q 0 , K 3 = Q 2 .
Can be split the Next_State Karnaugh Map of other pins by above-mentioned method, just can obtain the state expression formula of the JK flip-flop of corresponding pin.
As preferably, the number of pin to be solved is 4.Understandably, the number of pin to be solved is not fixing, and the method that the change of the number of pin to be solved still can adopt the present invention to propose is split Next_State Karnaugh Map.
The method of the state expression formula of the acquisition JK flip-flop that the present embodiment provides, by being divided into the first partitioning portion and the second partitioning portion to the Next_State Karnaugh Map of pin to be solved, the Next_State Karnaugh Map after making according to segmentation directly just obtains the state expression formula corresponding with the form of the characteristic equation of JK flip-flop.As can be seen here, by said method, without the need to changing the state expression formula of pin to be solved, improve efficiency.
Embodiment two
Fig. 5 is a kind of structural drawing obtaining the device of the state expression formula of JK flip-flop provided by the invention.The device obtaining the state expression formula of JK flip-flop comprises:
First acquiring unit 10, for obtaining the Next_State Karnaugh Map of pin to be solved on the original Next_State Karnaugh Map of sequential logical circuit;
Cutting unit 11, for being divided into the first partitioning portion and the second partitioning portion to the Next_State Karnaugh Map of pin to be solved;
Wherein, the first partitioning portion is Q nthe Next_State Karnaugh Map of=0 correspondence, the second partitioning portion is and Q nthe Next_State Karnaugh Map of=1 correspondence; Q nbe the label of the n-th pin to be solved, n be more than or equal to 0 positive integer.
As preferred embodiment, also comprise:
Second acquisition unit, for obtaining the state expression formula of the n-th pin to be solved according to Next_State Karnaugh Map corresponding to the first partitioning portion and Next_State Karnaugh Map corresponding to the second partitioning portion.
As preferred embodiment, also comprise:
Computing unit, for calculating the characteristic equation of JK flip-flop corresponding to the n-th pin to be solved according to the state expression formula of the n-th pin to be solved.
As preferred embodiment, the number of pin to be solved is 4.
Due to the embodiment that embodiment two is device sections corresponding to the method implemented in embodiment one, therefore concrete embodiment refers to the description of embodiment one, and the present embodiment wouldn't repeat.
The device of the state expression formula of the acquisition JK flip-flop that the present embodiment provides, by being divided into the first partitioning portion and the second partitioning portion to the Next_State Karnaugh Map of pin to be solved, the Next_State Karnaugh Map after making according to segmentation directly just obtains the state expression formula corresponding with the form of the characteristic equation of JK flip-flop.As can be seen here, by said method, without the need to changing the state expression formula of pin to be solved, improve efficiency.
Above the method for the state expression formula of acquisition JK flip-flop provided by the present invention and device are described in detail.In instructions, each embodiment adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar portion mutually see.For device disclosed in embodiment, because it corresponds to the method disclosed in Example, so description is fairly simple, relevant part illustrates see method part.It should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention, can also carry out some improvement and modification to the present invention, these improve and modify and also fall in the protection domain of the claims in the present invention.
Professional can also recognize further, in conjunction with unit and the algorithm steps of each example of embodiment disclosed herein description, can realize with electronic hardware, computer software or the combination of the two, in order to the interchangeability of hardware and software is clearly described, generally describe composition and the step of each example in the above description according to function.These functions perform with hardware or software mode actually, depend on application-specific and the design constraint of technical scheme.Professional and technical personnel can use distinct methods to realize described function to each specifically should being used for, but this realization should not thought and exceeds scope of the present invention.
The software module that the method described in conjunction with embodiment disclosed herein or the step of algorithm can directly use hardware, processor to perform, or the combination of the two is implemented.Software module can be placed in the storage medium of other form any known in random access memory (RAM), internal memory, ROM (read-only memory) (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technical field.

Claims (8)

1. obtain a method for the state expression formula of JK flip-flop, it is characterized in that, comprising:
The Next_State Karnaugh Map of sequential logical circuit obtains the Next_State Karnaugh Map of pin to be solved;
First partitioning portion and the second partitioning portion are divided into the Next_State Karnaugh Map of described pin to be solved;
Wherein, described first partitioning portion is Q nthe Next_State Karnaugh Map of=0 correspondence, described second partitioning portion is and Q nthe Next_State Karnaugh Map of=1 correspondence; Q nbe the label of the n-th pin to be solved, n be more than or equal to 0 integer.
2. the method for the state expression formula of acquisition JK flip-flop according to claim 1, is characterized in that, also comprise:
The Next_State Karnaugh Map corresponding according to described first partitioning portion and Next_State Karnaugh Map corresponding to described second partitioning portion obtain the state expression formula of the n-th pin to be solved.
3. the method for the state expression formula of acquisition JK flip-flop according to claim 2, is characterized in that, also comprise:
The characteristic equation of JK flip-flop corresponding to described n-th pin to be solved is calculated according to the state expression formula of described n-th pin to be solved.
4. the method for the state expression formula of the acquisition JK flip-flop according to claims 1 to 3 any one, is characterized in that, the number of pin to be solved is 4.
5. obtain a device for the state expression formula of JK flip-flop, it is characterized in that, comprising:
First acquiring unit, for obtaining the Next_State Karnaugh Map of pin to be solved on the Next_State Karnaugh Map of sequential logical circuit;
Cutting unit, for being divided into the first partitioning portion and the second partitioning portion to the Next_State Karnaugh Map of described pin to be solved;
Wherein, described first partitioning portion is Q nthe Next_State Karnaugh Map of=0 correspondence, described second partitioning portion is and Q nthe Next_State Karnaugh Map of=1 correspondence; Q nbe the label of the n-th pin to be solved, n be more than or equal to 0 positive integer.
6. the device of the state expression formula of acquisition JK flip-flop according to claim 5, is characterized in that, also comprise:
Second acquisition unit, for obtaining the state expression formula of the n-th pin to be solved according to Next_State Karnaugh Map corresponding to described first partitioning portion and Next_State Karnaugh Map corresponding to described second partitioning portion.
7. the device of the state expression formula of acquisition JK flip-flop according to claim 6, is characterized in that, also comprise:
Computing unit, for calculating the characteristic equation of JK flip-flop corresponding to described n-th pin to be solved according to the state expression formula of described n-th pin to be solved.
8. the device of the state expression formula of the acquisition JK flip-flop according to claim 5 to 7 any one, is characterized in that, the number of pin to be solved is 4.
CN201610074394.4A 2016-02-02 2016-02-02 Method and device for acquiring state expression of JK trigger Pending CN105574295A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610074394.4A CN105574295A (en) 2016-02-02 2016-02-02 Method and device for acquiring state expression of JK trigger

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610074394.4A CN105574295A (en) 2016-02-02 2016-02-02 Method and device for acquiring state expression of JK trigger

Publications (1)

Publication Number Publication Date
CN105574295A true CN105574295A (en) 2016-05-11

Family

ID=55884425

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610074394.4A Pending CN105574295A (en) 2016-02-02 2016-02-02 Method and device for acquiring state expression of JK trigger

Country Status (1)

Country Link
CN (1) CN105574295A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108170911A (en) * 2017-12-16 2018-06-15 太原理工大学 Time sequence logic circuit state simplifying method based on Granule Computing
CN115630090A (en) * 2022-12-20 2023-01-20 宜科(天津)电子有限公司 Task state conversion system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104967442A (en) * 2015-07-27 2015-10-07 桂林电子科技大学 8421BCD code synchronization decimal addition/subtraction counter based on reversible logic

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104967442A (en) * 2015-07-27 2015-10-07 桂林电子科技大学 8421BCD code synchronization decimal addition/subtraction counter based on reversible logic

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
任骏原: "基于次态卡诺图的J、K激励函数最小化方法及时序逻辑电路自启动设计", 《浙江大学学报(理学版)》 *
倪树范: "次态卡诺图在时序逻辑电路分析和设计中的运用", 《绵阳师范高等专科学校学报》 *
卫永琴 等: "浅谈时序逻辑电路设计中的小技巧", 《科技视界》 *
吴恒玉 等: "次态卡诺图在时序逻辑电路中的应用", 《南京工业职业技术学院学报》 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108170911A (en) * 2017-12-16 2018-06-15 太原理工大学 Time sequence logic circuit state simplifying method based on Granule Computing
CN108170911B (en) * 2017-12-16 2020-06-02 太原理工大学 Sequential logic circuit state simplifying method based on particle calculation
CN115630090A (en) * 2022-12-20 2023-01-20 宜科(天津)电子有限公司 Task state conversion system
CN115630090B (en) * 2022-12-20 2023-04-04 宜科(天津)电子有限公司 Task state conversion system

Similar Documents

Publication Publication Date Title
US9305396B2 (en) Identifying features in polygonal meshes
US10831604B2 (en) Storage system management method, electronic device, storage system and computer program product
CN106775474A (en) A kind of Nand Flash abrasion equilibrium methods, device and memory
US9189578B1 (en) System, method, and computer program product for power supply network visualization
CN105574295A (en) Method and device for acquiring state expression of JK trigger
WO2022161368A1 (en) Method and apparatus for determining spatial two-tuple, computer device, and storage medium
CN106340246A (en) Display method and display device based on curved display screen as well as user equipment
US9483593B2 (en) Method for decomposing a hardware model and for accelerating formal verification of the hardware model
US9495504B2 (en) Using traces of original model to verify a modified model
CN106445477A (en) Method for extending user-defined model base based on object-oriented program architecture
CN103425558B (en) A kind of method realizing the test of board I/O port based on test configurations table
EP3430518B1 (en) Analysis of recurring processes
CN115239884A (en) Reconstruction method and device for medium-assembled three-dimensional model
Morita Computation in reversible cellular automata
CN103559266A (en) Multi-mode matching method and device
CN103927345B (en) A kind of nested method and device of JSP labels
US10733346B1 (en) Systems and methods for arc-based debugging in an electronic design
CN107623965A (en) Digital pulse width modulation method, digital pulse-width modulator and light adjusting system
CN105827248A (en) Adaptive frequency coding method and apparatus
US10318682B1 (en) Systems and methods for analyzing node impedance state
US10380312B1 (en) System, method, and computer program product for analyzing formal constraint conflicts
Devillers et al. Some Basic Techniques allowing Petri Net Synthesis: Complexity and Algorithmic Issues
CN103617330A (en) Piston mesh division structure
US9268898B1 (en) Estimating power consumption of a circuit design
CN108984060A (en) A kind of icon display method and terminal device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20160511