CN105553611A - Data package decoding system and method - Google Patents
Data package decoding system and method Download PDFInfo
- Publication number
- CN105553611A CN105553611A CN201510906840.9A CN201510906840A CN105553611A CN 105553611 A CN105553611 A CN 105553611A CN 201510906840 A CN201510906840 A CN 201510906840A CN 105553611 A CN105553611 A CN 105553611A
- Authority
- CN
- China
- Prior art keywords
- packet
- data
- pipeline
- signal bag
- control signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0036—Systems modifying transmission characteristics according to link quality, e.g. power backoff arrangements specific to the receiver
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
Abstract
The invention discloses a data package decoding system and method, and the system is used for decoding a data package. The system comprises a pipeline decoding module, a first storage module, and a second storage module. The pipeline decoding module enables multi-input channel data packages to be divided into a control signal package and a data signal package at the same time, and enables the control signal package to be stored in the first storage module, wherein the data signal package is stored in the second storage module. The method comprises the steps: separating the control signal package and the data signal package in the data package; respectively storing the control signal package and the data signal package, i.e., storing the control signal package in the first storage module, and storing the data signal package in the second storage module; respectively transmitting the control signal package and the data signal package, thereby improving the speed of data decoding. When a work clock of the pipeline decoding module is greater than or equal to 145.75MHz, the system and method can enable the data transmission speed of middle and low-end FPGA chips to reach 5830Mbps.
Description
Technical field
The present invention relates to electronic application field, especially a kind of decoded packet data system and method.
Background technology
MIPI (MobileIndustryProcessorInterface, mobile Industry Processor Interface) MPHY standard is the agreement communicated for Mobile solution proposed by MIPI alliance.Due to serial transmission, bandwidth is high, and it is widely used in the various mobile devices such as imageing sensor.Along with the continuous lifting of transmission rate (datarate), send and receive all in the face of acid test, especially for FPGA receiving terminal.
Uniform protocol (UniPro agreement) is wherein the bottom host-host protocol based on MPHY, and its transmission and reception are comparatively complicated, and transmission rate is higher.For receipt decoding, need to use the fpga chip of expensive two-forty to realize.
Summary of the invention
The object of the present invention is to provide a kind of decoded packet data system and method, make to utilize the fpga chip of low and middle-end just can reach the Signal transmissions of the flank speed (5830Mbps) of MPHY protocol definition.
In order to achieve the above object, the invention provides a kind of decoded packet data system and method, wherein, described decoded packet data system is used for decoding to packet, comprising: pipeline decoder module, the first memory module and the second memory module;
Multiple input path packet is separated into control signal bag and data-signal bag by described pipeline decoder module simultaneously, and is stored in described first memory module by described control signal bag, and described data-signal bag is stored in described second memory module.
Preferably, in above-mentioned decoded packet data system, described pipeline decoder module is provided with multistage parallel pipeline, described control signal bag is stored in described first memory module by afterbody pipeline, described data-signal bag is stored in described second memory module, and the packet of other every grade pipeline to certain area section marks.
Preferably, in above-mentioned decoded packet data system, when the mark result of fore line to the packet of current region section depends on the mark result of upper level pipeline to the packet of a upper area segments.
Preferably, in above-mentioned decoded packet data system, the form of described packet is marked, the corresponding mark value of each data packet format.
Preferably, in above-mentioned decoded packet data system, the figure place of described mark value is no less than 4.
Preferably, in above-mentioned decoded packet data system, when the form kind of described packet is less than or equal to 16, the figure place of described mark value is set to 4; When the form kind of described packet is greater than 16 and is less than or equal to 256, the figure place of described mark value is set to 8; When the form kind of described packet is greater than 256, the figure place of described mark value is set to 16.
Preferably, in above-mentioned decoded packet data system, the input channel number of described packet is L, then the progression M of parallel pipeline in described pipeline decoder module, and wherein M=n*L+1, L, M and n are natural number, and L >=2, n >=2.
Preferably, in above-mentioned decoded packet data system, the number of the described packet that described pipeline decoder module is decoded simultaneously is n*L, and wherein, n and L is natural number, and L >=2, n >=2.
Preferably, in above-mentioned decoded packet data system, the first order parallel pipeline of described pipeline decoder module marks first packet, second level parallel pipeline marks second packet, so repeats, until the n-th * L level parallel pipeline marks a n-th * L packet, wherein, n and L is natural number, and L >=2, n >=2.
Present invention also offers and a kind ofly utilize decoded packet data system as above to carry out the method for decoding, packet comprises: control signal bag and data-signal bag, control signal bag and data-signal bag are separated by pipeline decoder module from packet described in multiple input path, and described control signal bag is stored in described first memory module, described data-signal bag is stored in described second memory module.
In decoded packet data system and method provided by the invention, control signal bag in packet and data-signal bag are separated, store respectively, be stored in described first memory module by described control signal bag, described data-signal bag is stored in described second memory module, and then send respectively, improve the speed of data decode.When the work clock of described pipeline decoder module is more than or equal to 145.75MHz, the message transmission rate on low and middle-end fpga chip can be made to reach 5830Mbps.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of decoded packet data system in the embodiment of the present invention;
The data while that Fig. 2 being 4 channel data bags in the embodiment of the present invention in decode procedure and mark structure schematic diagram;
Fig. 3 be in the embodiment of the present invention pipeline decoder module to 4 channel data bags simultaneously decoding process figure;
In figure: 101-pipeline decoder module; 102-first memory module; 103-second memory module.
Embodiment
Below in conjunction with schematic diagram, the specific embodiment of the present invention is described in more detail.According to following description and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Embodiments provide a kind of decoded packet data system and method, wherein, as shown in Figure 1, described decoded packet data system comprises: pipeline decoder module 101, first memory module 102 and the second memory module 103; Multiple input path packet is separated into control signal bag and data-signal bag by described pipeline decoder module 101 simultaneously, and described control signal bag to be stored in described first memory module 102, and described data-signal bag is stored in described second memory module 103.
Concrete, described pipeline decoder module 101 is a kind of Pipeline (pipeline walks abreast) structures comprising mark, namely multistage parallel pipeline is provided with, the input channel number of described packet is L, then the progression M of parallel pipeline in described pipeline decoder module 101, and the number of the described packet that described pipeline decoder module 101 is decoded simultaneously is n*L, wherein M=n*L+1, L, M and n are natural number, and L >=2, n >=2.
Described control signal bag is stored in described first memory module 102 by the afterbody pipeline of described pipeline decoder module 01, described data-signal bag is stored in described second memory module 103, and the packet of other every grade pipeline to certain area section marks.When the mark result of fore line to the packet of current region section depends on the mark result of upper level pipeline to the packet of a upper area segments.
Concrete, first order parallel pipeline marks first packet, and second level parallel pipeline marks second packet, so repeats, until the n-th * L level parallel pipeline marks a n-th * L packet, M level, namely described control signal bag is stored in described first memory module by (n*L+1) level parallel pipeline, and described data-signal bag is stored in described second memory module, wherein, L, M and n are natural number, and L >=2, n >=2.
In the present embodiment, described packet is the packet based on MIPIUniPro agreement, and based on described MIPIUniPro agreement, the input channel of described packet is provided with 4, i.e. L=4.In the present embodiment, in order to alleviate the requirement of FPGA to clock frequency, two divided-frequency process has been carried out to each input channel, make corresponding two packets of each input channel, i.e. n=2 in the present embodiment, make the clock frequency of each input channel reduce half, be more conducive to the reception realizing data on low and middle-end FPGA.
Certainly, in other embodiments of the invention, the value of n is not limited to equal 2, other process can also be carried out to each input channel, make the corresponding more packet of each input channel, such as, each input channel corresponding 3,4 or more packet, that is, n=3, n=4 or other values is made, to be more conducive to the reception realizing data on low and middle-end FPGA.
As n=2, the progression of the parallel pipeline arranged in described pipeline decoder module is M=n*L+1=2*4+1=9.Namely the number of described packet that described pipeline decoder module is decoded simultaneously is n*L, namely 8.Described pipeline decoder module will to this 8 data pack buffers 8 times, a clock consuming time at every turn, 8 clocks consuming time altogether, then the packet successively from the packet of lowest order to highest order, each clock process packet, and current according to when wrapping in present clock process, need to consider the mark result of previous clock to previous packet.
Concrete, first order parallel pipeline in described pipeline decoder module is used for marking first packet, second level parallel pipeline is used for marking second packet, but in the process marked second packet, needs the mark result of consideration first packet.Repetition like this, until mark to the 8th grade of parallel pipeline the 8th packet, then at the 9th grade of parallel pipeline, also be the 9th clock simultaneously, mark result according to eight packets stores respectively, be stored in described first memory module by the packet with control signal class mark, the packet with data line signal class mark is stored in described second memory module.
In the process marked described packet, the corresponding mark value of each data packet format, the figure place of described mark value is no less than 4.Concrete, when the form kind of described packet is less than or equal to 16, the figure place of described mark value is set to 4; When the form kind of described packet is greater than 16 and is less than or equal to 256, the figure place of described mark value is set to 8; When the form kind of described packet is greater than 256, the figure place of described mark value is set to 16.
In the present embodiment, the form based on the packet of described MIPIUniPro agreement has 16 kinds, and therefore, the figure place of described mark value is set to 16.
The embodiment of the present invention additionally provides a kind of concrete methods of realizing of described decoded packet data system.Connect example, still for the packet based on described MIPIUniPro agreement.
The a part of data packet format in described MIPIUniPro agreement is listed in table 1.
| Mark value | Data packet format | Mark value | Data packet format |
| 0 | FILLER | 8 | AFC1 |
| 1 | DL_DATA1 | 9 | AFC2 |
| 2 | DL_DATA2 | 10 | COF |
| 3 | SOF1 | 11 | CRC |
| 4 | SOF2 | 12 | PACP1 |
| 5 | EOF1 | 13 | PA_DATA1 |
| 6 | EOF2 | 14 | PACP2 |
| 7 | NAC | 15 | PA_DATA2 |
Table 1
Wherein, data packet format mark value is the packet of 1-6 is data-signal bag, and data packet format mark value is the packet of 8-10 and 12-15 is control signal bag.CRC packet is the verification bag to data-signal bag and control signal bag, and after verification completes, this CRC bag will be dropped.
In described MIPIUniPro agreement, each packet is made up of 17 bits, in the present embodiment, can simultaneously to 4 passages totally 8 packets decode simultaneously, that is, can simultaneously to the decoding data of 136.In the process that each packet is marked, by the mark value of 4, it is marked, that is, all have the data of 4 to indicate the data format of this packet to each packet, as shown in Figure 2.
Described pipeline decoder module will to this 136 8 data pack buffers 8 times, a clock consuming time at every turn, 8 clocks consuming time altogether, then the packet successively from the packet of lowest order to highest order, each clock process packet, and current according to when wrapping in present clock process, need to consider the mark result of previous clock to previous packet.
Concrete, as shown in Figure 3, first clock, unwrap from first data decoding of beginning, namely from [16:0] in Fig. 3, the first order parallel pipeline of described pipeline decoder module unwraps to first data decoding of beginning, if decoded result is SOF, then update mark value [3:0] is 3, and binary system is 0011, and the form of corresponding packet is SOF1.
At second clock, second level parallel pipeline is decoded to the second packet, i.e. decoded data [33:17] part, [3:0] part of first judge mark value is SOF1, if now decoded data [33:17] part is data format, be DATA form, then update mark value [7:4] part is 1, binary system is 0001, and corresponding data packet format is DL_DATA1.If now decoded data [33:17] part is PACP, namely second packet is control signal bag, update mark value [7:4] part is needed to be 12, corresponding data packet format is PACP1, if the 3rd packet decoded result is a packet, then [7:4] part of first judge mark value is PACP1, then [11:8] part of update mark value is PA_DATA1.Repetition like this, until to the 8th clock, the 8th grade of parallel pipeline marks the 8th packet.
Composition graphs 3, at the 9th clock, in the 9th grade of parallel pipeline, 136 all bit data and all decoded and mark, combine the packet in 136 bit data with same tag attribute according to different mark value, store respectively.Concrete, be that the packet of 1-6 is stored in described second memory module by mark value, mark value is that the packet of 8-10 and 12-15 is stored in described first memory module.Thus achieve being separated of data-signal bag and control signal bag, then export respectively.As the work clock >=145.75MHz of described pipeline decoder module, message transmission rate on low and middle-end fpga chip can be made also to reach 5830Mbps.
In Fig. 3, Data, Data_1d, Data_2d, Data_3d, Data_4d, Data_5d, Data_6d, Data_7d and Data_8d represent nine grades of parallel pipelines of described pipeline decoder module.
To sum up, in the decoded packet data system and method that the embodiment of the present invention provides, control signal bag in packet and data-signal bag are separated, store respectively, be stored in described first memory module by described control signal bag, described data-signal bag is stored in described second memory module, and then sends respectively, improves the speed of data decode.As the work clock >=145.75MHz of described pipeline decoder module, the message transmission rate on low and middle-end fpga chip can be made to reach 5830Mbps.
Above are only the preferred embodiments of the present invention, any restriction is not played to the present invention.Any person of ordinary skill in the field; in the scope not departing from technical scheme of the present invention; the technical scheme disclose the present invention and technology contents make the variations such as any type of equivalent replacement or amendment; all belong to the content not departing from technical scheme of the present invention, still belong within protection scope of the present invention.
Claims (10)
1. a decoded packet data system, for decoding to packet, is characterized in that, comprising: pipeline decoder module, the first memory module and the second memory module; Multiple input path packet is separated into control signal bag and data-signal bag by described pipeline decoder module simultaneously, and is stored in described first memory module by described control signal bag, and described data-signal bag is stored in described second memory module.
2. decoded packet data system as claimed in claim 1, it is characterized in that, described pipeline decoder module is provided with multistage parallel pipeline, described control signal bag is stored in described first memory module by afterbody pipeline, described data-signal bag is stored in described second memory module, and the packet of other every grade pipeline to certain area section marks.
3. decoded packet data system as claimed in claim 2, is characterized in that, when the mark result of fore line to the packet of current region section depends on the mark result of upper level pipeline to the packet of a upper area segments.
4. decoded packet data system as claimed in claim 2 or claim 3, is characterized in that, mark the form of described packet, the corresponding mark value of each data packet format.
5. decoded packet data system as claimed in claim 4, it is characterized in that, the figure place of described mark value is no less than 4.
6. decoded packet data system as claimed in claim 5, it is characterized in that, when the form kind of described packet is less than or equal to 16, the figure place of described mark value is set to 4; When the form kind of described packet is greater than 16 and is less than or equal to 256, the figure place of described mark value is set to 8; When the form kind of described packet is greater than 256, the figure place of described mark value is set to 16.
7. decoded packet data system as claimed in claim 2, it is characterized in that, the input channel number of described packet is L, then the progression M of parallel pipeline in described pipeline decoder module, and wherein M=n*L+1, L, M and n are natural number, and L >=2, n >=2.
8. decoded packet data system as claimed in claim 7, it is characterized in that, the number of the described packet that described pipeline decoder module is decoded simultaneously is n*L, and wherein, n and L is natural number, and L >=2, n >=2.
9. decoded packet data system as claimed in claim 8, it is characterized in that, the first order parallel pipeline of described pipeline decoder module marks first packet, second level parallel pipeline marks second packet, so repeats, until the n-th * L level parallel pipeline marks a n-th * L packet, wherein, n and L is natural number, and L >=2, n >=2.
10. one kind utilizes as decoded packet data system as described in any one in claim 1-9 carries out the method for decoding, it is characterized in that, packet comprises: control signal bag and data-signal bag, control signal bag and data-signal bag are separated by pipeline decoder module from packet described in multiple input path, and described control signal bag is stored in described first memory module, described data-signal bag is stored in described second memory module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510906840.9A CN105553611B (en) | 2015-12-09 | 2015-12-09 | Decoded packet data system and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510906840.9A CN105553611B (en) | 2015-12-09 | 2015-12-09 | Decoded packet data system and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105553611A true CN105553611A (en) | 2016-05-04 |
| CN105553611B CN105553611B (en) | 2018-12-11 |
Family
ID=55832564
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510906840.9A Active CN105553611B (en) | 2015-12-09 | 2015-12-09 | Decoded packet data system and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105553611B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006115151A1 (en) * | 2005-04-25 | 2006-11-02 | Sharp Kabushiki Kaisha | Recording device, reproducing device, recording/reproducing device, recording program, recording medium for such recording program, reproducing program, and recording medium for such reproducing program |
| CN101252415A (en) * | 2008-04-18 | 2008-08-27 | 中国人民解放军信息工程大学 | Complete package data transmission method and transmission system |
| CN102223683A (en) * | 2011-06-07 | 2011-10-19 | 中兴通讯股份有限公司 | Data transmission method, node and system in wireless sensor network |
| CN103077192A (en) * | 2012-12-24 | 2013-05-01 | 中标软件有限公司 | Data processing method and system thereof |
| CN103346949A (en) * | 2013-07-25 | 2013-10-09 | 北京大学 | Unpacking and packing method and system based on embedded two-channel network data package |
-
2015
- 2015-12-09 CN CN201510906840.9A patent/CN105553611B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006115151A1 (en) * | 2005-04-25 | 2006-11-02 | Sharp Kabushiki Kaisha | Recording device, reproducing device, recording/reproducing device, recording program, recording medium for such recording program, reproducing program, and recording medium for such reproducing program |
| CN101252415A (en) * | 2008-04-18 | 2008-08-27 | 中国人民解放军信息工程大学 | Complete package data transmission method and transmission system |
| CN102223683A (en) * | 2011-06-07 | 2011-10-19 | 中兴通讯股份有限公司 | Data transmission method, node and system in wireless sensor network |
| CN103077192A (en) * | 2012-12-24 | 2013-05-01 | 中标软件有限公司 | Data processing method and system thereof |
| CN103346949A (en) * | 2013-07-25 | 2013-10-09 | 北京大学 | Unpacking and packing method and system based on embedded two-channel network data package |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105553611B (en) | 2018-12-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101702639B (en) | Check value calculation method and device of cyclic redundancy check | |
| CN104426629A (en) | Physical layer coding and decoding methods and devices | |
| CN108306895A (en) | Data transmission method and device | |
| WO2011071310A3 (en) | Method for transmitting control information in a carrier aggregation system, receiving method, and terminal | |
| KR20150017648A (en) | Method and system of transmitting and receiving fragmentable data units in a wireless communication environment | |
| CN106464581A (en) | Data transmission method and system and data receiving device | |
| CN102801626B (en) | Satellite-borne data management method and device based on AOS standard | |
| US20200007155A1 (en) | Efficient data encoding | |
| CN105847101A (en) | Data transmission method based on vehicle bus | |
| CN102594492A (en) | Code block dividing method and device | |
| CN104917590B (en) | A kind of channel coding error correction method | |
| CN104467865B (en) | Serial communication protocol controller, byte split circuit and 8b10b encoders | |
| CN105827361B (en) | A kind of FEC method based on media content | |
| CN105279123A (en) | Serial port conversion structure and method of dual-redundancy 1553B bus | |
| CN104144035B (en) | Serial communication controlling circuit | |
| CN105553611A (en) | Data package decoding system and method | |
| CN104243083A (en) | Data mapping method, device and electronic equipment thereof | |
| WO2020156580A1 (en) | Transmission block transmission method and apparatus, communication device and storage medium | |
| US9337959B2 (en) | Defect propagation of multiple signals of various rates when mapped into a combined signal | |
| CN104853447A (en) | Method and device for processing data information | |
| CN106603193A (en) | Media content-based FEC mechanism | |
| CN107748728A (en) | A kind of serial communication distributor and its means of communication | |
| CN102780626B (en) | A kind of data forwarding method, device and the network equipment | |
| US8527677B1 (en) | Serial communications links with bonded first-in-first-out buffer circuitry | |
| CN105471527A (en) | Wireless communication method capable of realizing crossing-standard communication |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |