CN105552113A - Radiation sensitive field effect transistor and preparation method thereof - Google Patents
Radiation sensitive field effect transistor and preparation method thereof Download PDFInfo
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- CN105552113A CN105552113A CN201610111860.1A CN201610111860A CN105552113A CN 105552113 A CN105552113 A CN 105552113A CN 201610111860 A CN201610111860 A CN 201610111860A CN 105552113 A CN105552113 A CN 105552113A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 23
- 230000005855 radiation Effects 0.000 title abstract description 22
- 238000002353 field-effect transistor method Methods 0.000 title description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 62
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 30
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 27
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910021389 graphene Inorganic materials 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 230000005669 field effect Effects 0.000 claims abstract description 15
- 239000000463 material Substances 0.000 claims abstract description 13
- 238000005468 ion implantation Methods 0.000 claims abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 238000002955 isolation Methods 0.000 claims description 10
- 239000000126 substance Substances 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 8
- 238000012545 processing Methods 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 238000001035 drying Methods 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 3
- -1 boron ion Chemical class 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- 239000004411 aluminium Substances 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- JYMITAMFTJDTAE-UHFFFAOYSA-N aluminum zinc oxygen(2-) Chemical compound [O-2].[Al+3].[Zn+2] JYMITAMFTJDTAE-UHFFFAOYSA-N 0.000 claims description 2
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims 1
- 239000002245 particle Substances 0.000 abstract description 7
- 238000005516 engineering process Methods 0.000 abstract description 6
- 230000035945 sensitivity Effects 0.000 abstract description 6
- 238000001514 detection method Methods 0.000 abstract description 5
- 230000008569 process Effects 0.000 abstract description 5
- 230000003139 buffering effect Effects 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 238000009736 wetting Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 7
- 238000013461 design Methods 0.000 description 4
- 238000011160 research Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- VJJVVKGSBWRFNP-UHFFFAOYSA-N [O].[Si](=O)=O Chemical compound [O].[Si](=O)=O VJJVVKGSBWRFNP-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 208000033999 Device damage Diseases 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 231100000987 absorbed dose Toxicity 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005670 electromagnetic radiation Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1606—Graphene
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
The invention discloses a radiation sensitive field effect transistor (RadFET) on a silicon substrate and a preparation method thereof. The insulation channel layers of the device sequentially include a silicon dioxide layer prepared by a wetting method, graphene film and a silicon dioxide layer prepared by a dry method. The multiple layers of grapheme material are used as the channel layers, thus the sensitivity of a RadFET detector is increased; the loose silicon dioxide layer prepared by the wet method plays a role in buffering, thus damage to the device caused by high-energy particle radiation can be effectively relieved, meanwhile the interface problem caused by direct contact of the graphene film and source and drain electrodes is avoided, and the service life and performance of the device are enhanced. In addition, the silicon dioxide layer prepared by the dry method is subjected to the ion implantation technology, high-concentration impurity traps are introduced, the threshold voltage of the device can be effectively adjusted, source and drain contact resistances can be reduced at the same time, and the sensitivity of the device can be increased. The RadFET detector is simple in process, low in preparation cost, applicable to detection on total radiation dose, and wide in application prospect.
Description
Technical field
The invention belongs to field of manufacturing semiconductor devices, be specifically related to design and the preparation method of the radiosensitive field-effect transistor (RadFET) on a kind of silicon substrate.
Background technology
RadFET detector is mainly used in the measurement of space radiation accumulated dose, can estimate spacecraft electronic devices and components, influence degree that material and facility is subject to space radiation.Due to one of factor that total radiation dosage is electronic component failure, the monitoring of space radiation accumulated dose can provide engineering data for the design of satellite long-life.There is complicated radiation environment in space, mainly comprises particle radiation and electromagnetic radiation.The safety etc. of these space radiations to aircraft material, electronic device, equipment and aircrew constitutes serious threat, therefore develop advanced radiation detector and correlation detection technology, research space environment to the impact of spacecraft and spacefarer, become one of important content of aerospace engineering safety guarantee.In addition, in non-space field, RadFET detector can also be applied to the detection (as radiating medical, radiation experiments, integrated circuit fabrication process line and various big-and-middle-sized detecting devicess etc.) of various terrestrial surface radiation metering.
The operation principle of radiation detector, based on the interaction between particle and material, is mainly used to observe the microphenomenon of radiation and particle and study.RadFET detector can be obtained according to the principle of MOSFET to the gate oxide charge sensitive of device.In RadFET detector, thick grating oxide layer excites, ionizes under the effect of ray, produces electron-hole pair.Electronics is overflowed from grid under electric field action, hole is then fixed to Oxide trapped charge, thus changes the threshold voltage of MOSFET, and passes through relevant reading circuit and amplify, the output voltage signal obtained is consistent with the absorbed dose of region, detects radiation source.
Different according to from the interactional material of high energy particle, can be divided into gas detector, scintillation detector, semiconductor detector and other detectors by common radiation detector.By contrast, semiconductor RadFET detector have be convenient to integrated, volume is little, the advantage such as lightweight, low in energy consumption, is a kind ofly desirable to penetrate radiation dose detector, can be widely used in the fields such as Aero-Space detection, nuclear industry protection and medical radiation.
At present, about the preparation research of RadFET detector and the exploration of its irradiation model are deepening continuously, such as the factor such as oxidated layer thickness, technique is to the research of detector sensitivity, and adjusting thresholds injects the research etc. to detector performance.The excellent specific property of grapheme material makes it relatively be applicable to being applied to RadFET detector, and is in the infancy based on the correlative study of the RadFET detector of Graphene.
Summary of the invention
The object of the present invention is to provide a kind of preparation method of radiosensitive field-effect transistor (RadFET), be intended to the performance improving RadFET detector.
Technical scheme of the present invention is:
Based on a field-effect transistor for graphene film material, comprise substrate, gate electrode, gate medium, channel layer and source-drain electrode.Wherein, substrate is monocrystalline silicon, substrate forms gate electrode, gate electrode forms gate dielectric layer, gate dielectric layer is formed isolation trench channel layer, insulated trenches layer material is by loose silicon dioxide layer, the semiconductor graphene film layer (raising sensitivity) of wet-layer preparation, and on graphene film, dry process one deck compact silicon dioxide layer is formed, and forms source electrode and drain electrode respectively at the two ends of channel layer.
The preparation method of radiosensitive field-effect transistor of the present invention comprises the following steps:
1) grow layer of conductive film on a silicon substrate, chemical wet etching forms gate electrode;
2) photoetching gate dielectric layer and channel layer pattern, continuous dry process preparation growth gate dielectric layer, loose silicon dioxide layer in isolation trench channel layer adopts wet processing preparation, cover graphene film layer, dry process one deck compact silicon dioxide layer on graphene film, by ion implantation, top layer silicon dioxide is adulterated subsequently, obtain channel layer;
3) grow layer of conductive film, chemical wet etching forms source electrode and drain electrode;
4) grow one deck passivation dielectric layer, chemical wet etching forms the fairlead of gate electrode, source electrode and drain electrode;
5) grow layer of metal film, chemical wet etching forms metal electrode and interconnection.
Wherein:
In step 1) in, gate electrode adopts the electric conducting material such as metallic aluminium Al or Titanium Ti;
In step 2) in, the material of gate dielectric layer is the insulating material such as silicon dioxide; Isolation trench channel layer silicon dioxide is obtained by wet process oxidation technology, and its structure is the silicon dioxide layer comparatively loosened.
In step 2) in, use and have the graphene film of high connductivity characteristic of semiconductor, thickness is individual layer or 2 ~ 4 layers, and the silicon oxide layer that graphene film covers is obtained by dry oxidation.Select phosphorus or boron ion to carry out ion implantation, form the silica of N or P type doping;
In step 3) in, the conductive film of source electrode and drain electrode adopts the transparent conductive material such as tin indium oxide ITO or zinc oxide aluminum AZO.
The design parameter of radiosensitive field-effect transistor is: the breadth length ratio (W/L) of device is at 300/15 ~ 700/100 (micron); Channel layer thickness in 200 ~ 800 nanometers, wherein: the loose silicon dioxide layer of wet-layer preparation is in 150 ~ 700 nanometers.
Beneficial effect of the present invention:
The invention provides design of the radiosensitive field-effect transistor (RadFET) on a kind of silicon substrate and preparation method thereof, adopt the channel layer of single or multiple lift grapheme material as device of high connductivity characteristic of semiconductor, enhance RadFET detector sensitivity, loose silicon oxide layer under graphene film layer plays cushioning effect, effectively can slow down the device damage that High energy particles Radiation brings, avoid graphene film simultaneously and directly contact with electrode the interface problem brought, improve life-span and the performance of device.In addition, ion implantation technology is carried out to the silica in channel layer, introduce the particle trap of higher concentration, can the threshold voltage of effective adjusting device, reduce source-drain contact resistance, enhance device sensitivity simultaneously.This RadFET detector technique is simple, preparation cost is low, is applicable to the detection of total radiation dose, is with a wide range of applications.
Accompanying drawing explanation
Fig. 1 is the profile of the radiosensitive field-effect transistor of the present invention (RadFET);
Fig. 2 is the vertical view of the radiosensitive field-effect transistor of the present invention (RadFET);
Fig. 3 (a) ~ (g) sequentially show the preparation method of the radiosensitive field-effect transistor of the present invention (RadFET) and the main technological steps of this device embodiment.Wherein, (a) structural representation that is silicon substrate; B () is for forming the processing step of gate electrode; C () is for forming the processing step of gate dielectric layer and channel layer ground floor; D () is for preparing the processing step of Graphene transfer in channel layer; E () is the processing step of channel layer the superiors silicon dioxide layer; F () is ion implantation process step for preparing channel layer; G () is for forming the processing step of source electrode and drain electrode.
Embodiment
Below in conjunction with accompanying drawing, by specific embodiment, set forth the present invention further.
As depicted in figs. 1 and 2, field-effect transistor of the present invention comprises: the wet oxygen silicon dioxide layer 4 in substrate 1, gate electrode 2, gate dielectric layer 3, isolation trench channel layer, graphene film 5, dry oxygen silicon dioxide layer 6, source-drain electrode 7.Wherein, form gate electrode 2 on substrate 1, gate electrode 2 is formed gate dielectric layer 3, and gate dielectric layer 3 is formed isolation trench channel layer 4,5,6, and the two ends on channel layer 6 form source-drain electrode 7. respectively
An embodiment of field transistor preparation method of the present invention, by shown in Fig. 3 (a) to (g), comprises the following steps:
1) adopt monocrystalline silicon as device substrate 1, as shown in Fig. 3 (a), adopt dc sputtering processes to grow the metal Ti of one deck 10 ~ 150 nanometer thickness on substrate 1, then etch gate electrode 2, as shown in Fig. 3 (b);
2) use dry method-wet oxidation to form the silicon dioxide layer of 100 ~ 500 nanometer thickness, obtain the ground floor 4 of gate dielectric layer 3 and isolation trench channel layer.Photoetching process is used to obtain gate oxide and channel layer pattern, as shown in Fig. 3 (c); Wherein after dry method growth silicon dioxide 50 nanometer, direct wet method growth silica 1 50 ~ 700 nanometer.
3) by the individual layer of high connductivity semiconductor for preparing or 2 ~ 4 layer graphene film transfer to isolation trench channel layer 4, as shown in Fig. 3 (d) 4.
4) carry out isolation trench channel layer 6 silicon dioxide growth, adopt dry method growth silicon dioxide 50 nanometer, as shown in Fig. 3 (e) 6;
5) by ion implantation to step 4) in the top layer silicon dioxide of gained carry out boron ion doping.As shown in Fig. 3 (f);
6) adopt magnetron sputtering technique to grow one deck ITO conductive film, its thickness is 20 ~ 200 nanometers, and photoetching, etching form source electrode and drain electrode 7, as shown in Fig. 3 (g);
7) grow one deck silicon nitride passivation dielectric layer according to standard technology, photoetching, etching form the fairlead of gate electrode, source electrode and drain electrode;
8) grow layer of metal Al or transparent conductive film, photoetching, etching form electrode and interconnection.
It is finally noted that the object publicizing and implementing example is to help to understand the present invention further, but it will be appreciated by those skilled in the art that: without departing from the spirit and scope of the invention and the appended claims, various substitutions and modifications are all possible.Therefore, the present invention should not be limited to the content disclosed in embodiment, and the scope that the scope of protection of present invention defines with claims is as the criterion.
Claims (8)
1. the field-effect transistor based on graphene film material, comprise substrate, gate electrode, gate medium, channel layer and source-drain electrode, wherein, substrate is monocrystalline silicon, and substrate forms gate electrode, and gate electrode forms gate dielectric layer, gate dielectric layer is formed isolation trench channel layer, form source electrode and drain electrode respectively at the two ends of channel layer, it is characterized in that, described isolation trench channel layer is followed successively by: the silicon dioxide layer of the silicon dioxide layer of wet-layer preparation, graphene film and dry process.
2. field-effect transistor as claimed in claim 1, it is characterized in that, described graphene film is individual layer or 2 ~ 4 layer graphene materials.
3. field-effect transistor as claimed in claim 1, is characterized in that, described insulated trenches layer thickness in 200 ~ 800 nanometers, wherein: the silicon dioxide layer of wet-layer preparation is in 150 ~ 700 nanometers.
4. the preparation method of field-effect transistor as claimed in claim 1, comprises the following steps:
1) grow layer of conductive film on a silicon substrate, chemical wet etching forms gate electrode;
2) photoetching gate dielectric layer and channel layer pattern, continuous growth gate dielectric layer, wet processing prepares silicon dioxide layer, cover graphene film layer subsequently, on graphene film, dry method grows one deck compact silicon dioxide, by ion implantation, top layer silicon dioxide is adulterated subsequently, obtain channel layer;
3) grow layer of conductive film, chemical wet etching forms source electrode and drain electrode;
4) grow one deck passivation dielectric layer, chemical wet etching forms the fairlead of gate electrode, source electrode and drain electrode;
5) grow layer of metal film, chemical wet etching forms metal electrode and interconnection.
5. preparation method as claimed in claim 4, is characterized in that, step 1) in, gate electrode adopts metallic aluminium Al or Titanium Ti.
6. preparation method as claimed in claim 4, is characterized in that, step 2) in, gate dielectric layer is silicon dioxide insulator material prepared by dry process.
7. preparation method as claimed in claim 4, is characterized in that, in step 2) in, select phosphorus or boron ion to carry out ion implantation, form the silicon dioxide of N or P type doping.
8. preparation method as claimed in claim 4, is characterized in that, in step 3) in, the conductive film of source electrode and drain electrode adopts tin indium oxide ITO or zinc oxide aluminum AZO transparent conductive material.
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| CN108615786A (en) * | 2018-05-30 | 2018-10-02 | 上海大学 | Radiosensitive field-effect transistor of cadmium-zinc-teiluride and preparation method thereof |
| CN109196320A (en) * | 2016-05-30 | 2019-01-11 | 多次元能源系统研究集团 | High sensor and its manufacturing method with the transparent conductive film with crack |
| CN110911521A (en) * | 2019-11-22 | 2020-03-24 | 西安交通大学 | Multi-band graphene detector with multilayer coupling structure and preparation process thereof |
| CN111142146A (en) * | 2019-12-26 | 2020-05-12 | 兰州空间技术物理研究所 | Portable radiation dosimeter |
| CN113410135A (en) * | 2021-06-15 | 2021-09-17 | 西安微电子技术研究所 | Method for manufacturing anti-radiation junction field effect transistor |
| CN114864708A (en) * | 2022-05-06 | 2022-08-05 | 北京交通大学 | Multi-grid graphene field effect transistor type photoelectric sensor and preparation method thereof |
| CN115188825A (en) * | 2022-07-04 | 2022-10-14 | 弘大芯源(深圳)半导体有限公司 | Method for manufacturing radiation-resistant metal oxide semiconductor field effect device and manufacturing method thereof |
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| CN109196320A (en) * | 2016-05-30 | 2019-01-11 | 多次元能源系统研究集团 | High sensor and its manufacturing method with the transparent conductive film with crack |
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| CN114864708A (en) * | 2022-05-06 | 2022-08-05 | 北京交通大学 | Multi-grid graphene field effect transistor type photoelectric sensor and preparation method thereof |
| CN115188825A (en) * | 2022-07-04 | 2022-10-14 | 弘大芯源(深圳)半导体有限公司 | Method for manufacturing radiation-resistant metal oxide semiconductor field effect device and manufacturing method thereof |
| CN115188825B (en) * | 2022-07-04 | 2024-01-30 | 弘大芯源(深圳)半导体有限公司 | Method for manufacturing radiation-resistant metal oxide semiconductor field effect device |
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