CN105550443A - SystemC based unified stainer array TLM model with accurate cycle - Google Patents
SystemC based unified stainer array TLM model with accurate cycle Download PDFInfo
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Abstract
The invention relates to a SystemC based unified stainer array TLM model with an accurate cycle. According to the model, a plurality of physically and logically independent dyeing treatment units are integrated in a unified stainer array; and the unified stainer array can be modeled only by modeling one dyeing treatment unit by adopting a SystemC language and then instantiating a model for five times.
Description
Technical field
The present invention relates to computer hardware modeling technique field, particularly relate to a kind of unified stainer array TLM model based on SystemC Cycle accurate.
Background technology
For software/hardware coordinate design and the co-verification (Co-verification) of system, analog rate is extremely important.The classic method speed being modeled as basis with Method at Register Transfer Level (RTL) is slow, and the system model needed for only could obtaining at the later stage of design process.In order to raise the efficiency, the simulation of effective hardware/software system must be enabled at the commitment of design process.In order to overcome the limitation in RTL modeling, two methods can be adopted: (1) is in the abstraction level modeling higher than RTL.(2) use the different abstraction level of language SystemC modeling that general, comprise Method at Register Transfer Level.The transaction-level of SystemC2.0 is the abstraction level higher than RTL, can set up the executable specification of hardware fast, fast creation system model in this rank according to the Elementary Function specification of system.Analog rate high in this rank allows to develop in advance the application software relevant with verifying hardware.By adding sequential details in transaction-level model (Trans-actionLevelModels, TLMs), can the performance of evaluating system, the structure of searching system.The module essence of SystemC also promotes multiplexing between system of developed component.
SystemC is a kind of Modeling Platform based on C++ that OSCI (OpenSystemCInitiative) organizes to set up and safeguards, it is write with C Plus Plus completely, form by through well-designed C++ class storehouse and simulation kernel, support the modeling and simulation of hardware on gate leve, RTL, each abstraction hierarchy such as system-level, and be open source code.SystemC support hardware/software co-design, can describe the structure of the complication system be made up of hardware and software, is supported in the description to hardware, software and interface under C++ environment.Can abstract on various system-level level of practical function module, communication module, software module and hardware module with SystemC, the data type of its port introduced and signal describes, the concept of clock and time delay, just based on will unified for the description of the software and hardware thought to a kind of modeling language.The accurate model of software algorithm, the architecture of hardware, the interface of SoC and system-level design fast and effeciently can be set up with SystemC, and design is emulated, verify and optimizes (use SystemC modeling, its simulation velocity is generally 10 ~ 100 times with VHDL or Verilog modeling).The most basic structural unit of SystemC is module (module), and module can comprise other modules or process (process) and method (method), process as the function in C language in order to realize a certain behavior.Module, by interface (port) and other module communications, is connected with signal (Signal) between interface.A complete system is made up of multiple module, and each module comprises one or more process and method, and process is multiple operation, is communicated between them by signal.Clock Clock is a kind of special signal when emulating in order to Control timing sequence and makes course synchronization.Method for designing based on SystemC supports deviser's modeling in different levels, reduces size of code and workload, provides higher work efficiency, that is utilize SystemC can more efficiently to emulate rapidly compared with traditional method.But do not find the modeling method of the unified stainer array based on SystemC Cycle accurate at present yet.
Summary of the invention
The present invention is the above-mentioned technical matters solving background technology existence, and a kind of unified stainer array TLM model based on SystemC Cycle accurate is provided, SystemC language only need be adopted to carry out modeling to 1 dyeing processing unit, then by Model instantiation 5 times, the modeling to unified dyeing array can just be completed.
Technical solution of the present invention is: the present invention is a kind of unified stainer array TLM model based on SystemC Cycle accurate, and its special character is: the dyeing processing unit that the inner integrated multiple physics of described unified stainer array, logic are separate.
Above-mentioned dyeing processing unit comprises ControlStatusRegister module, Fetch module, Decode module, Issue module, Execute module, LoadStore module, WriteBack module, Scoreboard module, RegisterFile module, ConstantCache module, LocalSram module, ShareSram module and InstructionCache module; Described Fetch module is connected with Decode module with CSR, InstructionCache by transaction interface; Described Decode module is connected with Scoreborad module with Fetch, Issue by transaction interface; Described Issue module is connected with Scoreboard module with Decode, Execute, LoadStore by transaction-level interface; Described Execute module is connected with Issue with WriteBack module by transaction-level interface; Described LoadStore module is connected with Scoreboard module with Issue, WriteBack, ConstantCache, LocalSram, ShareSram by transaction-level interface; Described WriteBack module is connected with RegisterFile module with Execute, LoadStore by transaction-level interface; Described Scoreboard module is connected with LoadStore module with Decode, Issue by transaction-level interface.
The state of above-mentioned Fetch module in charge monitoring CSR module, instruction fetch from InstructionCache module, then passes to Decode unit by the instruction of taking-up.
Above-mentioned Decode module in charge carries out decoding to instruction, command information is inserted Scoreboard module simultaneously.
Above-mentioned Issue module is according to the command status of launching, performing recorded in Scoreboard, decide current instruction whether to be launched, after decision instruction can be launched, read operand relevant in RegisterFile, by 2 instruction issues to Execute or LoadStore module, the command information write Scoreboard module then will be launched.
Above-mentioned Execute module, according to the instruction of launching, performs relevant arithmetic, logical operation, then operation result is passed to WriteBack module.
Above-mentioned LoadStore module, according to the instruction of launching, performs Load instruction or Store instruction.Scoreboard update instruction state is notified after executing load, store instruction.
What above-mentioned WriteBack module received Execute module or LoadStore module writes back data, is write the relevant position of RegisterFile.
The all states performing instruction of above-mentioned Scoreboard module record, are convenient to Issue module according to status information to determine whether launch next instruction.
Above-mentioned dyeing processing unit is 5.
Unified stainer array TLM model based on SystemC Cycle accurate provided by the invention, adopts SystemC language and TLM modeling method, unified dyeing array is carried out to the modeling of Cycle accurate.In TLM modeling method, be that the function by transaction-level interface instead of the connection by hardware signal realize communicating between modules.Modules inside all contains the process of respective independent, executed in parallel, and each process only has a common event to trigger---rising edge clock; Each process can call the function in the transaction-level interface of respective module, carrys out mutual transmission of information.
Accompanying drawing explanation
Fig. 1 is the basic structure block diagram of transaction-level SystemC Cycle accurate modeling in the present invention;
Fig. 2 is the structured flowchart of unified dyeing array in the present invention;
Fig. 3 is the transaction-level structured flowchart of processing unit of dyeing in the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, technical scheme of the present invention is stated clearly and completely.Obviously; the embodiment stated is only the present invention's part embodiment, instead of whole embodiments, based on the embodiment in the present invention; the every other embodiment that those skilled in the art are not making creative work prerequisite and obtain, all belongs to protection scope of the present invention.
See Fig. 1, the basic structure of transaction-level SystemC modeling comprises TLM interface, transaction initiator (Initiator) and affairs by dynamic person (Target).The TLM interface initiator_target_tlm_if described in figure is an empty class containing reading and writing function, and the function of its inner docking port operation is declared, and does not relate to the concrete definition of any data, behavior.Affairs Initiator inside defines two interface A and B, has declared an inner loop process initiator_process ().The type of interface A, B is all sc_port<initiator_target_tlm_ifGreatT.GreaT .GT, internal process initiator_process belongs to the SC_CTHREAD type of a SystemC, this process has independent stack when running software, and exists in the whole life cycle of program.When this procedural sequences performs wait () statement, process is hung up; After clock.pos () in the responsive list only stated in advance in this process triggers, this process just can continue order and perform downwards.
Affairs Target inherits initiator_target_tlm_if interface class, and its inside defines two interface a and b, and it is all sc_export<initiator_target_tlm_ifGreatT.Gre aT.GT type.Affairs Target declares the behavior of function therein in specific implementation initiator_target_tlm_if interface class.
See Fig. 2, in the specific embodiment of the invention, the transaction-level structure of unified stainer permutation contains the separate dyeing processing unit of 5 physics, logic.
See Fig. 3, the modeling mechanism of dyeing processing unit of the present invention is based on content shown in Fig. 1.Dyeing processing unit is made up of ControlStatusRegister module, Fetch module, Decode module, Issue module, Execute module, LoadStore module, WriteBack module, Scoreboard module, RegisterFile module, ConstantCache module, LocalSram module, ShareSram module and InstructionCache module.
State the state of Fetch module in charge monitoring CSR module, instruction fetch from InstructionCache module, then passes to Decode unit by the instruction of taking-up.Wherein Fetch module is connected with Decode module with CSR, InstructionCache by transaction interface;
Decode module in charge carries out decoding to instruction, command information is inserted Scoreboard module simultaneously.Wherein Decode module is connected with Scoreborad module with Fetch, Issue by transaction interface;
Whether Issue module, according to the command status of launching, performing recorded in Scoreboard, decides current instruction and is launched.After decision instruction can be launched, read operand relevant in RegisterFile, by 2 instruction issues to Execute or LoadStore module, the command information write Scoreboard module then will be launched.Wherein Issue module is connected with Scoreboard module with Decode, Execute, LoadStore by transaction-level interface.
Execute module, according to the instruction of launching, performs relevant arithmetic, logical operation, then operation result is passed to WriteBack module.Wherein Execute module is connected with Issue with WriteBack module by transaction-level interface;
LoadStore module, according to the instruction of launching, performs Load instruction or Store instruction.Scoreboard update instruction state is notified after executing load, store instruction.Wherein LoadStore module is connected with Scoreboard module with Issue, WriteBack, ConstantCache, LocalSram, ShareSram by transaction-level interface;
What WriteBack module received Execute module or LoadStore module writes back data, is write the relevant position of RegisterFile.Wherein WriteBack module is connected with RegisterFile module with Execute, LoadStore by transaction-level interface;
The all states performing instruction of Scoreboard module record, are convenient to Issue module according to status information to determine whether launch next instruction.Wherein Scoreboard module is connected with LoadStore module with Decode, Issue by transaction-level interface;
Finally it should be noted that above embodiment only in order to technical scheme of the present invention to be described, be not intended to limit; Although with reference to previous embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that; It still can be modified to the technical scheme that foregoing embodiments is recorded, or carries out equivalent replacement to wherein portion of techniques feature; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (10)
1. based on a unified stainer array TLM model for SystemC Cycle accurate, it is characterized in that: the dyeing processing unit that the inner integrated multiple physics of described unified stainer array, logic are separate.
2., according to the unified stainer array TLM model based on SystemC Cycle accurate described in claim 1, it is characterized in that: described dyeing processing unit comprises ControlStatusRegister module, Fetch module, Decode module, Issue module, Execute module, LoadStore module, WriteBack module, Scoreboard module, RegisterFile module, ConstantCache module, LocalSram module, ShareSram module and InstructionCache module; Described Fetch module is connected with Decode module with CSR, InstructionCache by transaction interface; Described Decode module is connected with Scoreborad module with Fetch, Issue by transaction interface; Described Issue module is connected with Scoreboard module with Decode, Execute, LoadStore by transaction-level interface; Described Execute module is connected with Issue with WriteBack module by transaction-level interface; Described LoadStore module is connected with Scoreboard module with Issue, WriteBack, ConstantCache, LocalSram, ShareSram by transaction-level interface; Described WriteBack module is connected with RegisterFile module with Execute, LoadStore by transaction-level interface; Described Scoreboard module is connected with LoadStore module with Decode, Issue by transaction-level interface.
3. the unified stainer array TLM model based on SystemC Cycle accurate according to claim 2, it is characterized in that: the state of described Fetch module in charge monitoring CSR module, instruction fetch from InstructionCache module, then passes to Decode unit by the instruction of taking-up.
4. the unified stainer array TLM model based on SystemC Cycle accurate according to claim 3, is characterized in that: described Decode module in charge carries out decoding to instruction, command information is inserted Scoreboard module simultaneously.
5. the unified stainer array TLM model based on SystemC Cycle accurate according to claim 4, it is characterized in that: described Issue module is according to the command status of launching, performing recorded in Scoreboard, decide current instruction whether to be launched, after decision instruction can be launched, read operand relevant in RegisterFile, by 2 instruction issues to Execute or LoadStore module, the command information write Scoreboard module then will be launched.
6. the unified stainer array TLM model based on SystemC Cycle accurate according to claim 5, it is characterized in that: described Execute module is according to the instruction of launching, perform relevant arithmetic, logical operation, then operation result is passed to WriteBack module.
7. the unified stainer array TLM model based on SystemC Cycle accurate according to claim 6, it is characterized in that: described LoadStore module is according to the instruction of launching, perform Load instruction or Store instruction, after executing load, store instruction, notify Scoreboard update instruction state.
8. the unified stainer array TLM model based on SystemC Cycle accurate according to claim 7, it is characterized in that: what described WriteBack module received Execute module or LoadStore module writes back data, is write the relevant position of RegisterFile.
9. the unified stainer array TLM model based on SystemC Cycle accurate according to claim 8, it is characterized in that: all states performing instruction of described Scoreboard module record, be convenient to Issue module according to status information to determine whether launch next instruction.
10. the unified stainer array TLM model based on SystemC Cycle accurate according to the arbitrary claim of claim 1 to 9, is characterized in that: described dyeing processing unit is 5.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106683158A (en) * | 2016-12-12 | 2017-05-17 | 中国航空工业集团公司西安航空计算技术研究所 | Modeling structure of GPU texture mapping non-blocking memory Cache |
| CN106708473A (en) * | 2016-12-12 | 2017-05-24 | 中国航空工业集团公司西安航空计算技术研究所 | Uniform stainer array multi-warp instruction fetching circuit and method |
| CN108133452A (en) * | 2017-12-06 | 2018-06-08 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of instruction issue processing circuit of unified stainer array |
| CN109346028A (en) * | 2018-11-14 | 2019-02-15 | 西安翔腾微电子科技有限公司 | A kind of triangle rasterization Scan Architecture based on TLM |
| CN109599135A (en) * | 2018-11-14 | 2019-04-09 | 西安翔腾微电子科技有限公司 | TLM model, storage method, storage system and the storage medium of the frame buffer zone GPU |
| CN109634583A (en) * | 2018-11-14 | 2019-04-16 | 西安翔腾微电子科技有限公司 | A kind of the hardware TLM model and realization structure of the GPU color storage Cache module based on SystemC |
| CN111026528A (en) * | 2019-11-18 | 2020-04-17 | 中国航空工业集团公司西安航空计算技术研究所 | High-performance large-scale dyeing array program scheduling and distributing system |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101388109A (en) * | 2008-01-25 | 2009-03-18 | 威盛电子股份有限公司 | Drawing processing system, quick fetching system and data processing method |
| CN102648449A (en) * | 2009-09-29 | 2012-08-22 | 辉达公司 | Trap handler architecture for a parallel processing unit |
| CN103198505A (en) * | 2013-04-23 | 2013-07-10 | 四三九九网络股份有限公司 | GPU (graphic processing unit)-based method for game character rendering and character redressing and device thereof |
| CN104503950A (en) * | 2014-12-09 | 2015-04-08 | 中国航空工业集团公司第六三一研究所 | OpenGL (open graphic library) API (application program interface)-oriented graphic processor |
| CN103246770B (en) * | 2013-05-08 | 2015-10-14 | 南京大学 | A kind of system action emulation mode of based upon activities graph model |
-
2015
- 2015-12-11 CN CN201510926303.0A patent/CN105550443B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101388109A (en) * | 2008-01-25 | 2009-03-18 | 威盛电子股份有限公司 | Drawing processing system, quick fetching system and data processing method |
| CN102648449A (en) * | 2009-09-29 | 2012-08-22 | 辉达公司 | Trap handler architecture for a parallel processing unit |
| CN103198505A (en) * | 2013-04-23 | 2013-07-10 | 四三九九网络股份有限公司 | GPU (graphic processing unit)-based method for game character rendering and character redressing and device thereof |
| CN103246770B (en) * | 2013-05-08 | 2015-10-14 | 南京大学 | A kind of system action emulation mode of based upon activities graph model |
| CN104503950A (en) * | 2014-12-09 | 2015-04-08 | 中国航空工业集团公司第六三一研究所 | OpenGL (open graphic library) API (application program interface)-oriented graphic processor |
Non-Patent Citations (1)
| Title |
|---|
| 常轶松: "面积带宽优化的嵌入式 GPU 可编程着色器体系结构研究", 《中国博士学位论文全文数据库 工程信息辑》 * |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106683158A (en) * | 2016-12-12 | 2017-05-17 | 中国航空工业集团公司西安航空计算技术研究所 | Modeling structure of GPU texture mapping non-blocking memory Cache |
| CN106708473A (en) * | 2016-12-12 | 2017-05-24 | 中国航空工业集团公司西安航空计算技术研究所 | Uniform stainer array multi-warp instruction fetching circuit and method |
| CN106708473B (en) * | 2016-12-12 | 2019-05-21 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of unified more warp fetching circuits of stainer array |
| CN106683158B (en) * | 2016-12-12 | 2020-06-09 | 中国航空工业集团公司西安航空计算技术研究所 | Modeling system of GPU texture mapping non-blocking storage Cache |
| CN108133452A (en) * | 2017-12-06 | 2018-06-08 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of instruction issue processing circuit of unified stainer array |
| CN108133452B (en) * | 2017-12-06 | 2021-06-01 | 中国航空工业集团公司西安航空计算技术研究所 | Instruction transmitting and processing circuit of unified stainer array |
| CN109346028A (en) * | 2018-11-14 | 2019-02-15 | 西安翔腾微电子科技有限公司 | A kind of triangle rasterization Scan Architecture based on TLM |
| CN109599135A (en) * | 2018-11-14 | 2019-04-09 | 西安翔腾微电子科技有限公司 | TLM model, storage method, storage system and the storage medium of the frame buffer zone GPU |
| CN109634583A (en) * | 2018-11-14 | 2019-04-16 | 西安翔腾微电子科技有限公司 | A kind of the hardware TLM model and realization structure of the GPU color storage Cache module based on SystemC |
| CN109599135B (en) * | 2018-11-14 | 2021-02-09 | 西安翔腾微电子科技有限公司 | GPU frame buffer area storage hardware, storage method, storage system and storage medium |
| CN111026528A (en) * | 2019-11-18 | 2020-04-17 | 中国航空工业集团公司西安航空计算技术研究所 | High-performance large-scale dyeing array program scheduling and distributing system |
| CN111026528B (en) * | 2019-11-18 | 2023-06-30 | 中国航空工业集团公司西安航空计算技术研究所 | High-performance large-scale dyeing array program scheduling distribution system |
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