CN105529332B - A kind of codec type vertical gate 3D NAND and forming method thereof - Google Patents
A kind of codec type vertical gate 3D NAND and forming method thereof Download PDFInfo
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- CN105529332B CN105529332B CN201610018226.3A CN201610018226A CN105529332B CN 105529332 B CN105529332 B CN 105529332B CN 201610018226 A CN201610018226 A CN 201610018226A CN 105529332 B CN105529332 B CN 105529332B
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 32
- 239000000463 material Substances 0.000 claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 claims abstract description 17
- 239000007772 electrode material Substances 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 7
- 230000008021 deposition Effects 0.000 claims abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 70
- 239000000377 silicon dioxide Substances 0.000 claims description 35
- 238000000926 separation method Methods 0.000 claims description 31
- 230000000903 blocking effect Effects 0.000 claims description 15
- 235000012239 silicon dioxide Nutrition 0.000 claims description 15
- 229910010092 LiAlO2 Inorganic materials 0.000 claims description 6
- 229910010936 LiGaO2 Inorganic materials 0.000 claims description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 6
- 229910052593 corundum Inorganic materials 0.000 claims description 6
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 claims description 6
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 230000008901 benefit Effects 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 description 5
- 229910003465 moissanite Inorganic materials 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 241000790917 Dioxys <bee> Species 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
Abstract
The invention discloses a kind of codec type vertical gate 3D NAND and forming method thereof, and the method comprising the steps of: providing substrate；One or more layers semiconductor layer is formed in substrate；One or more layers semiconductor layer is etched to form multiple grooves；Gate structure is formed on the top in multiple grooves and across multiple grooves；Polysilicon layer is formed across the top of multiple grooves；Multiple grid materials are etched to gate structure and fill hole, hole is filled to polysilicon layer etching source material；Deposition of electrode material in hole and multiple grid materials filling hole is filled in source electrode material.The present invention has the advantage that having vertical direction more better than BICS structure to expand potentiality, influence of the increase of the number of plies for the performance of single storage tube is much smaller compared to the three-dimensional storage of vertical-channel, and this structure is also easier in technique, reduce the step of zanjon etches this complicated and time consumption, entire technique and current technology are completely compatible.
Description
Technical field
The present invention relates to semiconductor fields, and in particular to a kind of codec type vertical gate 3D NAND and forming method thereof.
Background technique
With the diminution of process, the cost that the storage density based on planar structure improves is also higher and higher, then produces
Three-dimensional storage organization is given birth to.BiCS (Bit Cost Scalable) structure is the very extensive 3D flash knot of existing research
Structure, the storage unit that the storage density of BiCS structure compares planar structure has large increase, but space utilization rate is still insufficient.
Summary of the invention
The present invention is directed at least solve one of above-mentioned technical problem.
For this purpose, an object of the present invention is to provide a kind of codec type vertical gate 3D NAND forming methods.
Two purposes of the invention are to propose a kind of codec type vertical gate 3D NAND.
To achieve the goals above, embodiment of the invention discloses a kind of codec type vertical gate 3D NAND forming method,
The following steps are included: providing substrate；The first separation layer is formed in the substrate；One is formed on first separation layer
Layer or multi-lager semiconductor layer；One or more layers described semiconductor layer is etched to form multiple grooves, the multiple groove extends to
The top surface of first separation layer；Silica tunnel layer is formed to the deposit silica of the multiple groove；Institute
State deposit silicon nitride electric charge capture layer and silicon dioxide blocking layer on silica tunnel layer；It is in the multiple groove and horizontal
Gate structure is formed on the silicon dioxide blocking layer at the top across the multiple groove；Across the top of the multiple groove
Polysilicon layer is formed on the silicon dioxide blocking layer in portion；Multiple grid materials are etched to the gate structure and fill hole,
The multiple grid material filling hole extends to the top surface of first separation layer, to the polysilicon layer etching source material
Material filling hole, source electrode material filling hole hole extend to the top surface of first separation layer；It is filled out in the source electrode material
Fill deposition of electrode material in hole and the multiple grid material filling hole.
Codec type vertical gate 3D NAND forming method according to an embodiment of the present invention has and preferably erects than BICS structure
For histogram to potentiality are expanded, influence of the increase of the number of plies for the performance of single storage tube is small compared to the three-dimensional storage of vertical-channel
Much, and it is also easier in technique, reduce the step of zanjon etches this complicated and time consumption, entire technique and current work
Skill technology is completely compatible.
In addition, codec type vertical gate 3D NAND forming method according to the above embodiment of the present invention, can also have as follows
Additional technical characteristic:
Further, the substrate has patterned surface.
Further, the substrate is Si, SiGe, SiC, GaAs, Ge, GaN, GaP, InP, Ga2O3、Al2O3、AlN、
ZnO、LiGaO2、LiAlO2One of.
Further, further comprising the steps of: heavy doping is carried out to the specified region of one or more layers semiconductor layer.
To achieve the goals above, embodiment of the invention discloses a kind of codec type vertical gate 3D NAND, comprising: lining
Bottom；It is formed in the first separation layer of the substrate；It is formed in one or more layers semiconductor layer on first separation layer,
Wherein, multiple grooves are provided in one or more layers described semiconductor layer, the multiple groove extends to first separation layer
Top surface, multiple holes are etched on one or more layers described semiconductor layer, the multiple hole extends to first isolation
The top surface of layer；The silica tunnel layer being formed on the multiple groove；It is formed in the silica tunnel layer
On silicon dioxide blocking layer；Multiple gate structures, the multiple gate structure are separately positioned in the multiple groove, are horizontal
In multiple holes on top and one or more layers described semiconductor layer across the multiple groove；Polysilicon layer, the polysilicon
Layer across the multiple groove top and be formed on silicon dioxide blocking layer, source is set on the polysilicon layer.
Codec type vertical gate 3D NAND according to an embodiment of the present invention, codec type vertical gate 3D NAND are to be totally different from
There is three bit memories of the vertical gate structure of BiCS structure better vertical direction to expand potentiality, and the increase of the number of plies is for list
The influence of the performance of a storage tube is much smaller compared to the three-dimensional storage of vertical-channel, and this structure is also simpler in technique
Just, reduce the step of zanjon etches this complicated and time consumption, entire technique and current technology are completely compatible.
In addition, codec type vertical gate 3D NAND according to the above embodiment of the present invention, can also have following additional skill
Art feature:
Further, the substrate has patterned surface.
Further, the substrate is Si, SiGe, SiC, GaAs, Ge, GaN, GaP, InP, Ga2O3、Al2O3、AlN、
ZnO、LiGaO2、LiAlO2One of.
Further, heavily doped region is provided on one or more layers described semiconductor layer.
Additional aspect and advantage of the invention will be set forth in part in the description, and will partially become from the following description
Obviously, or practice through the invention is recognized.
Detailed description of the invention
Above-mentioned and/or additional aspect of the invention and advantage will become from the description of the embodiment in conjunction with the following figures
Obviously and it is readily appreciated that, in which:
Fig. 1-8 is the forming process schematic diagram of the codec type vertical gate 3D NAND forming method of one embodiment of the invention；
Fig. 9 is the structural schematic diagram of the codec type vertical gate 3D NAND of one embodiment of the invention.
Specific embodiment
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, and for explaining only the invention, and is not considered as limiting the invention.
In the description of the present invention, it is to be understood that, term " center ", " longitudinal direction ", " transverse direction ", "upper", "lower",
The orientation or positional relationship of the instructions such as "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outside" is
It is based on the orientation or positional relationship shown in the drawings, is merely for convenience of description of the present invention and simplification of the description, rather than instruction or dark
Show that signified device or element must have a particular orientation, be constructed and operated in a specific orientation, therefore should not be understood as pair
Limitation of the invention.In addition, term " first ", " second " are used for description purposes only, it is not understood to indicate or imply opposite
Importance.
In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or be integrally connected；It can
To be mechanical connection, it is also possible to be electrically connected；It can be directly connected, can also can be indirectly connected through an intermediary
Connection inside two elements.For the ordinary skill in the art, above-mentioned term can be understood at this with concrete condition
Concrete meaning in invention.
Referring to following description and drawings, it will be clear that these and other aspects of the embodiment of the present invention.In these descriptions
In attached drawing, some particular implementations in the embodiment of the present invention are specifically disclosed, to indicate to implement implementation of the invention
Some modes of the principle of example, but it is to be understood that the scope of embodiments of the invention is not limited.On the contrary, of the invention
Embodiment includes all changes, modification and the equivalent fallen within the scope of the spirit and intension of attached claims.
Codec type vertical gate 3D NAND forming method according to an embodiment of the present invention is described below in conjunction with attached drawing.
Fig. 1-7 is the forming process schematic diagram of the codec type vertical gate 3D NAND forming method of one embodiment of the invention.
Please refer to Fig. 1-7, a kind of codec type vertical gate 3D NAND forming method the following steps are included:
S1: as shown in Figure 1, providing substrate 100.Specifically, substrate 100 can be the substrate with patterned surface, such as
Si with patterned structures or the Sapphire Substrate with patterned structures (PSS), this patterned structures advantageously reduce
Dislocation density in epitaxial layer, be also beneficial to LED goes out light.Substrate 100 can be Si, SiGe, SiC, Al2O3、AlN、ZnO、
Ga2O3、LiGaO2Or LiAlO2One of.Preferably, substrate 100 is Si, and Si substrate is cheap and easy to get, is easy to adulterate, while easily
Heterogeneous separation layer is generated in reacting.
S2: as shown in Fig. 2, forming the first separation layer 200 on substrate 100.Specifically, the first separation layer 200 is two
Silica material, effect are to realize the electric isolation of one layer of conductive layer on silicon substrate and the first separation layer 200.
S3: as shown in figure 3, forming one or more layers semiconductor layer on the first separation layer 200.At of the invention one
In example, four-level semiconductor layer 301/302/303/304 and four layers of separation layer 401/402/403/ are formed on the first separation layer
404。
Optionally, heavy doping is carried out in the specified region of four-level semiconductor layer 301/302/303/304, heavily doped region is
For making the substrate of depletion type MOS tube, without heavy doping, then the metal-oxide-semiconductor formed is enhanced metal-oxide-semiconductor.
S4: as shown in figure 4, etching one or more layers semiconductor layer to form multiple grooves, multiple grooves extend to first
The top surface of separation layer 200.
S5: silica tunnel layer is formed to the deposit silica of multiple grooves.Specifically, silica conduct is deposited
The gate medium of metal-oxide-semiconductor, in the region for forming storage tube, appropriate etching is that silica is thinning, the dioxy as SONOS storage tube
SiClx tunnel layer；Or in the region suitable control thickness for forming storage tube, the dioxy of formation when depositing silica
SiClx is than the relatively thin silica tunnel layer as SONOS storage tube.
S6: deposit silicon nitride electric charge capture layer and silicon dioxide blocking layer on silica tunnel layer form charge
Capture composite layer.
S7: as shown in figure 5, being formed in multiple grooves and on the silicon dioxide blocking layer at the top of multiple grooves
Gate structure 501/502.
S8: make as shown in fig. 6, forming polysilicon layer 600 on the silicon dioxide blocking layer at the top of multiple grooves
For source line, or when four-level semiconductor layer 301/302/303/304 retain partial region as depositing polysilicon conduct
Source line.
S9: as shown in fig. 7, etching multiple grid materials to gate structure 501/502 fills hole 5011/5021, multiple grid
Pole material filling hole 5011/5021 extends to the top surface of the first separation layer 200.To 600 etching source material of polysilicon layer
Hole 601 is filled, source electrode material filling hole hole 601 extends to the top surface of the first separation layer 200.To four-level semiconductor layer 301/
302/303/304 and four layers of separation layer 401/402/403/404 also etch deep hole 4041, increase space efficiency utilization.
S10: it is deposited as shown in figure 8, being filled in hole 5011/5021 and multiple grid materials filling hole 601 in source electrode material
Electrode material 5012/5022/602 is completed to be electrically connected.
The codec type vertical gate 3D NAND forming method of the embodiment of the present invention has vertical side preferably than BICS structure
To potentiality are expanded, influence of the increase of the number of plies for the performance of single storage tube is small compared to the three-dimensional storage of vertical-channel to be obtained
It is more and also easier in technique, reduce the step of zanjon etches this complicated and time consumption, entire technique and current technique
The completely compatible effect of technology.
Below with reference to Detailed description of the invention codec type vertical gate 3D NAND of the invention.
Referring to FIG. 9, a kind of codec type vertical gate 3D NAND, comprising: substrate 100, be formed on substrate 100
One separation layer 200 and it is formed in one or more layers semiconductor layer 301/302/303/304 on the first separation layer 200.Wherein, one
Multiple grooves are provided in layer or multi-lager semiconductor layer 301/302/303/304, multiple grooves extend to the top of the first separation layer
Portion surface.Be etched with multiple holes 401 on one or more layers semiconductor layer 301/302/303/304, multiple holes extend to first every
The top surface of absciss layer 200.Codec type vertical gate 3D NAND further includes the silica tunnelling being formed on multiple grooves
Layer, the silicon dioxide blocking layer and multiple gate structures 4042/5012/5022, polycrystalline being formed on silica tunnel layer
Silicon layer 600.Wherein, multiple gate structures 4042/5012/5022 are separately positioned in multiple grooves, across the top of multiple grooves
In multiple holes 4041 in portion and one or more layers semiconductor layer.Polysilicon layer 600 across multiple grooves top and be formed in
On silicon dioxide blocking layer.Source 6012 is set on polysilicon layer 600.
In one embodiment of the invention, substrate 100 has the substrate of patterned surface.
In one embodiment of the invention, substrate Si, SiGe, SiC, GaAs, Ge, GaN, GaP, InP, Ga2O3、
Al2O3、AlN、ZnO、LiGaO2、LiAlO2One of.Preferably silicon substrate.
In one embodiment of the invention, it is provided on one or more layers semiconductor layer 301/302/303/304 heavily doped
Miscellaneous region.
In order to clearly illustrate the beneficial effect of codec type vertical gate 3D NAND of the invention, will be carried out by below table
Explanation.
| Grid voltage | 0 | 0 | 0 | 0 | State |
| First layer | ON | OFF | ON | OFF | off |
| The second layer | OFF | ON | ON | OFF | off |
| Third layer | ON | OFF | OFF | ON | off |
| 4th layer | OFF | ON | OFF | ON | off |
The conducting situation of each layer under voltage status is not added in the grid that table 1 represents selection layer
| Grid voltage | 0 | 1 | 0 | 1 | State |
| First layer | ON | ON | ON | ON | on |
| The second layer | OFF | ON | ON | ON | off |
| Third layer | ON | ON | OFF | ON | off |
| 4th layer | OFF | ON | OFF | ON | off |
Table 2 indicates that first layer is connected under this pressurized conditions
| Grid voltage | 1 | 0 | 0 | 1 | State |
| First layer | ON | OFF | ON | ON | off |
| The second layer | ON | ON | ON | ON | on |
| Third layer | ON | OFF | OFF | ON | off |
| 4th layer | ON | ON | OFF | ON | off |
Table 3 indicates that the second layer is connected under this pressurized conditions
| Grid voltage | 0 | 1 | 1 | 0 | State |
| First layer | ON | ON | ON | OFF | off |
| The second layer | OFF | ON | ON | OFF | off |
| Third layer | ON | ON | ON | ON | on |
| 4th layer | OFF | ON | ON | ON | off |
Table 4 indicates that third layer is connected under this pressurized conditions
| Grid voltage | 1 | 0 | 1 | 0 | State |
| First layer | ON | OFF | ON | OFF | off |
| The second layer | ON | ON | ON | OFF | off |
| Third layer | ON | OFF | ON | ON | off |
| 4th layer | ON | ON | ON | ON | on |
Table 5 indicates the 4th layer of conducting under this pressurized conditions
By upper table 1-5 it is found that selecting the voltage of tube grid by control decoding, the selection to a certain layer is realized.Position end
Selecting pipe is the 3D NAND string in order to distinguish inner side and outer side.When the number of plies changes, appropriate adjustment also can guarantee completion pair
The selection of a certain layer.
In addition, the other compositions and effect of codec type vertical gate 3D NAND of the embodiment of the present invention and forming method thereof
All be for a person skilled in the art it is known, in order to reduce redundancy, do not repeat them here.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not
Centainly refer to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be any
One or more embodiment or examples in can be combined in any suitable manner.
Although an embodiment of the present invention has been shown and described, it will be understood by those skilled in the art that: not
A variety of change, modification, replacement and modification can be carried out to these embodiments in the case where being detached from the principle of the present invention and objective, this
The range of invention is by claim and its equivalent limits.
Claims (8)
1. a kind of codec type vertical gate 3D NAND forming method, which comprises the following steps:
Substrate is provided；
The first separation layer is formed in the substrate；
One or more layers semiconductor layer is formed on first separation layer；
One or more layers described semiconductor layer is etched to form multiple grooves, the multiple groove extends to first separation layer
Top surface；
Silica tunnel layer is formed to the deposit silica of the multiple groove；
Deposit silicon nitride electric charge capture layer and silicon dioxide blocking layer on the silica tunnel layer；
Grid is formed in the multiple groove and on the silicon dioxide blocking layer at the top of the multiple groove
Structure；
Polysilicon layer is formed on the silicon dioxide blocking layer at the top of the multiple groove；
Multiple grid materials are etched to the gate structure and fill hole, the multiple grid material filling hole extends to described first
The top surface of separation layer fills hole to the polysilicon layer etching source material, and source electrode material filling hole extends to institute
State the top surface of the first separation layer；
Deposition of electrode material in hole and the multiple grid material filling hole is filled in the source electrode material.
2. codec type vertical gate 3D NAND forming method according to claim 1, which is characterized in that the substrate has
Patterned surface.
3. codec type vertical gate 3D NAND forming method according to claim 1, which is characterized in that the substrate be Si,
SiGe、SiC、GaAs、Ge、GaN、GaP、InP、Ga2O3、Al2O3、AlN、ZnO、LiGaO2、LiAlO2One of.
4. codec type vertical gate 3D NAND forming method according to claim 1, which is characterized in that further include following step
It is rapid:
Heavy doping is carried out to the specified region of one or more layers semiconductor layer.
5. a kind of codec type vertical gate 3D NAND characterized by comprising
Substrate；
It is formed in the first separation layer of the substrate；
It is formed in one or more layers semiconductor layer on first separation layer, wherein in one or more layers described semiconductor layer
Multiple grooves are provided with, the multiple groove extends to the top surface of first separation layer, and described one or more layers is partly led
Multiple holes are etched on body layer, the multiple hole extends to the top surface of first separation layer；
The silica tunnel layer being formed on the multiple groove；
The silicon dioxide blocking layer being formed on the silica tunnel layer；
Multiple gate structures, the multiple gate structure are separately positioned in the multiple groove, across the multiple groove
In multiple holes on top and one or more layers described semiconductor layer；
Polysilicon layer, the polysilicon layer across the multiple groove top and be formed on silicon dioxide blocking layer, institute
It states and source is set on polysilicon layer.
6. codec type vertical gate 3D NAND according to claim 5, which is characterized in that the substrate has graphical table
Face.
7. codec type vertical gate 3D NAND according to claim 5, which is characterized in that the substrate be Si, SiGe,
SiC、GaAs、Ge、GaN、GaP、InP、Ga2O3、Al2O3、AlN、ZnO、LiGaO2、LiAlO2One of.
8. codec type vertical gate 3D NAND according to claim 5, which is characterized in that one or more layers described semiconductor
Heavily doped region is provided on layer.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103226973A (en) * | 2012-01-30 | 2013-07-31 | 群联电子股份有限公司 | NAND flash memory unit, NAND flash memory array, and methods for operating them |
| CN104392997A (en) * | 2014-11-12 | 2015-03-04 | 清华大学 | Step type vertical gate NAND and forming method thereof |
| US9024374B2 (en) * | 2010-07-06 | 2015-05-05 | Macronix International Co., Ltd. | 3D memory array with improved SSL and BL contact layout |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9024374B2 (en) * | 2010-07-06 | 2015-05-05 | Macronix International Co., Ltd. | 3D memory array with improved SSL and BL contact layout |
| CN103226973A (en) * | 2012-01-30 | 2013-07-31 | 群联电子股份有限公司 | NAND flash memory unit, NAND flash memory array, and methods for operating them |
| CN104392997A (en) * | 2014-11-12 | 2015-03-04 | 清华大学 | Step type vertical gate NAND and forming method thereof |
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