CN105529264A

CN105529264A - LDMOS transistor and LDMOS transistor forming method

Info

Publication number: CN105529264A
Application number: CN201410522011.6A
Authority: CN
Inventors: 李勇; 赵杰
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: SMIC New Technology Research and Development Shanghai Corp
Priority date: 2014-09-30
Filing date: 2014-09-30
Publication date: 2016-04-27
Anticipated expiration: 2034-09-30
Also published as: CN105529264B

Abstract

The invention discloses an LDMOS transistor and an LDMOS transistor forming method. The LDMOS transistor forming method comprises the steps of: providing a semiconductor substrate which is provided with fin parts; forming a drift region in each fin part; forming gate structures crossing the fin parts, wherein the gate structures cover the top part and side walls of the fin parts, and the gate structures cover the drift regions partially; forming source material layers and drain material layers in the fin parts on both sides of each gate structure, wherein the drain material layers are positioned in the drift regions; and carrying out ion implantation in the source material layers to form sources, and carrying out ion implantation in the drain material layers to form a drain. The LDMOS transistor formed by adopting the LDMOS transistor forming method has improved performance.

Description

The formation method of ldmos transistor and ldmos transistor

Technical field

The present invention relates to semiconductor applications, particularly relate to formation method and the ldmos transistor of ldmos transistor.

Background technology

LDMOS transistor (LateralDiffusionMOS, LDMOS), owing to possessing high-breakdown-voltage, the characteristic with CMOS technology compatibility, is widely used in power device.Compared with Conventional MOS transistors, LDMOS device has an isolation structure at least between drain region and grid.When LDMOS connects high pressure, bear higher voltage drop by this isolation structure, obtain the object of high-breakdown-voltage.

Prior art discloses a kind of fin ldmos transistor, the formation method of above-mentioned fin ldmos transistor is as follows:

With reference to figure 1 and Fig. 2, provide Semiconductor substrate 10, described Semiconductor substrate has the first fin 111, second fin 112 and the 3rd fin 113 between the first fin 111 and the second fin 112.The length of the 3rd fin 113 is much smaller than the first fin 111 and the second fin 112.

Formed between the first fin 111 and the 3rd fin 113 between first fleet plough groove isolation structure 121, second fin 112 and the 3rd fin 113 and form the second fleet plough groove isolation structure 122.The height of the first fleet plough groove isolation structure 121 and the second fleet plough groove isolation structure 122 lower than the first fin 111 to the height of the 3rd fin 113.

Form the first grid structure 131 across the first fin 111, described first grid structure 131 covers top and the sidewall of the first fin 111.First grid structure 131 is cover part first fleet plough groove isolation structure 121 also.Wherein, first grid structure 131 is polysilicon gate construction, comprises the first silicon oxide layer (not shown) and is positioned at the first polysilicon layer on the first silicon oxide layer.

Form the second grid structure 132 across the second fin 112, described second grid structure 132 covers top and the sidewall of the second fin 112.Second grid structure 132 is cover part second fleet plough groove isolation structure 122 also.Second grid structure 132 is also polysilicon gate construction, comprises the second silicon oxide layer (not shown) and is positioned at the second polysilicon layer on the second silicon oxide layer.

With reference to figure 3, in the first fin 111 of first grid structure 131 side, form the first source electrode groove 141a, in the second fin 112 of second grid structure 132 side, form the second source electrode groove 142a.Drain recesses 15a is formed in the 3rd fin 113.

With reference to figure 4, form germanium silicon layer at the first source electrode groove 141a (with reference to figure 3), the second source electrode groove 142a (with reference to figure 3), then ion implantation is carried out to described germanium silicon layer, respectively corresponding formation the first source electrode 141 and the second source electrode 142.In drain recesses 15a, form germanium silicon layer, ion implantation is carried out to the germanium silicon layer of drain recesses, form drain electrode 15.Wherein germanium silicon layer is all higher than each fin, and the corresponding source electrode formed and drain electrode are also all higher than each fin.

Then, with reference to figure 5, form dielectric layer 16, cover the first fin 111, first source electrode 141, first grid structure 131, first fleet plough groove isolation structure 121, drain electrode the 15, the 3rd fin 113, second fleet plough groove isolation structure 122, second grid structure 132, second source electrode 142 and the second fin 112.

Then, with reference to figure 6, remove first grid structure 131, in dielectric layer, form first grid texture grooves 171a, bottom described first grid texture grooves 171a, expose the first fin 111 and part first fleet plough groove isolation structure 121.Remove second grid structure 132, in dielectric layer, form second grid texture grooves 172a, bottom described second grid texture grooves 172a, expose the second fin 112 and part second fleet plough groove isolation structure 122.

Then with reference to figure 7, in first grid texture grooves 171a, fill the first aluminum gate structure material layer, form the first aluminum gate structure 171.Wherein, the first aluminum gate structure 171 comprises first grid oxygen layer (not shown) and is positioned at the first aluminium lamination in first grid oxygen layer.In second grid texture grooves 172a, fill the second aluminum gate structure material layer, form the second aluminum gate structure 172.Wherein, the second aluminum gate structure 172 comprises second gate oxygen layer (not shown) and is positioned at the second aluminium lamination in second gate oxygen layer.

When ldmos transistor is opened, voltage is applied in drain electrode 15 and the first source electrode 141, electric current can flow in the process of drain electrode 15 by the first source electrode 141, due to the existence of the first fleet plough groove isolation structure 121, the Electric Field Distribution of ldmos transistor is changed, and the first fleet plough groove isolation structure 121 bears larger electric field.Voltage is applied in drain electrode 15 and the second source electrode 142, electric current can flow in the process of drain electrode 15 by the second source electrode 142, due to the existence of the second fleet plough groove isolation structure 122, Electric Field Distribution around second fleet plough groove isolation structure 122 is changed, and the second fleet plough groove isolation structure 122 bears larger electric field.

But the performance of the fin ldmos transistor of prior art is not good.

Summary of the invention

The problem that the present invention solves is that the performance of the fin ldmos transistor of prior art is not good.

For solving the problem, the invention provides a kind of formation method of ldmos transistor, comprising:

There is provided Semiconductor substrate, described Semiconductor substrate has fin;

Drift region is formed in described fin;

Form the grid structure across described fin, described grid structure covers top and the sidewall of described fin, and described grid structure part covers described drift region;

In the fin of described grid structure both sides, form source electrode material layer and drain material layer, described drain material layer is in described drift region;

Ion implantation is carried out to described source electrode material layer and drain material layer, forms source electrode and drain electrode.

Optionally, described Semiconductor substrate also has well region, and described well region surrounds described drift region.

Optionally, the injection type of described drift region is contrary with the injection type of described well region.

Optionally, form the step of source electrode material layer and drain material layer in the fin of described grid structure both sides before, also comprise: formation side wall around described grid structure.

Optionally, after surrounding's formation side wall of described grid structure, form the step of source electrode material layer and drain material layer in the fin of described grid structure both sides before, also comprise the following steps: to form the first barrier layer on described drift region, described first barrier layer is identical with described grid structure thickness, and described first barrier layer is for defining position and the width of drain electrode.

Optionally, described first barrier layer is polysilicon gate construction.

Optionally, after forming the first barrier layer, form the step of source electrode material layer and drain material layer in the fin of described grid structure both sides before, be also included in the step forming side wall around the first barrier layer.

Optionally, form source electrode material layer and drain material layer in the fin of described grid structure both sides while, also form at least one pseudo-drain material layer, described pseudo-drain material layer is in described drift region; While ion implantation is carried out to described source electrode material layer and drain material layer, ion implantation is carried out to described pseudo-drain material layer, form pseudo-drain electrode.

Optionally, described first barrier layer is at least one, described grid structure and described the first barrier layer near grid structure define the position and width that drain, the position of remaining two described puppet drain electrodes of adjacent first barrier layer definition and width, or, described first barrier layer is at least two, the position of two adjacent the first barrier layer definition drain electrodes and width, the position of the pseudo-drain electrode of remaining first barrier layer definition and width.

Optionally, the formation method of described source electrode material layer, drain material layer and pseudo-drain material layer comprises: with described side wall, the first barrier layer for mask etching fin, in fin, form source electrode groove, drain recesses and pseudo-drain recesses, described drain recesses and described pseudo-drain recesses are in described drift region; In described source electrode groove, drain recesses and pseudo-drain recesses, correspondence forms source electrode material layer, drain material layer and pseudo-drain material layer respectively.

Optionally, when described transistor is PMOS transistor, described source electrode material layer, described drain material layer and described pseudo-drain material layer are germanium silicon layer; When described transistor is nmos pass transistor, described source electrode material layer, described drain material layer and described pseudo-drain material layer are silicon carbide layer.

Optionally, form the step of source electrode material layer and drain material layer in the Semiconductor substrate of described grid structure both sides before, also comprise the following steps: to form the second barrier layer at grid structure away from the side of drift region, described second barrier layer is identical with described grid structure thickness, the position of described second barrier layer definition source electrode and width.

Optionally, described second barrier layer is polysilicon gate construction, after forming the second barrier layer, before forming the step of source electrode material layer and drain material layer, is also included in the step forming side wall around the second barrier layer in the fin of described grid structure both sides.

Optionally, two described LOMOS transistor common drains or respectively there is drain electrode.

Optionally, before formation source electrode material layer and drain material layer, form the second barrier material layer at described grid structure away from the side of described drift region, or, the drift region of the opposite side of described grid structure is formed the first barrier material layer;

Fin under first barrier material layer and described first barrier material layer is etched, in described first barrier material layer, form at least one first through hole, form drain recesses and pseudo-drain recesses in described fin, remaining first barrier material layer is the first barrier layer, or

Etch the fin under the second barrier material layer and described second barrier material layer, form the second through hole, and in Semiconductor substrate, form source electrode groove in described second barrier material layer, remaining second barrier material layer is the second barrier layer;

Form side wall at described first through-hole side wall or form side wall at described second through-hole side wall;

In described drain recesses and pseudo-drain recesses, form drain material layer and pseudo-drain material layer respectively or form source electrode material layer in described source electrode groove.

Optionally, before formation source electrode material layer and drain material layer, form the second barrier material layer in the side of described grid structure away from described drift region and on the drift region of the opposite side of described grid structure, form the first barrier material layer;

Optionally, fin under first barrier material layer and described first barrier material layer is etched, in described first barrier material layer, form at least one first through hole, form drain recesses and dummy grid groove in fin, remaining first barrier material layer is the first barrier layer;

Etch the fin under the second barrier material layer and described second barrier material layer, form the second through hole, and in fin, form source electrode groove in described second barrier layer, remaining second barrier material layer is the second barrier layer;

Form side wall at described first through-hole side wall and form side wall at described second through-hole side wall;

Corresponding formation drain material layer, pseudo-drain material layer and source electrode material layer in described drain recesses, pseudo-drain recesses and in source electrode groove.

The present invention also provides a kind of ldmos transistor, comprising: Semiconductor substrate, and described Semiconductor substrate has fin; Across the grid structure of described fin, described grid structure covers top and the sidewall of described fin; Be positioned at source electrode and the drain electrode of the Semiconductor substrate of described grid structure both sides;

Ldmos transistor of the present invention also comprises:

Drift region, described drift region is positioned at described fin, and described grid structure part covers described drift region, and described drain electrode is positioned at described drift region.

Optionally, also comprise: the first barrier layer, on described drift region, for defining position and the width of described drain electrode.

Optionally, described ldmos transistor also comprises pseudo-drain electrode, in described drift region, described first barrier layer is at least one, described grid structure and described the first barrier layer near grid structure define the position and width that drain, the position of remaining two described puppet drain electrodes of adjacent first barrier layer definition and width, or, described first barrier layer is at least two, the position of two adjacent the first barrier layer definition drain electrodes and width, the position of the pseudo-drain electrode of remaining first barrier layer definition and width.

Optionally, also comprise: the second barrier layer, in the side of described grid structure away from described drift region, for defining position and the width of described source electrode.

Compared with prior art, technical scheme of the present invention has the following advantages:

In the fin of Semiconductor substrate, define drift region instead of fleet plough groove isolation structure of the prior art, the Electric Field Distribution around drift region is changed, and can bear larger electric field.In addition, the composition of fleet plough groove isolation structure is generally silica, and source electrode and drain material layer cannot be formed on silicon oxide layer.Just because of there is the existence of drift region in the fin of Semiconductor substrate, do not have fleet plough groove isolation structure.Therefore, when forming drain material layer in fin, can prevent the formation of silicon oxide layer to drain material layer in fleet plough groove isolation structure from having an impact, thus the performance of drain material layer can be improved, and then improve the performance of LDMOS of follow-up formation.

Accompanying drawing explanation

Fig. 1 is Semiconductor substrate and be positioned at the plan structure schematic diagram of first grid structure, second grid structure and the 3rd grid structure in Semiconductor substrate in the fin ldmos transistor of prior art;

Fig. 2 is the cross-sectional view in the AA direction along Fig. 1;

Fig. 3 ~ Fig. 7 is the cross-sectional view of each forming step after Fig. 2 step of the fin ldmos transistor of prior art;

Fig. 8 ~ Figure 12 is the cross-sectional view of each forming step in the ldmos transistor of the embodiment of the present invention one;

Figure 13 is the cross-sectional view of the ldmos transistor of the embodiment of the present invention three.

Embodiment

Through finding and analyzing, the reason that the performance of the fin ldmos transistor of prior art is not good is as follows:

(1) combine referring to figs. 2 and 3, the 3rd fin 113 in, form the method for drain recesses 15a is photoetching, etching, because the length of the 3rd fin 113 is less, by the impact of lithographic accuracy, is very difficultly just in time aligned in the 3rd fin 113 and carries out etching operation.Part drain recesses 15a can be formed on the first adjacent fleet plough groove isolation structure 121 or/and on the second fleet plough groove isolation structure 122.Therefore, the partial sidewall of drain recesses 15a is that the first fleet plough groove isolation structure 121 is or/and the second fleet plough groove isolation structure 122.

When growth forms germanium silicon layer in drain recesses 15a, at the first fleet plough groove isolation structure 121 or/and the performance of the germanium silicon layer of the second fleet plough groove isolation structure 122 place formation is bad, even cannot form germanium silicon layer.Especially at the first fleet plough groove isolation structure 121 or/and the performance of the germanium silicon layer of the formation of the corner of the second fleet plough groove isolation structure 122 is more bad.Reason is as follows: germanium silicon layer material be on the 3rd fin 113 of silicon growth performance good.And the material of the first and second fleet plough groove isolation structures is silicon dioxide.Therefore, the Performance Ratio that germanium silicon layer grows on silica is poor, even cannot grow.

Therefore, the Performance Ratio of the drain electrode of follow-up formation is poor, thus affects the performance of the ldmos transistor of follow-up formation.

(2) combine with reference to figure 5 to Fig. 7, first grid structure 131 part covers the first fleet plough groove isolation structure 121, and second grid structure 132 part covers the second fleet plough groove isolation structure 122, therefore, first grid structure 131 and second grid structure 132 longer.In the process of formation first aluminum gate structure 171 and the second aluminum gate structure 172, the first aluminium lamination is more soft longer, during cmp operation formation the first aluminium lamination, easily occurs (dishing) phenomenon that caves in.Therefore, the performance of the first aluminum gate structure 171 adopting existing method to be formed is not good.In addition, the second aluminium lamination is more soft longer, during cmp operation formation the second aluminium lamination, also easily occurs depressed phenomenon.Therefore, the performance of the second aluminum gate structure 172 adopting existing method to be formed is not good yet.

The germanium silicon layer at (3) first source electrode 141 places needs to need higher than the second fin 112 higher than the germanium silicon layer at the first fin 111, second source electrode 142 place, and the germanium silicon layer at 15 places that drain needs higher than the 3rd fin 113.The germanium silicon layer at such first source electrode 141 place and drain electrode 15 places can apply optimum stress to the raceway groove under first grid structure 131, carrys out the mobility of maximized raising charge carrier.In like manner, the germanium silicon layer at the second source electrode 142 place and drain electrode 15 places can apply optimum stress to the raceway groove under second grid structure 132, carrys out the mobility of maximized raising charge carrier.

But the growing height of germanium silicon layer is directly proportional to the size of the growing space of germanium silicon layer.For fin ldmos transistor, the size of the first source electrode groove 141a, the second source electrode groove 142a and drain recesses 15a is too little, and how accurately to control the growing height of above-mentioned germanium silicon layer everywhere, existing technique is difficult to accomplish.Following situation can be there is:

1. to form germanium silicon layer in drain recesses 15a, this germanium silicon layer is that example is described higher than the first fin or the second fin.

With reference to figure 4, be directly proportional to the distance between first grid structure 131, second grid structure 132 at the growing height of the germanium silicon layer higher than first, second fleet plough groove isolation structure of drain electrode place.In prior art, distance between first grid structure 131 and second grid structure 132 is larger, therefore, the height that germanium silicon layer grows in drain recesses not only can exceed the height of first, second fleet plough groove isolation structure, but also can exceed the height of first grid structure 131, second grid structure 132.The germanium silicon layer volume formed between first grid structure 131 and second grid structure 132 is very large, for spherical.

2. to form germanium silicon layer in the first source electrode groove, this germanium silicon layer is that example is described higher than the first fin or the second fin.

With reference to figure 4, the germanium silicon layer higher than the first fin 111 being positioned at the first source electrode groove only has the growing height of first grid structure 131 to the germanium silicon layer at the first source electrode place restricted.Therefore, the growth technique due to the germanium silicon layer at the first source electrode place is difficult to the growing height accurately controlling germanium silicon layer, and the germanium silicon layer volume higher than the first source electrode place of the first fin 111 also can be very large, for spherical, and higher than first grid structure 131.

3. the situation forming germanium silicon layer in the second source electrode groove is identical with the situation forming germanium silicon layer in the first source electrode groove, and volume also can be very large, in spherical and higher than second grid structure 132.

Therefore, the height of the germanium silicon layer of the method formation of prior art all can exceed first grid structure 131, second grid structure 132.Formed in the process of the first aluminium lamination and the second aluminium lamination at employing cmp, cmp can stop on germanium silicon layer, can't stop in first grid structure 131 and second grid structure 132 place, thus the thickness of the first aluminium lamination and the second aluminium lamination is increased, further affect the performance of the first aluminum gate structure 171 and the second aluminum gate structure 172.

Therefore, in order to solve the problems of the technologies described above, the invention provides a kind of formation method of ldmos transistor, adopt the formation method of ldmos transistor of the present invention, the performance of the ldmos transistor of follow-up formation can be improved.Below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.

Embodiment one

The present embodiment is described with two adjacent ldmos transistor common drains.

In conjunction with reference to figure 8 and Fig. 9, provide Semiconductor substrate 20.

In the present embodiment, Semiconductor substrate 20 is silicon substrate.Semiconductor substrate 20 has at least one fin 201.There is between each fin 201 insulating barrier 202 lower than fin 201.The material of insulating barrier 202 is silica.Concrete formation method is as follows:

Semiconductor substrate 20 is formed patterned first mask layer (not shown), and described patterned first mask layer defines fin position to be formed; With described patterned first mask layer for mask etching Semiconductor substrate 20 forms at least one bulge-structure, then between bulge-structure, height of formation is identical and lower than the insulating barrier 202 of bulge-structure, insulating barrier 202 plays the insulating effect between semiconductor device.The described projective structure higher than insulating barrier 202 is fin 201.

In other embodiments, Semiconductor substrate is silicon-on-insulator (SOI).Silicon-on-insulator comprises bottom silicon layer, the insulating barrier be positioned on bottom silicon layer, the top silicon layer be positioned on insulating barrier.Described top silicon layer also belongs to protection scope of the present invention for the formation of at least one fin.

Continue to combine with reference to figure 8 and Fig. 9, in Semiconductor substrate, form drift region 203.

In the present embodiment, formed after fin 201, ion implantation formation well region (not shown) is carried out to fin 201 and lower Semiconductor substrate thereof.

After forming well region, ion implantation is carried out to fin 201, form drift region 203.Drift region 203 surround by well region.The injection degree of depth of drift region 203 is greater than the degree of depth of insulating barrier 202.The injection type of drift region 203 is contrary with the injection type of well region.The ldmos transistor that two of follow-up formation are adjacent can share a drift region 203.

Then, with reference to Figure 12, fin 201 forms first grid structure 21, second grid structure 22, first barrier layer and the second barrier layer.

First grid structure 21 and second grid structure 22 are polysilicon gate construction or metal gate structure.First barrier layer and the second barrier layer are polysilicon gate construction.

First grid structure 21 and second grid structure 22 are effective grid in the ldmos transistor of follow-up formation.First grid structure 21 and second grid structure 22 be drift region 203 described in cover part respectively.

Although the first barrier layer and the second barrier layer are polysilicon gate constructions, are non-effective grid, do not play the effect of grid.First barrier layer can prevent the drain material layer overgrowth in subsequent step.Second barrier layer can prevent the source electrode material layer growth in subsequent step excessive.In the present embodiment, arranging of the first barrier layer and the second barrier layer is specific as follows:

There is between first grid structure 21 and second grid structure 22 first barrier layer, barrier layer 231 to the first 236, and the first barrier layer, barrier layer 231 to the first 236 is all positioned on drift region 203.First barrier layer 231 is adjacent with first grid 21, and the first barrier layer 236 is adjacent with second grid 22.

In the present embodiment, the first adjacent barrier layer 233 and the first barrier layer 234 define position and the width of the drain electrode 264 of follow-up formation.Remaining first adjacent barrier layer can define position and the width of the puppet drain electrode of follow-up formation.The position that the puppet that first grid structure 21 also defines follow-up formation with the first barrier layer 231 near first grid structure 21 drains and width.The position that the puppet that second grid structure 22 defines follow-up formation with the first barrier layer 231 near second grid structure 22 drains and width.

Wherein, pseudo-drain electrode has the shape of drain electrode 264, but does not have the function of drain electrode 264.Follow-up to LDMOS apply voltage time, conducting is carried out in drain electrode and source electrode, and puppet drain do not participate in above-mentioned electrical connection.The effect of pseudo-drain electrode is as follows: if drain electrode was lost efficacy, and now applies voltage to puppet drain electrode, also can have the function of drain electrode.On the other hand, in the process of photoetching, the dimensional accuracy of drain electrode can better be controlled.

In other embodiments, other two adjacent the first barrier layers also can define position and the width of the drain electrode of follow-up formation, belong to protection scope of the present invention.

In other embodiments, first grid structure can define position and the width of the drain electrode of follow-up formation with the first barrier layer near first grid structure, belongs to protection scope of the present invention.

In other embodiments, second grid structure can define position and the width of the drain electrode of follow-up formation with the first barrier layer near second grid structure, belongs to protection scope of the present invention.

In other embodiments, to the number not circumscribed on the first barrier layer.

In other embodiments, pseudo-drain electrode is not had to belong to protection scope of the present invention yet.

Continue with reference to Figure 12, the second barrier layer 241 is positioned on the fin 201 of first grid structure 21 away from side, drift region 203.Second barrier layer 242 is positioned on the fin 201 of second grid structure 22 away from side, drift region 203.In the present embodiment, the second barrier layer 241 and first grid structure 21 define position and the width of the first source electrode of follow-up formation.Second barrier layer 242 and second grid structure 22 define position and the width of the second source electrode of follow-up formation.

In other embodiments, can also form second barrier layer between first grid structure 21 and the second barrier layer 241, this second barrier layer is adjacent with first grid structure.This second barrier layer defines position and the width of the first source electrode together with the second barrier layer 241.

In other embodiments, between second grid structure 22 and the second barrier layer 242, also can also form second barrier layer, this second barrier layer is adjacent with second grid structure.This second barrier layer defines position and the width of the second source electrode together with the second barrier layer 242.

In the present embodiment, first grid structure 21 and second grid structure 22 are metal gate structure.First barrier layer and the second barrier layer are polysilicon gate construction.With reference to figure 9 to Figure 11, the concrete formation method on first grid structure 21, second grid structure 22, first barrier layer and the second barrier layer is as follows:

In conjunction with reference to figure 8, fin 201 forms gate dielectric material layer, in subsequent technique, for the formation of the gate dielectric layer of each dummy gate structure.Gate dielectric material layer forms polysilicon layer, in subsequent technique, for the formation of the polysilicon gate of each dummy gate structure.Then, form patterned second mask layer (not shown) on the polysilicon layer, with the second mask layer of described patterning for mask, gate dielectric material layer and polysilicon layer are etched, the first dummy gate structure A1 is formed successively to the other end, the second dummy gate structure A2, the 3rd dummy gate structure A3, the 4th dummy gate structure A4, the 5th dummy gate structure A5, the 6th dummy gate structure A6, the 7th dummy gate structure A7, the 8th dummy gate structure A8, the 9th dummy gate structure A9 and the tenth dummy gate structure A10 from one end of fin 201.First dummy gate structure A1 to the tenth dummy gate structure A10 is respectively across on fin 201, and corresponding top and the sidewall covering fin 201.

Second dummy gate structure A2 and the 9th dummy gate structure A9 respectively part cover described drift region, the second dummy gate structure A2 for the formation of first grid structure 21.9th dummy gate structure A9 be for the formation of second grid structure 22.3rd dummy gate structure A3 to the 8th dummy gate structure A8, on described drift region, is the first barrier layer, barrier layer 231 to the first 236.

First dummy gate structure A1 is the second barrier layer 241.Tenth dummy gate structure A10 is the second barrier layer 242.

Continue with reference to figure 8, the first dummy gate structure A1 to the tenth dummy gate structure A10 comprises the respective gate dielectric layer be positioned on fin 201 and the polysilicon gate being positioned at the correspondence on respective gate dielectric layer respectively.

Be second distance H2 between first dummy gate structure A1 and the second dummy gate structure A2, described second distance H2 is for defining position and the width of the first source electrode of follow-up formation.

Distance between two adjacent dummy gate structure between second dummy gate structure A2 to the 9th dummy gate structure A9 is the first distance H1, described first distance H1 for defining position and the width of the drain electrode of follow-up formation, also for define follow-up formation puppet drain electrode position and width.

Be the 3rd distance H3 between 9th dummy gate structure A9 and the tenth dummy gate structure A10, described 3rd distance H3 is for defining position and the width of the second source electrode of follow-up formation.

In other embodiments, there is no the 3rd dummy gate structure A3 to one or two dummy gate structure in the 5th dummy gate structure A5, belong to the scope of protection of the invention yet.

In other embodiments, there is no the 6th dummy gate structure A6 to one or two dummy gate structure in the 8th dummy gate structure A8, belong to the scope of protection of the invention yet.

In the present embodiment, after forming each dummy gate structure, around each dummy gate structure, form side wall.Formation method knows technology for those skilled in the art.

The reason forming side wall around each dummy gate structure is as follows:

(1) at the second dummy gate structure A2 in the 9th dummy gate structure A9, the side wall between adjacent dummy gate structure defines the drain electrode of follow-up formation and the position of pseudo-drain electrode and width.

Side wall around (2) first dummy gate structure A1 and the side wall between the second dummy gate structure A2 define position and the width of the first source electrode of follow-up formation.

Side wall around (3) the 9th dummy gate structure A9 and the side wall between the tenth dummy gate structure A10 define position and the width of the second source electrode of follow-up formation.

(4) if there is no side wall around each grid structure, then follow-up in the source electrode material layer of formation and the process of drain material layer, polysilicon gate corresponding in each dummy gate structure also can grow source electrode material layer and drain material layer.Like this, the source electrode material layer of follow-up formation and the volume of drain material layer can be larger, and the source electrode material layer of formation and the height of drain material layer can be higher.But, the source electrode material layer of formation and the volume of drain material layer and aspect ratio prior art little.

In other embodiments, if do not form side wall around each grid structure, also belong to the scope of protection of the invention.

Then, with reference to figure 9, with the side wall around each dummy gate structure for mask, fin is etched, in the fin 201 between the first dummy gate structure A1 and the second dummy gate structure A2, form the first source electrode groove.Form drain recesses in fin 201 between the 5th dummy gate structure A5 to the adjacent dummy grid in the 6th dummy gate structure A6, in the fin 201 between the second dummy gate structure A2 to the adjacent dummy grid in the 5th dummy gate structure A5, form pseudo-drain recesses.Other pseudo-drain recesses is formed in fin 201 between the 6th dummy gate structure A6 to the adjacent dummy grid in the 9th dummy gate structure A9.The second source electrode groove is formed in fin 201 between the 9th dummy gate structure A9 and the tenth dummy gate structure A10.

In the present embodiment, the first source electrode groove, the second source electrode groove, drain recesses and pseudo-drain recesses are formed simultaneously.Concrete formation method knows technology for those skilled in the art, does not repeat them here.

Then, continue with reference to figure 9, in the first source electrode groove, form the first source electrode material layer, in the second source electrode groove, form the second source electrode material layer, in drain recesses, form drain material layer, in pseudo-drain recesses, form pseudo-drain material layer.

In the present embodiment, when the ldmos transistor of follow-up formation is PMOS transistor, then the first source electrode material layer, the second source electrode material layer, drain material layer and each pseudo-drain material layer are germanium silicon layer.

The method forming germanium silicon layer is selective epitaxial growth.

In the present embodiment, the first source electrode material layer, the second source electrode material layer, drain material layer and each pseudo-drain material layer all a little more than fin 201, and lower than the height of each pseudo-grid structure.

In ldmos transistor of the prior art, formed the first source electrode material layer, the second source electrode material layer, drain material layer space larger, but, in this transistor, first source electrode material layer, the second source electrode material layer and drain material layer just need to exceed a little height of fin, otherwise cannot apply optimum stress to the raceway groove under each self-corresponding grid.But controlling the first source electrode material layer, the second source electrode material layer and drain material layer, just to exceed a little height of fin be very rambunctious in actual growth technique.Certainly, the height of pseudo-drain material layer is the same with the height of drain material layer is also very rambunctious.

Therefore, the present embodiment according to " growing height of germanium silicon layer is directly proportional to the growing space of germanium silicon layer " and principle, by controlling the growing space of germanium silicon layer, control the growing height of germanium silicon layer.Relative to prior art, by reducing the growing space of germanium silicon layer, reduce the growing height of germanium silicon layer.

Be specially, the growing space defining drain electrode in the present embodiment is the first distance H1.First distance H1 is less than the distance between first grid structure of the prior art and second grid structure, and therefore, the height of the drain material layer formed in the present embodiment can reduce, and at least this is highly not less than fin 201, not higher than the height of each dummy gate structure.Like this, in the step of follow-up formation metal gate structure, when adopting the metal gates in cmp metal gate structure, cmp operation can not stop on drain material layer in advance, and then the thickness of the metal gate layers in the metal gate structure of follow-up formation is met the requirements, to improve the performance of the LDMOS of follow-up formation.

The growing space defining the first source electrode material layer in the present embodiment is second distance H2.And the growing space of second distance H2 first source electrode material layer in prior art.Therefore, the height of the first source electrode material layer formed in the present embodiment can reduce, and at least this is highly not less than fin 201, not higher than the height of each dummy gate structure.Like this, in the step of follow-up formation metal gate structure, when adopting the metal gates in cmp metal gate structure, adopt cmp can not stop in advance on the first source electrode material layer.And then the thickness of the metal gate layers in the metal gate structure of follow-up formation is met the requirements, to improve the performance of the LDMOS of follow-up formation.

The growing space defining the second source electrode material layer in the present embodiment is the 3rd distance H3.And the growing space of the 3rd distance H3 second source electrode material layer in prior art.Therefore, the height of the second source electrode material layer formed in the present embodiment can reduce, and this is highly not less than fin 201, not higher than the height of each dummy gate structure.Like this, in the step of follow-up formation metal gate structure, when adopting the metal gates in cmp metal gate structure, cmp operation can not stop on the second source electrode material layer in advance.And then the thickness of the metal gate layers in the metal gate structure of follow-up formation is met the requirements, improve the performance of the LDMOS of follow-up formation.

Further, the first distance H1 in the present embodiment, second distance H2 and the 3rd distance H3 are respectively and are more than or equal to 0.01 micron and are less than or equal to 0.2 micron.If the first distance H1, second distance H2 and the 3rd distance H3 are too large, problems of the prior art (3) will be produced.If the first distance H1, second distance H2 and the 3rd distance H3 too little, then, be not easy to be formed higher than the germanium silicon layer of fin 201.

After forming above-mentioned germanium silicon layer, on above-mentioned germanium silicon layer, form silicon cap layer (not shown) respectively.Form acting as of silicon cap layer: in subsequent step, need to form metal silicide layer on germanium silicon layer.Germanium silicon layer is too much germanic, and the performance that germanium silicon layer is formed metal silicide is not good.And on silicon, form the better performances of metal silicide layer.So need to form silicon cap layer between the metal silicide layer and above-mentioned germanium silicon layer of follow-up formation.

Then, ion implantation is carried out to the first source electrode material layer, the second source electrode material layer, drain material layer and each pseudo-drain material layer, corresponding formation first source electrode 251, second source electrode 252, drain electrode 264 and each puppet drain electrode (pseudo-drain electrode 261 to puppet drain electrode 263, pseudo-drain electrode 265 to puppet drain electrode 267).Wherein drain electrode is the common drain of two ldmos transistors.

In other embodiments, when the ldmos transistor of follow-up formation is NMOS.Then the first source electrode material layer, the second source electrode material layer, drain material layer and pseudo-drain material layer are silicon carbide layer.

Then, with reference to Figure 10, the drain electrode between dummy gate structure adjacent in Semiconductor substrate 20, fin 201, first dummy gate structure A1, the first source electrode, the second dummy gate structure A2 are to the 9th dummy gate structure A9, the second dummy gate structure A2 to the 9th dummy gate structure A9 and pseudo-drain electrode, the second source electrode, the tenth dummy grid A10 form interlayer dielectric layer 27.

The material of interlayer dielectric layer 27 is silica, carborundum or silicon oxynitride.Interlayer dielectric layer 27 can be also low-k materials or ultralow-k material film, and the dielectric constant of described low-k materials is less than or equal to 3, and the dielectric constant of described ultralow-k material film is less than or equal to 2.7.The formation method of interlayer dielectric layer 27 is deposition.Be specifically as follows high-density plasma (HighDensityPlasma, HDP) chemical vapour deposition (CVD) or high depth ratio fill out ditch technique (HighAspectRatioProcess, HARP) or flowing chemical vapour deposition (CVD) (FlowableChemicalVaporDeposition, FCVD).Adopt above-mentioned three kinds of method filling capacities comparatively strong, interlayer dielectric layer 27 density of formation is higher.Certainly, interlayer dielectric layer 27 also can be other depositing operations well known to those skilled in the art, also belongs to protection scope of the present invention.

In the present embodiment, interlayer dielectric layer 27 is equal to the tenth dummy gate structure A10 with the first dummy gate structure A1.

Then, in conjunction with reference Figure 10 and Figure 11, after forming interlayer dielectric layer 27, remove part second dummy gate structure layer A2, the 9th dummy gate structure layer A9, in interlayer dielectric layer, form first grid texture grooves and second grid texture grooves respectively, bottom described first grid texture grooves and second grid texture grooves, expose fin 201 and part drift region 203 respectively.

Wherein, the formation method of first grid texture grooves, second grid texture grooves is as follows: form patterned 3rd mask layer (not shown) at the top of interlayer dielectric layer 27, with described patterned 3rd mask layer for mask, etching removal second dummy gate structure A2 and the 9th dummy gate structure A9, forms first grid texture grooves and second grid texture grooves respectively.

It should be noted that, first grid texture grooves and second grid texture grooves are 3 ~ 100nm with the cover width H4 of drift region 203 respectively.If above-mentioned cover width H4 is too little, the first grid structure 21 formed in first grid texture grooves cannot control well region and drift region simultaneously.The second grid structure 22 formed in second grid texture grooves cannot control well region and drift region simultaneously, and the transmission path in electronics or hole is easily blocked.Above-mentioned cover width H4 is the bigger the better, but described cover width H4 is larger, the length dimension of the first metal gate layers in the first grid structure of follow-up formation is larger, when adopting the method for cmp to grind the first metal gate layers, more easily there is depression defect.In like manner, described cover width H4 is larger, and the length dimension of the second metal gate layers in the second grid structure of follow-up formation is larger, when adopting the method for cmp to grind the second metal gate layers, more easily occurs depression defect.

Then, with reference to Figure 12, the first high-k gate dielectric layer and the second high-k gate dielectric layer is formed respectively in the bottom of first grid texture grooves and second grid texture grooves and sidewall, afterwards, the first metal layer and the second metal level is formed respectively on the first high-k gate dielectric layer and the second high-k gate dielectric layer, described the first metal layer and the second metal level are higher than each dummy gate structure and interlayer dielectric layer 27, afterwards, the method of cmp is adopted to be removed by the metal level higher than each dummy gate structure and interlayer dielectric layer 27, form the first metal gate layers and the second metal gate layers respectively.First metal gate layers and the first high-k gate dielectric layer define first grid structure 21.Second metal gate layers and the second high-k gate dielectric layer define second grid structure 22.

And the 3rd dummy gate structure A3 between first grid structure 21 and second grid structure 22 is the first barrier layer to the 9th dummy gate structure A8.Be respectively the first barrier layer, barrier layer 234, first, barrier layer 233, first, barrier layer 232, first, barrier layer 231, first 235 and the first barrier layer 236.

So first grid structure 21, second grid structure 22, first barrier layer, the second barrier layer just defines.

Continue with reference to Figure 12, two adjacent the first barrier layers 233 and the first barrier layer 234 define position and the width of drain electrode 264, first barrier layer 231 and first grid structure 21 define pseudo-drain 261 position and width, first barrier layer 231 and the second barrier layer 232 define pseudo-drain 262 position and width, second barrier layer 232 and the 3rd barrier layer 233 define pseudo-drain 263 position and width, 4th barrier layer 234 and the 5th barrier layer 235 define pseudo-drain 265 position and width, 5th barrier layer 235 and the 6th barrier layer 236 define pseudo-drain 266 position and width, 6th barrier layer 236 and second grid structure 22 define pseudo-drain 267 position and width.

In other embodiments, described first grid structure and described the first barrier layer near first grid structure define the position and width that drain, or, near the position of the first barrier layer definition drain electrode of second grid structure and width described in described second grid domain.The position of remaining two described puppet drain electrodes of adjacent first barrier layer definition and width.

In the present embodiment, the first barrier layer is except defining drain electrode, the position of pseudo-drain electrode and width.First barrier layer also has an effect: produce depressed phenomenon in the process of the second metal gates in the process of the first metal gate layers in the first grid structure preventing the method for employing cmp from being formed, in formation second grid structure.Reason is as follows: the material of the first metal gate layers and the second metal gate layers is aluminium or copper, and relative to polysilicon gate, material is softer.If do not form the first barrier layer, in the process of above-mentioned cmp the first metal layer and the second metal level, there is no the support of polysilicon layer harder in the first barrier layer, when the first metal layer that grinding is so long and the second metal level, there will be depressed phenomenon.

Further, isolate each polysilicon layer in each pseudo-that drain, in discrete state each pseudo-grid structure and can better alleviate above-mentioned depressed phenomenon.That is, the number of above-mentioned each puppet drain electrode, more for the number of dummy grid of isolating between each puppet drain electrode, the effect alleviating above-mentioned depressed phenomenon is more obvious.

It should be noted that, the fin 201 in the present embodiment is overall structures, and the first source electrode, drain electrode and the second source electrode are all formed on this fin 201.And unlike prior art, the first source electrode is formed on the first fin, the second source electrode is formed on the second fin, and drain electrode is formed on the 3rd fin.There is between first fin and the second fin the first fleet plough groove isolation structure.Between second fin and the 3rd fin, there is the second fleet plough groove isolation structure.In the present embodiment, in fin 201, define drift region 203, this drift region 203 surround by the well region in fin.This drift region 203 instead of the first fleet plough groove isolation structure of the prior art and the second fleet plough groove isolation structure.The well region of drift region 203 and this drift region of encirclement forms depletion layer, and the Electric Field Distribution around such drift region 203 is changed, and can bear larger electric field.Therefore, drift region 203 is identical with the effect of the second fleet plough groove isolation structure with the first fleet plough groove isolation structure of the prior art.

In addition, exactly because there is the existence of drift region 203, the first fleet plough groove isolation structure and/or the second fleet plough groove isolation structure is not had around drain recesses, therefore, when growing drain material layer in drain recesses, the place that cannot grow drain material layer is there will not be in drain recesses, drain material layer all can solid in drain recesses, especially the drain material layer of the corner of drain recesses also can grow fine, thus improve the performance of drain material layer, and then improve the performance of LDMOS of follow-up formation.

In other embodiments, first grid structure 21 and second grid structure 22 can also be polysilicon gate construction, also belong to protection scope of the present invention.If first grid structure 21 and second grid structure 22 are polysilicon gate construction, then above-mentioned formation first grid texture grooves and second grid texture grooves step and in first grid texture grooves and second grid texture grooves, form the first and second high-k gate dielectric layers respectively, the forming step of the first and second metal gate layers that correspondence is positioned on the first and second high-k gate dielectric layers can omit.

In other embodiments, fin is not formed the second barrier layer and belongs to protection scope of the present invention yet.Just, the first source electrode material layer formed in subsequent step and the height of the second source electrode material layer and width can increase, and there will be the problems of the prior art (3).

In other embodiments, fin does not form the first barrier layer, belongs to protection scope of the present invention yet.The height of the drain material layer just formed and width dimensions are very large, also there will be the problems of the prior art (3).

In other embodiments, the formation method on first grid structure, the first barrier layer, second grid structure and the second barrier layer is as follows, also belongs to protection scope of the present invention.Be specially:

Fin is first formed the first polysilicon gate construction and the second polysilicon gate construction.

Then, form the first barrier material layer and the second barrier material layer in the both sides of described first polysilicon gate construction, form the first barrier material layer and the second barrier material layer in the both sides of the second polysilicon gate construction.The first barrier material layer between first polysilicon gate construction and the second polysilicon gate construction is one, and shares, and therefore, is positioned at the centre of the 5th dummy gate structure and the 6th dummy gate structure.In the present embodiment, the first barrier material layer and the second barrier material layer are polysilicon gate construction.Specifically please refer to the first dummy gate structure A1 in an embodiment, the 3rd dummy gate structure A3 structure to the 8th dummy gate structure A8, the tenth dummy gate structure A10.

Then, form interlayer dielectric layer, this interlayer dielectric layer covers Semiconductor substrate, fin, the second barrier material layer, the first polysilicon gate construction, the first barrier material layer, the second polysilicon gate construction.Interlayer dielectric layer and first grid structure, second grid structure are equal.

Then, remove the first polysilicon gate construction and the second polysilicon gate construction, first grid texture grooves and second grid texture grooves is formed in interlayer dielectric layer, afterwards, in first grid texture grooves, form the first metal gate structure, in second grid texture grooves, form the second metal gate structure.

Certainly, in other embodiments, do not form the first metal gate structure and the second metal gate structure, first grid structure and second grid structure are all that polysilicon gate construction also belongs to protection scope of the present invention.

Then, interlayer dielectric layer is formed patterned 4th mask layer, with patterned 4th mask layer for mask to the first barrier material layer and under fin etch, in described first barrier material layer, form at least the first through hole, and in fin, form drain recesses and pseudo-drain recesses.At this moment, remaining first barrier material layer is the first barrier layer being positioned at drain recesses both sides.To the second barrier material layer and under Semiconductor substrate etch, form the second through hole at described first metal gate structure away from the second barrier material layer of side, drift region, and in fin, form the first source electrode groove.Also form the second through hole at described second metal gate structure away from the second barrier material layer of side, drift region, and in fin, form the second source electrode groove.At this moment, the second barrier layer being positioned at the first source electrode groove both sides and the second barrier layer being positioned at the second source electrode groove both sides also just define.

Then, side wall is formed respectively at least one first through-hole side wall described, the second through-hole side wall.

Then, corresponding formation drain material layer and pseudo-drain material layer in described drain recesses, pseudo-drain recesses.The first source electrode material layer is formed in the first source electrode groove.The second source electrode material layer is formed in the second source electrode groove.

Certainly, in other embodiments, the second barrier material layer not forming the 5th dummy gate structure side also belongs to protection scope of the present invention.

Certainly, in other embodiments, the second barrier material layer not forming the 6th dummy gate structure side also belongs to protection scope of the present invention.

Certainly, in other embodiments, do not form the second barrier material layer and belong to protection scope of the present invention yet.

Certainly, in other embodiments, do not form the first barrier material layer and belong to protection scope of the present invention yet.

Embodiment two

With reference to Figure 12, the present invention also provides a kind of LDMOS transistor structure, and two adjacent ldmos transistors share a drain electrode.Specifically comprise: semiconductor lining 20, described Semiconductor substrate 20 has fin 201; Also cover first grid structure 21 and the second grid structure 22 of described fin 201 top and sidewall respectively across described fin 201, first grid structure 21 and second grid structure 22 cover top and the sidewall of described fin 201 respectively;

Be positioned at the first source electrode 251 and the drain electrode 264 of the Semiconductor substrate of described first grid structure 21 both sides, be positioned at the second source electrode 252 and the drain electrode 264 of the Semiconductor substrate of second grid structure 22 both sides, described drain electrode 264 is the common drain of two adjacent ldmos transistors;

Ldmos transistor in the present embodiment also comprises:

Drift region 203, the described fin 201 that described drift region is positioned at, described first grid structure 21 and second grid structure 22 respectively part cover described drift region 203, and described drain electrode 264 is positioned at described drift region 203.

Ldmos transistor in the present embodiment also comprises:

First barrier layer, barrier layer 231 to the first 236 is polysilicon gate construction, also covers described fin 201 top and sidewall respectively, on the drift region 203 between first grid structure 21 and second grid structure 22 across described fin 201.

Described ldmos transistor also comprises pseudo-drain electrode 261 to puppet drain electrode 263, and pseudo-drain electrode 265 to puppet drain electrode 267, in described drift region 203.Two adjacent the first barrier layers 233 and the first barrier layer 234 define position and the width of drain electrode 264, first barrier layer 231 and first grid structure 21 define pseudo-drain 261 position and width, first barrier layer 231 and the second barrier layer 232 define pseudo-drain 262 position and width, second barrier layer 232 and the 3rd barrier layer 233 define pseudo-drain 263 position and width, 4th barrier layer 234 and the 5th barrier layer 235 define pseudo-drain 265 position and width, 5th barrier layer 235 and the 6th barrier layer 236 define pseudo-drain 266 position and width, 6th barrier layer 236 and second grid structure 22 define pseudo-drain 267 position and width.

In other embodiments, described first barrier layer is at least one, described first grid structure and described the first barrier layer near first grid structure define the position and width that drain, or, near the position of the first barrier layer definition drain electrode of second grid structure and width described in described second grid domain.The position of remaining two described puppet drain electrodes of adjacent first barrier layer definition and width.

Described ldmos transistor also comprises the second barrier layer 241 and the second barrier layer 242, is polysilicon gate construction, also covers described fin 201 top and sidewall respectively across described fin 201.In the present embodiment, the second barrier layer 241 on the fin 201 of described first grid structure 21 away from side, described drift region 203, for defining position and the width of the first source electrode 251.Second barrier layer 242 on the fin of described second grid structure 22 away from side, described drift region 203, for defining position and the width of the second source electrode 252.

Wherein, first grid structure 21 and second grid structure 22 are polysilicon gate construction or metal gate structure.

Distance between two adjacent the first barrier layers is the first distance H1, and the distance between first grid structure 21 and second barrier layer 241 is second distance H2, and the distance between second grid structure 22 and another the second barrier layer 242 is the 3rd distance H3.Described first distance H1, second distance H2 and the 3rd distance H3 are for being more than or equal to 0.01 micron and being less than or equal to 0.2 micron.

Specifically please refer to embodiment one.

Embodiment three

With reference to Figure 13, the present embodiment provides a kind of formation method of ldmos transistor, being distinguished as of the present embodiment and embodiment one: embodiment one has two source electrodes, is respectively the first source electrode and the second source electrode.First source electrode and the second source electrode share a drain electrode.The ldmos transistor of the present embodiment only has a source electrode 35, and the drain electrode 364 in the present embodiment is not common drain.Source electrode 35 in the present embodiment and drain electrode 364 between only have a grid structure 31.Grid structure 31 part covers on drift region 303.Pseudo-drain electrode 361, pseudo-drain electrode 362, pseudo-drain electrode 363 and drain electrode 364 are all in drift region 303.In other embodiments, the number of pseudo-drain electrode is unrestricted or do not have pseudo-drain electrode all to belong to protection scope of the present invention.

Drift region forms the first barrier layer, barrier layer 331 to the first 334, for defining position and the width of drain electrode and each puppet drain electrode.Specific as follows: in described drift region 203.Two adjacent the first barrier layers 333 and the first barrier layer 334 define position and the width of drain electrode 364, first barrier layer 331 and first grid structure 31 define pseudo-drain 361 position and width, first barrier layer 331 and the second barrier layer 332 define pseudo-drain 362 position and width, the second barrier layer 332 and the 3rd barrier layer 333 define puppet drain 363 position and width.

Distance between the first adjacent barrier layer is the first distance.Distance between first barrier layer and first grid structure is also the first distance.Distance between first barrier layer and second grid structure is also the first distance.

The fin of grid structure away from side, drift region 303 forms the second barrier layer 34, define position and the width of source electrode together with grid structure 31.Distance between second barrier layer 34 and grid structure 31 is second distance.

First distance and second distance are for being more than or equal to 0.01 micron and being less than or equal to 0.2 micron.

Concrete formation method please refer to embodiment one.

Embodiment four

With reference to Figure 13, the present invention also provides a kind of ldmos transistor, comprising:

Semiconductor substrate, described Semiconductor substrate has fin 301;

Across the grid structure 31 of described fin 301, described grid structure 31 covers top and the sidewall of described fin 301; Be positioned at source electrode 35 and the drain electrode 364 of the Semiconductor substrate of described grid structure 31 both sides.

Ldmos transistor in the present embodiment also comprises:

Drift region 303, the described fin 301 that described drift region 303 is positioned at, described grid structure 31 part covers described drift region 303, and described drain electrode 364 is positioned at described drift region 303.

Ldmos transistor in the present embodiment also comprises the first barrier layer 331 to the 4th barrier layer 334, is also polysilicon gate construction, also covers described fin 301 top and sidewall respectively across described fin 301.Described first barrier layer 331 is all positioned on described drift region 303 to the 4th barrier layer 334.

Described ldmos transistor also comprises pseudo-drain electrode 361 to puppet drain electrode 363, in described drift region 203.Two adjacent the first barrier layers 333 and the first barrier layer 334 define position and the width of drain electrode 364, first barrier layer 331 and first grid structure 31 define pseudo-drain 361 position and width, first barrier layer 331 and the second barrier layer 332 define pseudo-drain 362 position and width, the second barrier layer 332 and the 3rd barrier layer 333 define puppet drain 363 position and width.

Ldmos transistor in the present embodiment also comprises the second barrier layer 34, is polysilicon gate construction, covers described fin 301 top and sidewall respectively across described fin 301.Described second barrier layer 34 is on the fin 301 of described grid structure away from side, described drift region.

Specifically can with reference to above-described embodiment.

Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.

Claims

1. a formation method for ldmos transistor, is characterized in that, comprising:

Drift region is formed in described fin;

2. form method as claimed in claim 1, it is characterized in that, described Semiconductor substrate also has well region, and described well region surrounds described drift region.

3. form method as claimed in claim 2, it is characterized in that, the injection type of described drift region is contrary with the injection type of described well region.

4. form method as claimed in claim 1, it is characterized in that, form the step of source electrode material layer and drain material layer in the fin of described grid structure both sides before, also comprise: formation side wall around described grid structure.

5. form method as claimed in claim 4, it is characterized in that, after surrounding's formation side wall of described grid structure, form the step of source electrode material layer and drain material layer in the fin of described grid structure both sides before, also comprise the following steps: to form the first barrier layer on described drift region, described first barrier layer is identical with described grid structure thickness, and described first barrier layer is for defining position and the width of drain electrode.

6. form method as claimed in claim 5, it is characterized in that, described first barrier layer is polysilicon gate construction.

7. form method as claimed in claim 5, it is characterized in that, after forming the first barrier layer, form the step of source electrode material layer and drain material layer in the fin of described grid structure both sides before, be also included in the step forming side wall around the first barrier layer.

8. form method as claimed in claim 5, it is characterized in that, form source electrode material layer and drain material layer in the fin of described grid structure both sides while, also form at least one pseudo-drain material layer, described pseudo-drain material layer is in described drift region;

While ion implantation is carried out to described source electrode material layer and drain material layer, ion implantation is carried out to described pseudo-drain material layer, form pseudo-drain electrode.

9. form method as claimed in claim 8, it is characterized in that, described first barrier layer is at least one, described grid structure and described the first barrier layer near grid structure define the position and width that drain, the position of remaining two described puppet drain electrodes of adjacent first barrier layer definition and width, or

Described first barrier layer is at least two, the position of two adjacent the first barrier layer definition drain electrodes and width, the position of the pseudo-drain electrode of remaining first barrier layer definition and width.

10. form method as claimed in claim 8, it is characterized in that, the formation method of described source electrode material layer, drain material layer and pseudo-drain material layer comprises:

With described side wall, the first barrier layer for mask etching fin, form source electrode groove, drain recesses and pseudo-drain recesses in fin, described drain recesses and described pseudo-drain recesses are in described drift region;

In described source electrode groove, drain recesses and pseudo-drain recesses, correspondence forms source electrode material layer, drain material layer and pseudo-drain material layer respectively.

11. form method as claimed in claim 10, it is characterized in that, when described transistor is PMOS transistor, described source electrode material layer, described drain material layer and described pseudo-drain material layer are germanium silicon layer; When described transistor is nmos pass transistor, described source electrode material layer, described drain material layer and described pseudo-drain material layer are silicon carbide layer.

12. formation methods as described in claim 1 or 5, it is characterized in that, form the step of source electrode material layer and drain material layer in the Semiconductor substrate of described grid structure both sides before, also comprise the following steps: to form the second barrier layer at grid structure away from the side of drift region, described second barrier layer is identical with described grid structure thickness, the position of described second barrier layer definition source electrode and width.

13. form method as claimed in claim 12, it is characterized in that, described second barrier layer is polysilicon gate construction, after forming the second barrier layer, form the step of source electrode material layer and drain material layer in the fin of described grid structure both sides before, be also included in the step forming side wall around the second barrier layer.

14. form method as claimed in claim 1, it is characterized in that, two described LOMOS transistor common drains or have drain electrode respectively.

15. form method as claimed in claim 1, it is characterized in that, before formation source electrode material layer and drain material layer, the second barrier material layer is formed away from the side of described drift region at described grid structure, or, the drift region of the opposite side of described grid structure is formed the first barrier material layer;

16. form method as claimed in claim 1, it is characterized in that, before formation source electrode material layer and drain material layer, form the second barrier material layer in the side of described grid structure away from described drift region and on the drift region of the opposite side of described grid structure, form the first barrier material layer;

Fin under first barrier material layer and described first barrier material layer is etched, at least one first through hole is formed in described first barrier material layer, in fin, form drain recesses and dummy grid groove, remaining first barrier material layer is the first barrier layer;

17. 1 kinds of ldmos transistors, comprising: Semiconductor substrate, and described Semiconductor substrate has fin;

Across the grid structure of described fin, described grid structure covers top and the sidewall of described fin; Be positioned at source electrode and the drain electrode of the Semiconductor substrate of described grid structure both sides;

It is characterized in that, also comprise:

18. ldmos transistors as claimed in claim 17, is characterized in that, also comprise: the first barrier layer, on described drift region, for defining position and the width of described drain electrode.

19. ldmos transistors as claimed in claim 18, it is characterized in that, described ldmos transistor also comprises pseudo-drain electrode, in described drift region, described first barrier layer is at least one, described grid structure and described the first barrier layer near grid structure define the position and width that drain, the position of remaining two described puppet drain electrodes of adjacent first barrier layer definition and width, or, described first barrier layer is at least two, the position of two adjacent the first barrier layer definition drain electrodes and width, the position of the pseudo-drain electrode of remaining first barrier layer definition and width.

20. ldmos transistors as claimed in claim 17, is characterized in that, also comprise:

Second barrier layer, in the side of described grid structure away from described drift region, for defining position and the width of described source electrode.