CN105528014B - A kind of control method of the SCR trigger pulse based on FPGA - Google Patents
A kind of control method of the SCR trigger pulse based on FPGA Download PDFInfo
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Abstract
The present invention relates to a kind of control methods of the SCR trigger pulse based on FPGA.The method includes：The mains signal rectification that will be received exports synchronizing signal；Synchronizing signal is sampled, rising edge signal and failing edge signal are obtained；Rising edge signal is detected, effective rising edge signal is obtained, failing edge signal is detected, obtains effective failing edge signal；Synchronizing signal is divided into the first odd number group signal and the first even number set signal according to effective rising edge signal；Synchronizing signal is divided into the second odd number group signal and the second even number set signal according to effective failing edge signal；Timing is carried out to a cycle of the first odd number group signal, the first even number set signal, the second odd number group signal, the second even number set signal respectively using reference clock signal, when timing result meets predetermined condition, exports trigger pulse enable signal；Silicon controlled trigger signal is exported according to trigger pulse enable signal.
Description
Technical Field
The invention relates to the field of electronic control, in particular to a control method of silicon controlled trigger pulse based on FPGA.
Background
The invention relates to the field of electronic control, and discloses a technology for generating a silicon controlled trigger pulse by using a microprocessor (CPU for short), wherein the technology is mature, but the performance of the CPU is influenced by developing a silicon controlled digital trigger by using the microprocessor, and when a synchronous signal is interrupted temporarily, if other interrupt programs with higher priority or the same priority are running at the same time, the position of the output pulse is possibly inaccurate. In addition, most of the methods developed by using the microprocessor adopt a synchronous signal at intervals, and a trigger pulse signal is output through PWM in a sampling time interval. However, if the ac mains signal is not stable at 50Hz but varies within a certain range around 50Hz, and the sync signal is not sampled for a long time, the output trigger pulse position will drift.
Disclosure of Invention
The invention aims to realize the output of the silicon controlled trigger pulse through the FPGA, and the system resource is not occupied, so that a CPU in the system can efficiently process other works. And when the alternating current signal of the commercial power is unstable, the position accuracy of the output silicon controlled rectifier trigger pulse can be ensured.
In a first aspect, an embodiment of the present invention provides a method for controlling a thyristor trigger pulse based on an FPGA, where the method includes:
rectifying the received commercial power alternating current signal and outputting a synchronous signal;
sampling the synchronous signal to obtain a rising edge signal and a falling edge signal of the synchronous signal; detecting the rising edge signal to obtain an effective rising edge signal, and detecting the falling edge signal to obtain an effective falling edge signal;
dividing the synchronization signal into a first odd group signal and a first even group signal according to the effective rising edge signal; dividing the synchronization signal into a second odd group signal and a second even group signal according to the effective falling edge signal;
timing one period of the first odd group signal by using a reference clock signal to obtain a first period signal cnt _ cycle 1; clocking the one period of the first even group of signals with the reference clock signal to obtain a second periodic signal cnt _ cycle 2;
timing one period of the second odd group signal by using the reference clock signal to obtain a first pulse signal cnt _ pulse 1; timing the one period of the second even group of signals by using the reference clock signal to obtain a second pulse signal cnt _ pulse 2;
when the first pulse signal and the second periodic signal satisfy the following condition:
cnt _ pulse1 ═ cnt _ cycle2 (2n-1)/4, where n is 1 or 2;
or, when the second pulse signal and the first periodic signal satisfy the following condition:
cnt _ pulse2 ═ cnt _ cycle1 (2n-1)/4, where n is 1 or 2;
generating a trigger pulse enable signal;
and outputting a silicon controlled trigger signal according to the trigger pulse enabling signal.
Preferably, the detecting the rising edge signal to obtain an effective rising edge signal, and the detecting the falling edge signal to obtain an effective falling edge signal specifically includes:
when the time interval between a second rising edge signal and a first rising edge signal in the rising edge signals is larger than a first threshold value, determining the second rising edge signal as an effective rising edge signal;
and when the time interval between the first falling edge signal after the effective rising edge signal and the effective rising edge signal is larger than a second threshold value, determining the first falling edge signal as an effective falling edge signal.
Preferably, the method further comprises: and obtaining the cached delay value.
Further preferably, when the cnt _ pulse1 is cnt _ cycle2 (2n-1)/4 or the cnt _ pulse2 is cnt _ cycle1 (2n-1)/4, the generation of the trigger pulse enable signal is specifically:
when the cnt _ pulse1 is cnt _ cycle2 (2n-1)/4+ delay value, n is 1 or 2, or,
cnt _ pulse2 ═ cnt _ cycle1 — (2n-1)/4+ delay values, where n is 1 or 2,
generating the trigger pulse enable signal.
In a second aspect, the embodiment of the invention provides a system for controlling a thyristor trigger pulse based on an FPGA.
The system comprises: the synchronous signal generating circuit is used for rectifying the received commercial power alternating current signal and outputting a synchronous signal;
the synchronous signal edge generating module is used for sampling the synchronous signal to obtain a rising edge signal and a falling edge signal of the synchronous signal;
the synchronous signal edge detection module is used for detecting the rising edge signal to obtain an effective rising edge signal and detecting the falling edge signal to obtain an effective falling edge signal;
the reference clock signal generating module is used for generating a reference clock signal;
the processing module is used for dividing the synchronous signals into a first odd group signal and a first even group signal according to the effective rising edge signal; the processing module is further configured to divide the synchronization signal into a second odd group signal and a second even group signal according to the effective falling edge signal;
a synchronous signal period counter for timing a period of the first odd group signal by using the reference clock signal to obtain a first period signal cnt _ cycle 1; clocking the one period of the first even group of signals with the reference clock signal to obtain a second periodic signal cnt _ cycle 2;
a synchronous pulse counter, which uses the reference clock signal to time one cycle of the second odd group signal, so as to obtain a first pulse signal cnt _ pulse 1; timing the one period of the second even group of signals by using the reference clock signal to obtain a second pulse signal cnt _ pulse 2;
the enable signal generating module is configured to, when the first pulse signal and the second periodic signal satisfy the following condition:
cnt _ pulse1 ═ cnt _ cycle2 (2n-1)/4, where n is 1 or 2;
or, when the second pulse signal and the first periodic signal satisfy the following condition:
cnt _ pulse2 ═ cnt _ cycle1 (2n-1)/4, where n is 1 or 2;
generating a trigger pulse enable signal;
and the output pulse generation module is used for outputting a silicon controlled trigger signal according to the trigger pulse enable signal.
Preferably, the synchronization signal edge detection module is specifically configured to: when the synchronous signal edge detection module detects that the time interval between a second rising edge signal and a first rising edge signal in the rising edge signals is larger than a first threshold value, determining that the second rising edge signal is a valid rising edge signal;
and when the time interval between a first falling edge signal and the effective rising edge signal after the synchronous signal edge detection module detects the effective rising edge signal is greater than a second threshold value, determining that the first falling edge signal is an effective falling edge signal.
Preferably, the system further comprises: the counter starting module is used for starting a synchronous signal period counter when the effective rising edge signal is detected; when a valid falling edge signal is detected, a sync pulse counter is started.
Preferably, the system further comprises: and the delay value register is used for caching the delay value.
Further preferably, the enable signal generating module is specifically configured to:
when the cnt _ pulse1 is cnt _ cycle2 (2n-1)/4+ delay value, n is 1 or 2, or,
cnt _ pulse2 ═ cnt _ cycle1 — (2n-1)/4+ delay values, where n is 1 or 2,
generating the trigger pulse enable signal.
The invention provides a control method of silicon controlled trigger pulse based on FPGA, which is characterized in that firstly, commercial power alternating current signals are rectified to output synchronous signals, and the period of the synchronous signals is the same as that of the commercial power alternating current signals. And respectively timing one period of the odd group signal and the even group signal in the synchronous signal by using the reference clock signal according to the effective rising edge signal and the effective falling edge signal of the synchronous signal, and outputting the silicon controlled trigger signal when the timing result meets a preset condition. Therefore, the output position of the silicon controlled trigger signal is continuously changed along with the periodic change of the synchronous signal. Because the period of the synchronous signal is the same as that of the alternating current signal of the mains supply, namely when the period of the alternating current signal of the mains supply changes, the position of the output silicon controlled trigger signal also changes correspondingly.
Drawings
Fig. 1 is a flowchart of a method for controlling a thyristor trigger pulse based on an FPGA according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a control system for a thyristor trigger pulse based on an FPGA according to an embodiment of the present invention;
fig. 3 is a timing diagram of the ac signal of the utility power, the synchronization signal, and the trigger signal of the thyristor according to the embodiment of the present invention;
fig. 4 is a schematic diagram of a synchronization signal with glitches according to an embodiment of the present invention.
Detailed Description
The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.
Fig. 1 is a flowchart of a method for controlling a thyristor trigger pulse based on an FPGA in embodiment 1 of the present invention, and as shown in fig. 1, the embodiment of the present invention specifically includes the following steps:
step 101, rectifying a received commercial power alternating current signal and outputting a synchronous signal;
specifically, the commercial power ac signal is an ac signal with a frequency of about 50Hz, and after rectification, a synchronization signal is generated in a range corresponding to the positive half-wave, in this example, the synchronization signal is a square wave signal. The synchronization signal has the same period as the mains ac signal.
Step 102, sampling a synchronous signal to obtain a rising edge signal and a falling edge signal of the synchronous signal;
specifically, the sampling of the synchronization signal is to sample the synchronization signal by using a reference clock signal, and a rising edge signal and a falling edge signal of the synchronization signal are obtained by sampling.
The reference clock signal is: the reference clock signal generating module generates a clock signal.
103, detecting the rising edge signal to obtain an effective rising edge signal, and detecting the falling edge signal to obtain an effective falling edge signal;
specifically, when the time interval between a second rising edge signal and a first rising edge signal in two adjacent rising edge signals is greater than a first threshold, determining that the second rising edge signal is a valid rising edge signal;
and after the second rising edge is determined to be the effective rising edge signal, when the time interval between the first falling edge signal and the effective rising edge signal after the second rising edge is determined to be greater than a second threshold value, determining the first falling edge signal to be the effective falling edge signal.
In a specific example, as shown in fig. 4, the frequency of the ac mains signal is 50Hz, which may also vary within a certain range, so the period is about 20 ms. The distance between two valid rising edge signals of the synchronization signal is therefore around 20 ms. The effective high level of the synchronization signal is 0.5ms to 9.5ms, and it is assumed that the edge glitch to be filtered is a signal fluctuation in a range of 10us near the edge signal, so in fig. 4, when the time interval between the rising edge signal 4 and the rising edge signal 1 in the adjacent rising edge signal 1 and the rising edge signal 4 is detected to be greater than a first threshold value of 9.51ms (i.e., the time interval between the maximum value of the effective high level of 9.5ms + the filtering range of 10 us), it may be determined that the rising edge signal 4 is an effective rising edge signal; the rising edge signal 2 and the rising edge signal 3 are wave signals, and then the rising edge signal 2 and the rising edge signal 3 are filtered. When the rising edge signal 4 is detected to be a valid rising edge signal, the first falling edge signal 4 whose time interval with the valid rising edge signal 4 is greater than the second threshold value 0.1ms (the time interval of the filtering range of 10 us) can be determined as a valid falling edge signal, and whether the falling edge signal 1, the falling edge signal 2 and the falling edge signal 3 in fig. 4 are valid falling edge signals needs to be determined according to whether the rising edge signal 1 is a valid rising edge signal, and if the rising edge signal 1 is a valid rising edge signal, according to the above method, the falling edge signal 2 can be determined to be a valid falling edge signal, so as to filter the falling edge signal 1 and the falling edge signal 3.
Step 104, dividing the synchronous signals into a first odd group signal and a first even group signal according to the effective rising edge signal; dividing the synchronization signal into a second odd group signal and a second even group signal according to the effective falling edge signal;
specifically, the synchronization signals are divided according to the effective rising edge signals, and two synchronization signals of adjacent rising edges are divided into a first odd group signal and a first even group signal respectively; and dividing the synchronous signals according to the effective falling edge signals, and dividing the two synchronous signals of the adjacent falling edges into a second odd group signal and a second even group signal respectively.
Step 105, timing one cycle of the first odd group signal by using the reference clock signal to obtain a first cycle signal cnt _ cycle 1; timing one period of the first even group of signals by using a reference clock signal to obtain a second periodic signal cnt _ cycle 2;
specifically, one cycle of the first odd group signal is clocked according to the number of pulses output by the reference clock signal and the cycle of the reference clock signal, so as to obtain a first cycle signal cnt _ cycle 1.
And timing one period of the first even group of signals according to the number of pulses output by the reference clock signal and the period of the reference clock signal to obtain a second periodic signal cnt _ cycle 2.
Step 106, timing one period of the second odd group signal by using the reference clock signal to obtain a first pulse signal cnt _ pulse 1; timing one period of the second even group signal by using the reference clock signal to obtain a second pulse signal cnt _ pulse 2;
specifically, one cycle of the second odd group signal is clocked according to the number of pulses output by the reference clock signal and the cycle of the reference clock signal, so as to obtain the first pulse signal cnt _ pulse 1.
And timing one period of the second even group signal according to the number of pulses output by the reference clock signal and the period of the reference clock signal to obtain a second pulse signal cnt _ pulse 2.
Step 107, when the second odd group signal counting result is equal to one fourth or three fourths of the first even group signal counting result, or when the second even group signal counting result is equal to one fourth or three fourths of the first odd group signal counting result, generating a trigger pulse enable signal;
specifically, the above relationship can be formulated as:
cnt _ pulse1 ═ cnt _ cycle2 ═ (2n-1)/4, where n is 1 or 2; (formula 1)
Or
cnt _ pulse2 ═ cnt _ cycle1 ═ (2n-1)/4, where n is 1 or 2; (formula 2)
Optionally, if a delay value is preset externally, the relationship may be expressed as follows by obtaining the cached delay value based on the above formula 1 and formula 2 in consideration of the externally set delay:
cnt _ pulse1 ═ cnt _ cycle2 ═ 2n-1)/4+ delay values, where n is 1 or 2; (formula 3) or (b) in the presence of,
cnt _ pulse2 ═ cnt _ cycle1 ═ 2n-1)/4+ delay values, where n is 1 or 2; (formula 4)
A trigger pulse enable signal is generated.
And step 108, outputting a silicon controlled trigger signal according to the trigger pulse enabling signal.
Specifically, the generated trigger pulse enable signal is used as an excitation signal, and a silicon controlled trigger signal is output according to the excitation signal.
According to the control method of the silicon controlled trigger pulse based on the FPGA, firstly, a mains supply alternating current signal is rectified to output a synchronous signal, and the period of the synchronous signal is the same as that of the mains supply alternating current signal. And respectively timing one period of the odd group signal and the even group signal in the synchronous signal by using the reference clock signal according to the effective rising edge signal and the effective falling edge signal of the synchronous signal, and outputting the silicon controlled trigger signal when the timing result meets a preset condition. Therefore, the output position of the silicon controlled trigger signal is continuously changed along with the periodic change of the synchronous signal. Because the period of the synchronous signal is the same as that of the alternating current signal of the mains supply, namely when the period of the alternating current signal of the mains supply changes, the position of the output silicon controlled trigger signal also changes correspondingly. Therefore, when the alternating current signal of the mains supply is unstable, the position accuracy of the output silicon controlled rectifier trigger pulse can be ensured. And the output of the silicon controlled trigger pulse is realized through the FPGA, so that the system resource is not occupied, and a CPU in the system can efficiently process other works.
Fig. 2 is a schematic diagram of a control system for controlling a thyristor trigger pulse based on an FPGA in embodiment 2 of the present invention.
The system comprises: the synchronization signal generation circuit 201 is configured to rectify the received 220V ac signal and output a synchronization signal. A reference clock signal generation module 204, which is used for generating an external clock through a Phase Locked Loop (PLL) inside the FPGA, and the synchronization signal edge generation module 202 samples the synchronization signal through the reference clock signal generation module 204 to obtain a rising edge signal and a falling edge signal of the synchronization signal; the synchronization signal edge detection module 203 detects the rising edge signal to obtain a valid rising edge signal, and detects the falling edge signal to obtain a valid falling edge signal.
Specifically, when the synchronization signal edge detection module 203 detects that a time interval between a second rising edge signal that is later than the first rising edge signal and a first rising edge signal that is earlier than the second rising edge signal is greater than a first threshold, it is determined that the second rising edge signal is a valid rising edge signal;
when the time interval between the first falling edge signal and the valid rising edge signal after the synchronization signal edge detection module 203 detects the valid rising edge signal is greater than the second threshold, it is determined that the first falling edge signal is the valid falling signal.
In a specific example, the frequency of the ac mains signal is 50Hz, which may also vary within a certain range, so that the period is around 20 ms. The distance between two valid rising edge signals of the synchronization signal is therefore around 10 ms. The effective high level of the synchronization signal is 0.5ms to 9.5ms, and it is assumed that the edge glitch to be filtered is signal fluctuation in a range of 10us near the edge signal, so when the synchronization signal edge detection module 203 detects that a time interval between a second rising edge signal following and a first rising edge signal preceding in two adjacent rising edge signals is greater than a first threshold value of 9.51ms (i.e., a time interval of a maximum value of the effective high level of 9.5ms + a filtering range of 10 us), it may be determined that the second rising edge signal is an effective rising edge signal; when the synchronization signal edge detection module 203 detects that the second rising edge signal is a valid rising edge signal, the first falling edge signal whose time interval with the valid rising edge signal is greater than the second threshold 0.01ms (time interval of the filtering range 10 us) can be determined as a valid falling edge signal.
When the start counter module 205 detects a valid rising edge signal, then start the sync period counter 207; when the start counter module 205 detects a valid falling edge signal, then the sync pulse counter 208 is started;
optionally, the start counter module 205 is further configured to, when the effective falling edge signal is not detected within 80ms, enter the output pulse generating module 210, and output a normally high level to the thyristor, where the purpose is to output a high level to the thyristor trigger electrode when the detection module does not detect the effective synchronization signal within 4 periods, so that the thyristor is always kept in a conducting state.
A processing module 206, which divides the synchronization signal into a first odd group signal and a first even group signal according to the effective rising edge signal; the synchronization signal is divided into a second odd group signal and a second even group signal according to the active falling edge signal. The synchronizing signal period counter 207 clocks one period of the first odd group signal with the reference clock signal to obtain a first period signal cnt _ cycle 1; timing one period of the first even group of signals to obtain a second period signal cnt _ cycle 2;
the sync pulse counter 208 clocks one cycle of the second odd group signal with the reference clock signal to obtain a first pulse signal cnt _ pulse 1; timing one period of the second even group signal to obtain a second pulse signal cnt _ pulse 2;
the enabling signal generating module 209 is configured to, when the first pulse signal and the second periodic signal satisfy the following condition:
cnt _ pulse1 ═ cnt _ cycle2 ═ 2n-1)/4, n is 1 or 2 (formula 5)
Or, when the second pulse signal and the first period signal satisfy the following condition:
cnt _ pulse2 ═ cnt _ cycle1 ═ 2n-1)/4, n is 1 or 2 (formula 6)
Generating a trigger pulse enable signal;
a delay value register 211 for buffering delay values.
Alternatively, when a delay value is preset externally, the buffered delay value is obtained from the delay value register 211. Based on the above-described equations 5 and 6, in the case of considering the delay time,
cnt _ pulse1 ═ cnt _ cycle2 ═ 2n-1)/4+ delay value, n is 1 or 2 (formula 7)
Or,
cnt _ pulse2 ═ cnt _ cycle1 ═ 2n-1)/4+ delay value, n is 1 or 2 (formula 8)
A trigger pulse enable signal is generated.
The output pulse generating module 210 outputs a thyristor trigger signal according to the trigger pulse enable signal;
optionally, the output pulse generating module 210 is further configured to output a normally high level to the trigger electrode of the thyristor when the effective falling edge signal is not detected within 80ms, and the purpose of the output pulse generating module is also to output a high level to the trigger electrode of the thyristor when the effective synchronizing signal is not detected within 4 periods by the detecting module, so that the thyristor is always kept in a conducting state.
According to the control system of the silicon controlled trigger pulse based on the FPGA, the commercial power alternating current signal is rectified through the synchronous signal generating circuit to output the synchronous signal, and the period of the synchronous signal is the same as that of the commercial power alternating current signal. And a reference clock signal output by an external clock is utilized to respectively time one period of the odd group signal and the even group signal in the synchronous signal according to the effective rising edge signal and the effective falling edge signal, and when the timing result meets a preset condition, the trigger pulse generation module outputs the silicon controlled trigger signal. Therefore, the output position of the silicon controlled trigger signal is continuously changed along with the periodic change of the synchronous signal. Because the period of the synchronous signal is the same as that of the alternating current signal of the mains supply, namely when the period of the alternating current signal of the mains supply changes, the position of the output silicon controlled trigger signal also changes correspondingly. Therefore, when the alternating current signal of the mains supply is unstable, the position accuracy of the output silicon controlled rectifier trigger pulse can be ensured. The output of the silicon controlled trigger pulse is realized through the FPGA, the resources of the system are not occupied, and a CPU in the system can efficiently process other works.
Fig. 3 is a timing chart of the commercial power ac signal, the synchronization signal, and the thyristor trigger signal provided in embodiment 3 of the present invention;
as shown in fig. 3, the frequency of the ac mains signal is 50Hz, and the period is about 20 ms. The synchronization signal is obtained by sampling the ac signal of the utility power, and in this embodiment, the synchronization signal is a square wave. The period of the synchronous signal is the same as that of the alternating current signal of the mains supply. The high effective level of the synchronous signal is 0.5 ms-9.5 ms, so that the high effective level of the synchronous signal appears in the positive half-wave range of the commercial power alternating current signal. Dividing the synchronization signal into a first odd group signal and a first even group signal according to the effective rising edge signal; the synchronization signal is divided into a second odd group signal and a second even group signal according to the active falling edge signal. The synchronous signal period counter utilizes the reference clock signal to time one period of the first odd group signal to obtain a first period signal cnt _ cycle 1; timing one period of the first even group of signals to obtain a second period signal cnt _ cycle 2; the synchronous pulse counter utilizes the reference clock signal to time one period of the second odd group signal to obtain a first pulse signal cnt _ pulse 1; timing one period of the second even group signal to obtain a second pulse signal cnt _ pulse 2; when the cnt _ pulse1 is cnt _ cycle2 (2n-1)/4, n is 1 or 2, or cnt _ pulse2 is cnt _ cycle1 (2n-1)/4, n is 1 or 2, (if a delay value is preset externally, when the cnt _ pulse1 is cnt _ cycle2 (2n-1)/4+ delay value is satisfied, n is 1 or 2, or cnt _ pulse2 is cnt _ cycle1 (2n-1)/4+ delay value, n is 1 or 2), the output pulse generation module outputs the thyristor trigger signal shown in fig. 3 according to the trigger pulse enable signal.
The timing diagram of the ac mains signal, the synchronization signal, and the trigger signal of the thyristor provided in this embodiment is obtained by rectifying the ac mains signal through the synchronization signal generating circuit to output the synchronization signal, where the period of the synchronization signal is the same as that of the ac mains signal. And respectively timing one period of the odd group signal and the even group signal in the synchronous signal according to the effective rising edge signal and the effective falling edge signal, and outputting the silicon controlled trigger signal by the trigger pulse generation module when the timing result meets a preset condition. Therefore, the output position of the silicon controlled trigger signal is continuously changed along with the periodic change of the synchronous signal. Because the period of the synchronous signal is the same as that of the alternating current signal of the mains supply, namely when the period of the alternating current signal of the mains supply changes, the position of the output silicon controlled trigger signal also changes correspondingly. Therefore, when the alternating current signal of the mains supply is unstable, the position accuracy of the output silicon controlled rectifier trigger pulse can be ensured.
Those of skill would further appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied in hardware, a software module executed by a processor, or a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (9)
1. A control method of silicon controlled trigger pulse based on FPGA is characterized by comprising the following steps:
rectifying the received commercial power alternating current signal and outputting a synchronous signal;
sampling the synchronous signal to obtain a rising edge signal and a falling edge signal of the synchronous signal; detecting the rising edge signal to obtain an effective rising edge signal, and detecting the falling edge signal to obtain an effective falling edge signal;
dividing the synchronization signal into a first odd group signal and a first even group signal according to the effective rising edge signal; dividing the synchronization signal into a second odd group signal and a second even group signal according to the effective falling edge signal;
timing one period of the first odd group signal by using a reference clock signal to obtain a first period signal cnt _ cycle 1; clocking the one period of the first even group of signals with the reference clock signal to obtain a second periodic signal cnt _ cycle 2;
timing one period of the second odd group signal by using the reference clock signal to obtain a first pulse signal cnt _ pulse 1; timing the one period of the second even group of signals by using the reference clock signal to obtain a second pulse signal cnt _ pulse 2;
when the first pulse signal and the second periodic signal satisfy the following condition:
cnt _ pulse1 ═ cnt _ cycle2 (2n-1)/4, where n is 1 or 2;
or, when the second pulse signal and the first periodic signal satisfy the following condition:
cnt _ pulse2 ═ cnt _ cycle1 (2n-1)/4, where n is 1 or 2;
generating a trigger pulse enable signal;
and outputting a silicon controlled trigger signal according to the trigger pulse enabling signal.
2. The method according to claim 1, wherein the detecting the rising edge signal to obtain a valid rising edge signal and the detecting the falling edge signal to obtain a valid falling edge signal are specifically:
when the time interval between a second rising edge signal and a first rising edge signal in the rising edge signals is larger than a first threshold value, determining the second rising edge signal as an effective rising edge signal;
and when the time interval between the first falling edge signal after the effective rising edge signal and the effective rising edge signal is larger than a second threshold value, determining the first falling edge signal as an effective falling edge signal.
3. The method of claim 1, further comprising: and obtaining the cached delay value.
4. The method of claim 3, wherein the first pulse signal and the second periodic signal satisfy the following condition:
cnt _ pulse1 ═ cnt _ cycle2 ═ 2n-1)/4+ delay values, where n is 1 or 2;
or, when the second pulse signal and the first periodic signal satisfy the following condition:
cnt _ pulse2 ═ cnt _ cycle1 ═ 2n-1)/4+ delay values, where n is 1 or 2; generating a trigger pulse enable signal;
and outputting a silicon controlled trigger signal according to the trigger pulse enabling signal.
5. The control system of the silicon controlled rectifier trigger pulse based on the FPGA is characterized by comprising the following components:
the synchronous signal generating circuit is used for rectifying the received commercial power alternating current signal and outputting a synchronous signal;
the synchronous signal edge generating module is used for sampling the synchronous signal to obtain a rising edge signal and a falling edge signal of the synchronous signal;
the synchronous signal edge detection module is used for detecting the rising edge signal to obtain an effective rising edge signal and detecting the falling edge signal to obtain an effective falling edge signal;
the reference clock signal generating module is used for generating a reference clock signal;
the processing module is used for dividing the synchronous signals into a first odd group signal and a first even group signal according to the effective rising edge signal; the processing module is further configured to divide the synchronization signal into a second odd group signal and a second even group signal according to the effective falling edge signal;
a synchronous signal period counter for timing a period of the first odd group signal by using the reference clock signal to obtain a first period signal cnt _ cycle 1; clocking the one period of the first even group of signals with the reference clock signal to obtain a second periodic signal cnt _ cycle 2;
a synchronous pulse counter, which uses the reference clock signal to time one cycle of the second odd group signal, so as to obtain a first pulse signal cnt _ pulse 1; timing the one period of the second even group of signals by using the reference clock signal to obtain a second pulse signal cnt _ pulse 2;
the enable signal generating module is configured to, when the first pulse signal and the second periodic signal satisfy the following condition:
cnt _ pulse1 ═ cnt _ cycle2 (2n-1)/4, where n is 1 or 2;
or, when the second pulse signal and the first periodic signal satisfy the following condition:
cnt _ pulse2 ═ cnt _ cycle1 (2n-1)/4, where n is 1 or 2;
generating a trigger pulse enable signal;
and the output pulse generation module is used for outputting a silicon controlled trigger signal according to the trigger pulse enable signal.
6. The system of claim 5, wherein the synchronization signal edge detection module is specifically configured to:
when the synchronous signal edge detection module detects that the time interval between a second rising edge signal and a first rising edge signal in the rising edge signals is larger than a first threshold value, determining that the second rising edge signal is a valid rising edge signal;
and when the time interval between a first falling edge signal and the effective rising edge signal after the synchronous signal edge detection module detects the effective rising edge signal is greater than a second threshold value, determining that the first falling edge signal is an effective falling edge signal.
7. The system of claim 5, further comprising: the counter starting module is used for starting a synchronous signal period counter when the effective rising edge signal is detected; when a valid falling edge signal is detected, a sync pulse counter is started.
8. The system of claim 5, further comprising: and the delay value register is used for caching the delay value.
9. The system of claim 8, wherein the enable signal generation module is specifically configured to: when the cnt _ pulse1 is cnt _ cycle2 (2n-1)/4+ delay value, n is 1 or 2, or,
cnt _ pulse2 ═ cnt _ cycle1 — (2n-1)/4+ delay values, where n is 1 or 2,
generating the trigger pulse enable signal.
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