CN105514262A - Crossing matrix array magnetic random memory manufacturing process - Google Patents

Crossing matrix array magnetic random memory manufacturing process Download PDF

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Publication number
CN105514262A
CN105514262A CN201510726489.5A CN201510726489A CN105514262A CN 105514262 A CN105514262 A CN 105514262A CN 201510726489 A CN201510726489 A CN 201510726489A CN 105514262 A CN105514262 A CN 105514262A
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conductive layer
layer
manufacturing process
magnetic memory
decker
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肖荣福
郭一民
陈峻
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Shanghai Ciyu Information Technologies Co Ltd
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Shanghai Ciyu Information Technologies Co Ltd
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00Galvanomagnetic devices
    • H10N50/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B61/00Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/10Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having two electrodes, e.g. diodes or MIM elements

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Hall/Mr Elements (AREA)
  • Mram Or Spin Memory Techniques (AREA)

Abstract

The invention provides a crossing matrix array magnetic random memory manufacturing process, and the processor comprises the steps: forming a bottom electrode; forming a magnetic memory unit array at the top of the bottom electrode: manufacturing a multilayer film and forming a tandem magnetic tunnel junction and a three-layer (conductive layer 1/semiconductor/conductive layer 1) structure; and forming a top electrode at the top of the magnetic memory unit array. A crossing matrix array magnetic random memory manufactured through the manufacturing process employs the three-layer (conductive layer 1/semiconductor/conductive layer 1) structure to replace a triode as a current flow direction selector in a magnetic memory unit, and achieves the change of a complex power supply network into a simple crossing power supply mode. The manufacturing process greatly simplifies the production technology of MRAMs, reduces the cost, and can greatly improve the integration of a storage chip, especially for a pSTT-MRAM product.

Description

Cross matrix column magnetic RAM manufacturing process
Technical field
The present invention relates to memory device field, particularly relate to a kind of cross matrix column magnetic RAM manufacturing process.
Background technology
People utilize the characteristic of MTJ (MTJ, MagneticTunnelJunction) to make magnetic RAM in recent years, are MRAM (MagneticRandomAccessMemory).MRAM is a kind of New Solid nonvolatile memory, and it has the characteristic of high-speed read-write.Ferromagnetism MTJ is generally sandwich structure, and be wherein magnetic memory layer, and it can change the direction of magnetization to record different data; Be positioned at the tunnel barrier layer of middle insulation; Magnetic reference layer, is positioned at the opposite side of tunnel barrier layer, and its direction of magnetization is constant.When Magnetic memory layer is parallel with the magnetization intensity vector direction between magnetic reference layer or antiparallel time, the Resistance states of MTJ element is also corresponding is respectively low resistance state or high-impedance state.The Resistance states of such measurement MTJ element can obtain the information stored.
A kind of existing method can obtain high magneto-resistor (MR, MagnetoResistance) rate: accelerate crystallization on the surface of the magnetic film of non crystalline structure and form one deck crystallization acceleration film.After this tunic is formed, crystallization starts to be formed from tunnel barrier layer side, makes the surface of tunnel barrier layer be formed with magnetic surface like this and mates, so just can obtain high MR and lead.
Generally by different write operation methods, MRAM device is classified.Traditional MRAM is magnetic field switch type MRAM: produce magnetic field in the intersection of two current line of intersecting, can change the magnetization direction of the Magnetic memory layer of MTJ element.Spin-transfer torque magnetic RAM (STT-MRAM, Spin-transferTorqueMagneticRandomAccessMemory) diverse write operation is then adopted, its utilize be electronics spin angular momentaum transfer, i.e. the electron stream of spin polarization is transferred to its angular momentum the magnetic material in Magnetic memory layer.The capacity of Magnetic memory layer is less, needs the spin polarized current carrying out write operation also less.Institute in this way can meet device miniaturization and low current density simultaneously.STT-MRAM has the characteristic of high-speed read-write, Large Copacity, low-power consumption, potential in electronic chip industry, especially in moving chip industry, substitutes traditional semiconductor memory to realize the non-volatile of energy conservation and data.
For current face inner mold STT-MRAM (wherein the direction of easy axis of MTJ element is in face), characteristic by face inner mold MTJ element limit, single component size is general comparatively large, and adjacent MTJ element needs comparatively Large space, to avoid mutual magnetic interference.Therefore, the lifting of face inner mold STT-MRAM product integrated level is limited.
Vertical-type MTJ (PMTJ, PerpendicularMagneticTunnelJunction) namely magnetic moment perpendicular to the MTJ of substrate surface, in such an embodiment, due to two magnetospheric magnetocrystalline anisotropy stronger (not considering shape anisotropy), make its direction of easy axis all perpendicular to layer surface.Under identical condition, component size can be done specific surface inner mold MTJ element is less, and it is very little that the magnetic polarization error of direction of easy axis can be done, and the reduction of MTJ component size makes required switch current also can correspondingly reduce.On the other hand, in memory arrays, the safe spacing of neighboring vertical type MTJ also can greatly reduce than face inner mold MTJ.Thus vertical-type STT-MRAM (pSTT-MRAM, perpendicularSpin-transferTorqueMagneticRandomAccessMemo ry) is than face inner mold STT-MRAM, its integrated level has very large room for promotion.
But in existing STT-MRAM structure; the MTJ element of each mnemon can connect a triode usually as current direction selector; as used metal-oxide-semiconductor; by the conducting of metal-oxide-semiconductor and cut-off to realize conduct current; thus the high resistance and low resistance state of MTJ element can be set by corresponding write current; also be namely written with storage information, and judge the Resistance states of MTJ element according to the size of read current, also namely read storage information.
For face inner mold STT-MRAM, based on the size of face inner mold MTJ element and the requirement of mutual spacing thereof, the size of triode is not the Main Bottleneck of raising face inner mold STT-MRAM integrated level, reduces the size of triode in other words, for the lifting limitation of face inner mold STT-MRAM integrated level.And it is on the contrary for vertical-type STT-MRAM situation, the size of vertical-type MTJ element and mutual spacing thereof greatly reduce than face inner mold MTJ element, the size of triode is almost depended in the now lifting of integrated level completely, even if use current state-of-the-art technique (live width), the size of triode is still much larger than vertical-type MTJ element, triode manufacturing process relatively also more complicated, improves the manufacturing cost of product simultaneously.
Therefore, those skilled in the art is devoted to the STT-MRAM manufacturing process developing a kind of high integrated, high-performance, cost savings.
Summary of the invention
For achieving the above object, the invention provides a kind of magnetic RAM manufacturing process, comprising:
Form hearth electrode;
Forming Magnetic Memory cell array at described hearth electrode top, forming the MTJ and conductive layer 1/ semi-conductor/conducting layer 2 three-decker of connecting comprising preparing plural layers; Described herein " top " or " top " represents the side away from substrate base in corresponding construction;
Top electrode is formed at described Magnetic Memory cell array top.
Further, the formation of described hearth electrode comprises:
Depositions of bottom electrode metal level and hard mask one;
Photoetching hearth electrode;
Etching hearth electrode;
Deposit dielectrics one;
Surface planarisation.
Further, the formation of described Magnetic Memory cell array comprises:
The film of described conductive layer 1/ semi-conductor/conducting layer 2 three-decker and described MTJ is formed in the preparation of described hearth electrode top, wherein first preparation forms the film of the film MTJ described in sedimentary composition again of described conductive layer 1/ semi-conductor/conducting layer 2 three-decker, or the film of MTJ described in first sedimentary composition prepares the film forming described conductive layer 1/ semi-conductor/conducting layer 2 three-decker again;
Deposit hard mask two;
Photoetching Magnetic Memory cell array;
Etching Magnetic Memory cell array;
Deposit dielectrics two;
Surface planarisation.
Further, the formation of described top electrode comprises:
At described Magnetic Memory cell array deposited atop top electrode metal level and hard mask three;
Photoetching top electrode;
Etching top electrode;
Deposit dielectrics three;
Surface planarisation.
Further, described MTJ comprises the magnetic reference layer of stacked setting, tunnel barrier layer and Magnetic memory layer.From the bottom to top, can be magnetic reference layer, tunnel barrier layer and Magnetic memory layer successively, also can be Magnetic memory layer, tunnel barrier layer and magnetic reference layer successively.The relative position of "up" and "down" described herein, " on " comparatively in D score further from substrate base.
Further, the semiconductor of described conductive layer 1/ semi-conductor/conducting layer 2 three-decker comprises P type semiconductor or N type semiconductor.Semiconductor substrate can adopt Si, Ge, SiGe or SiC, and wherein N type semiconductor is formed by doping V valency element (as As, P etc.), and P type semiconductor is formed by doped with II I valency element (as B etc.); Also can adopt GaAs or InP, wherein N type semiconductor is formed by doping VI valency element (as Se, Te etc.), and P type semiconductor is formed by doped with II valency element (as Be etc.).
Further, the conductive layer 1 of described conductive layer 1/ semi-conductor/conducting layer 2 three-decker and/or conductive layer 2 comprise Pt, Au, Rd, Ir, Ru, Pd, Ag, Mo, Cr, W, Ti, Ta or CuAl.
Further; the conductive layer 1 of described conductive layer 1/ semi-conductor/conducting layer 2 three-decker and conductive layer 2 comprise the diffusion barrier be disposed adjacent with the semiconductor of described conductive layer 1/ semi-conductor/conducting layer 2 three-decker respectively, to stop that the impurity in described P type semiconductor or N type semiconductor spreads in described conductive layer 1 and conductive layer 2.
Further, described top electrode and/or described hearth electrode comprise metal level Cu; Or comprise sandwich construction TaN/Ta/Cu/Ta/TaN or TiN/Ti/Cu/Ti/TiN, wherein TaN/Ta or TiN/Ti at Cu top is as hard mask.
Further, described hearth electrode defines some first guiding lines, described top electrode defines some second guiding lines arranged in a crossed manner with described some first guiding lines, thus described some first guiding lines and described some second guiding lines define some crossover nodes; Each described crossover node is provided with a Magnetic Memory unit, and described Magnetic Memory unit is electrically connected with first guiding line at crossover node place residing for it and the second guiding line respectively.
Cross matrix column magnetic RAM obtained by the present invention, conductive layer 1/ semi-conductor/conducting layer 2 three-decker is utilized to substitute triode as the current direction selector in Magnetic Memory unit, achieve and use the power supply network of complexity instead simple staggered form supply power mode, thus the present invention greatly simplify MRAM production technology, reduce cost, and greatly can improve the integrated level of storage chip, particularly for pSTT-MRAM product.
Be described further below with reference to the technique effect of accompanying drawing to design of the present invention, concrete structure and generation, to understand object of the present invention, characteristic sum effect fully.
Accompanying drawing explanation
Fig. 1 is the process chart of preferred embodiment of the present invention;
Fig. 2 is the post-depositional structural representation of hearth electrode metal level;
Fig. 3 is the structural representation after photoetching hearth electrode;
Fig. 4 is the structural representation after prepared by hearth electrode;
Fig. 5 is the end face schematic diagram of Fig. 4 structure;
Fig. 6 is the structural representation after conductive layer/semi-conductor/conducting layer three-decker thin film deposition;
Fig. 7 is the structural representation after MTJ thin film deposition;
Fig. 8 is the structural representation after photoetching Magnetic Memory cell array;
Fig. 9 is the structural representation after etching Magnetic Memory cell array;
Figure 10 is the structural representation after prepared by Magnetic Memory cell array;
Figure 11 is the end face schematic diagram of Figure 10 structure;
Figure 12 is the structural representation after prepared by top electrode;
Figure 13 is the end face schematic diagram of Figure 12 structure;
Figure 14 is the structural representation first processing MTJ film reprocessing conductive layer/semi-conductor/conducting layer three-decker film;
Figure 15 be a kind of cross matrix column random asccess memory perspective view.
Embodiment
In the description of embodiments of the present invention, it will be appreciated that, term " on ", D score, " front ", " afterwards ", " left side ", " right side ", " vertically ", " level ", " top ", " end " " interior ", " outward ", " clockwise ", orientation or the position relationship of the instruction such as " counterclockwise " are based on orientation shown in the drawings or position relationship, only the present invention for convenience of description and simplified characterization, instead of indicate or imply that the device of indication or element must have specific orientation, with specific azimuth configuration and operation, therefore limitation of the present invention can not be interpreted as.
Fig. 1 is the magnetic RAM preparation technology flow chart of the present embodiment, and concrete technology flow process is as follows:
1, depositions of bottom electrode conductive layer and hard mask
By physical vapour deposition (PVD) (PVD, PhysicalVaporDeposition) on substrate base 100, as physical sputtering, form Cu film 210, and as the Ta film 220 of hard mask (hardmask), as shown in Figure 2.In order to prevent the electron transfer of Cu, preferably with TaN/Ta and Ta/TaN, Cu film 210 is surrounded (not shown) respectively in the both sides up and down of Cu film 210, namely the sandwich construction of TaN/Ta/Cu/Ta/TaN is adopted, wherein the material layer on the "/" left side is arranged on the material layer of the right, and Ta also can substitute with Ti, namely adopts the sandwich construction of TiN/Ti/Cu/Ti/TiN.In above-mentioned sandwich construction, TaN/Ta or TiN/Ti of top layer can as hard mask.
2, photoetching hearth electrode
Coating photoresist 250 also photoetching forms hearth electrode pattern, as shown in Figure 3.
3, hearth electrode is etched
By etching, Cu film 220 and Ta film 230 form hearth electrode pattern.
4, deposit dielectrics, surface planarisation
By chemical vapour deposition (CVD) (CVD, ChemicalVaporDeposition), as PCVD (PECVD, PlasmaEnhancedChemicalVaporDeposition) SiO 2the groove that film 260 is formed after filling etching, and carry out planarization, as adopted cmp (CMP, ChemicalMechanicalPolishing), thus form structure shown in Fig. 4 (cutaway view) and Fig. 5 (vertical view).
5, depositing conducting layer/semi-conductor/conducting layer three-decker film
As shown in Figure 6, conductive layer 310, semiconductor 320 and conductive layer 330 is prepared successively.Wherein, conductive layer 310 and conductive layer 330 can adopt Pt metal, Au, Rd, Ir, Ru, Pd, Ag, Mo, Cr, W, Ti, Ta or CuAl etc., are formed by PVD.
Semiconductor 320 forms (for Si base material) by following two kinds of methods:
(1) PVD method, use Si target, Ar is sputter gas, growth one deck amorphous silicon (a-Si) film, N type semiconductor is become by doping V valency element (as As, P etc.) after completing, or by doped with II I valency element (as B etc.), become P type semiconductor.Wherein doping process the target directly in thin film growth process can add doped chemical, also can be realized by the way of ion beam mutation.Then carry out high temperature (500 DEG C ~ 800 DEG C) annealing, changed into monocrystalline or be at least polycrystal layer, and eliminate growth defect wherein, and repair due to the various defects caused of adulterating.
(2) CVD method, with the gas containing silicon (as SiH 4), directly generate monocrystalline by high-temperature chemical reaction or be at least polysilicon membrane.Also can make film containing hydrionic amorphous silicon (Si:H) by the method for PECVD, hydrogen ion wherein can eliminate those Si keys (danglingbonds) do not matched, and then carries out high annealing, eliminates defect.In growth course, the gas containing doped chemical can be added, directly Si film is made N-type or P type semiconductor, or be adulterated by the method for ion beam mutation, again by high temperature (500 DEG C ~ 800 DEG C) annealing, form the base semiconductor of at least polycrystalline form.
Certainly, in above two kinds of methods, also can not adulterate, and use intrinsic semiconductor.
Preferably; when semiconductor 320 be P type or N type semiconductor time; a diffusion barrier (not shown) can also be deposited respectively between semiconductor 320 and its upper and lower conductive layers 330,310; as used TiN, TaN etc., to stop diffusion in the impurity conductive layer 330,310 in P type semiconductor or N type semiconductor.
6, MTJ film is deposited
After above-mentioned technique completes, then generate MTJ by PVD deposition.In order to grow high-quality MTJ multilayer film, the smoothness of substrate surface is extremely important, and in general, surface roughness preferably controls within 2 dusts.For this purpose, first carry out cmp planarization, and then carry out the growth of MTJ multilayer film.Specifically deposited seed layer 410 (as Ta, NiCr etc.), magnetic reference layer 420, tunnel barrier layer 430, Magnetic memory layer 440 and hard mask layer 450 (as Ta etc.) successively, as shown in Figure 7.Certain magnetic reference layer 420, tunnel barrier layer 430 and Magnetic memory layer 440 can stack gradually described above from the bottom to top, also can from the bottom to top successively deposited magnetic memory layer, tunnel barrier layer and magnetic reference layer.
7, photoetching Magnetic Memory cell array
Then photoresist 460 is coated with and photoetching formation Magnetic Memory unit array patterns, as shown in Figure 8.
8, Magnetic Memory cell array is etched
Etched by special magnetic material, form the Magnetic Memory unit of some columns, each Magnetic Memory unit all has the MTJ and conductive layer/semi-conductor/conducting layer three-decker that are connected in series.
Because MT reconnaissance J multilayer film relates to multiple transition metals, wherein a kind of method etches by reactive ion etching (RIE, ReactiveIonEtch) method.Specifically first etch hard mask with the etching gas of CF4 and so on, and then etch, until be finally parked in bottom electrode layer with methyl alcohol (CH3OH) or CO+NH3 gas.In etching process, the edge 480 or destroyed of Magnetic Memory unit, thus lose their original physical characteristics, as shown in Figure 9.In order to remove impaired edge 480, once gentle etching processing can be carried out with ion beam, it is all removed.All with the whole multilayer film of ion beam etching, then can certainly use PECVD, grow edge-protected by each Magnetic Memory unit of one deck silicon nitride (SiN) film at once.
9, deposit dielectrics, surface planarisation
The groove formed after filling etching by PECVDSiO2 film 360 again, and carry out planarization with CMP effects on surface, namely form the structure as shown in Figure 10 (profile) and Figure 11 (vertical view).
10, top electrode conductive layer and hard mask is deposited
To prepare hearth electrode similar, form Cu film 510, as the electric conducting material preparing top electrode by PVD.Similarly, in order to prevent the electron transfer of Cu, preferably with TaN/Ta and Ta/TaN, Cu film 510 is surrounded (not shown) respectively in the both sides up and down of Cu film 510, namely the sandwich construction of TaN/Ta/Cu/Ta/TaN is adopted, and Ta also can substitute with Ti, namely adopts the sandwich construction of TiN/Ti/Cu/Ti/TiN.In above-mentioned sandwich construction, TaN/Ta or TiN/Ti of top layer can as hard mask.
11, photoetching top electrode, with photoetching hearth electrode resemble process.
12, top electrode is etched, with etching hearth electrode resemble process.
13, deposit dielectrics, surface planarisation
The groove formed after filling etching by PECVDSiO2 film, and carry out planarization with CMP effects on surface, namely form the structure as shown in Figure 12 (profile) and Figure 13 (vertical view).
The preparation order of conductive layer in above-mentioned technological process/semi-conductor/conducting layer three-decker film and MTJ film also can be put upside down, and namely first processes MTJ film reprocessing conductive layer/semi-conductor/conducting layer three-decker film, as shown in figure 14.
In addition, in above technological process, a photoetching is adopted directly to form Magnetic Memory unit, Twi-lithography can certainly be adopted to be formed, for above-mentioned technique, wherein can first do a photoetching, etching, SiO2 filling and planarization after completing in conductive layer/semi-conductor/conducting layer three-decker film preparation, carry out the deposition of MTJ film again, and corresponding photoetching (using identical mask plate with previous photoetching), etch, SiO2 fills and planarization, thus the Magnetic Memory cell array that formation is identical with said structure.
As shown in figure 13, hearth electrode comprises some Vertical dimension wires, as illustrated in the drawing wire 211,212,213, and top electrode comprises some horizontal guiding lines, as illustrated in the drawing wire 511,512.Wire 211,212,213 and wire 511,512 have intersected to form 6 crossover nodes mutually; Each crossover node is provided with a Magnetic Memory unit, thus define a kind of cross matrix column MRAM, Figure 15 show cross matrix column random asccess memory perspective view.
In addition, have in the storage array of M × N number of storage element (M+N>>1) at one, i.e. M bit lines and N bar wordline, as the low resistance of current direction selector and high resistance are respectively R land R h, so: must much smaller than 1; Thus need meet: R H R L > > M × N M + N .
Along with the increase of mnemon quantity (M, N), R h/ R lratio also need more and more higher, even need both difference several order of magnitude.Therefore, for how preventing unnecessary drain (leakage current) from being very important.These leakage currents not only can consume a large amount of energy, and can produce heat, affect the normal work of mnemonic.
The shortcoming of Schottky diode is that it has a larger leakage current, leakage current be proportional to the sectional area of Schottky pole and temperature square.In order to reduce leakage current, can work under not too high temperature environment by control device.And the sectional area of Schottky diode do the smaller the better, and the semiconductor layer in conductive layer/semi-conductor/conducting layer three-decker is kept a suitable thickness.
Reducing leakage current very effective method is exactly select the metal/semiconductor material of suitably pairing, makes it to have larger potential barrier.Lower form lists some common metal materials and N-type (with some P types) Si and GaAs forms barrier height (the barrierheight-φ after Schottky diode b):
Metal Mg Ti Cr W Mo Pd Au Pt
Si--φ Bn(eV) 0.4 0.5 0.61 0.67 0.68 0.77 0.8 0.9
Si-φ Bp(eV) 0.61 0.5 0.42 0.3
GaAs-φ Bn(eV) 0.9 0.86
In order to reduce leakage current, should select gold half contact that potential barrier is high, such as gold (Au) or platinum (Pt) form Schottky diode with N type semiconductor.
More than describe preferred embodiment of the present invention in detail.Should be appreciated that those of ordinary skill in the art just design according to the present invention can make many modifications and variations without the need to creative work.Therefore, all technical staff in the art, all should by the determined protection range of claims under this invention's idea on the basis of existing technology by the available technical scheme of logical analysis, reasoning, or a limited experiment.

Claims (10)

1. a magnetic RAM manufacturing process, is characterized in that, comprising:
Form hearth electrode;
Forming Magnetic Memory cell array at described hearth electrode top, forming the MTJ and conductive layer 1/ semi-conductor/conducting layer 2 three-decker of connecting comprising preparing plural layers;
Top electrode is formed at described Magnetic Memory cell array top.
2. manufacturing process as claimed in claim 1, it is characterized in that, the formation of described hearth electrode comprises:
Depositions of bottom electrode metal level and hard mask one;
Photoetching hearth electrode;
Etching hearth electrode;
Deposit dielectrics one;
Surface planarisation.
3. manufacturing process as claimed in claim 1, it is characterized in that, the formation of described Magnetic Memory cell array comprises:
The film of described conductive layer 1/ semi-conductor/conducting layer 2 three-decker and described MTJ is formed in the preparation of described hearth electrode top, wherein first preparation forms the film of the film MTJ described in sedimentary composition again of described conductive layer 1/ semi-conductor/conducting layer 2 three-decker, or the film of MTJ described in first sedimentary composition prepares the film forming described conductive layer 1/ semi-conductor/conducting layer 2 three-decker again;
Deposit hard mask two;
Photoetching Magnetic Memory cell array;
Etching Magnetic Memory cell array;
Deposit dielectrics two;
Surface planarisation.
4. manufacturing process as claimed in claim 1, it is characterized in that, the formation of described top electrode comprises:
At described Magnetic Memory cell array deposited atop top electrode metal level and hard mask three;
Photoetching top electrode;
Etching top electrode;
Deposit dielectrics three;
Surface planarisation.
5. manufacturing process as claimed in claim 1, is characterized in that, described MTJ comprises the magnetic reference layer of stacked setting, tunnel barrier layer and Magnetic memory layer.
6. manufacturing process as claimed in claim 1, it is characterized in that, the semiconductor of described conductive layer 1/ semi-conductor/conducting layer 2 three-decker comprises P type semiconductor or N type semiconductor.
7. manufacturing process as claimed in claim 6; it is characterized in that; the conductive layer 1 of described conductive layer 1/ semi-conductor/conducting layer 2 three-decker and conductive layer 2 comprise the diffusion barrier be disposed adjacent with the semiconductor of described conductive layer 1/ semi-conductor/conducting layer 2 three-decker respectively, to stop that the impurity in described P type semiconductor or N type semiconductor spreads in described conductive layer 1 and conductive layer 2.
8. manufacturing process as claimed in claim 1, it is characterized in that, conductive layer 1 and/or the conductive layer 2 of described conductive layer 1/ semi-conductor/conducting layer 2 three-decker comprise Pt, Au, Rd, Ir, Ru, Pd, Ag, Mo, Cr, W, Ti, Ta or CuAl.
9. manufacturing process as claimed in claim 1, it is characterized in that, described top electrode and/or described hearth electrode comprise metal level Cu; Or comprise sandwich construction TaN/Ta/Cu/Ta/TaN or TiN/Ti/Cu/Ti/TiN, wherein TaN/Ta or TiN/Ti at Cu top is as hard mask.
10. the manufacturing process as described in claim 1-9, it is characterized in that, described hearth electrode defines some first guiding lines, described top electrode defines some second guiding lines arranged in a crossed manner with described some first guiding lines, thus described some first guiding lines and described some second guiding lines define some crossover nodes; Each described crossover node is provided with a Magnetic Memory unit, and described Magnetic Memory unit is electrically connected with first guiding line at crossover node place residing for it and the second guiding line respectively.
CN201510726489.5A 2015-10-30 2015-10-30 Crossing matrix array magnetic random memory manufacturing process Pending CN105514262A (en)

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CN1487523A (en) * 2002-03-15 2004-04-07 ��������˹�����տ����� Improved diode used in MRAM device and producing method thereof
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CN103021449A (en) * 2011-09-26 2013-04-03 株式会社东芝 Magnetic random access memory
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Publication number Priority date Publication date Assignee Title
CN1445782A (en) * 2002-03-14 2003-10-01 惠普公司 Storage device array magnetic bit with of with sharing one common line
CN1487523A (en) * 2002-03-15 2004-04-07 ��������˹�����տ����� Improved diode used in MRAM device and producing method thereof
CN101256831A (en) * 2007-01-30 2008-09-03 三星电子株式会社 Memory devices including multi-bit memory cells having magnetic and resistive memory elements and related methods
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Publication number Priority date Publication date Assignee Title
CN107527993A (en) * 2016-06-20 2017-12-29 上海磁宇信息科技有限公司 A kind of MTJ contact electrode and forming method thereof
CN107527993B (en) * 2016-06-20 2020-05-26 上海磁宇信息科技有限公司 Magnetic tunnel junction contact electrode and forming method thereof

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Application publication date: 20160420