CN105511836A - High-speed and multimode modulo addition operation circuit - Google Patents
High-speed and multimode modulo addition operation circuit Download PDFInfo
- Publication number
- CN105511836A CN105511836A CN201610044246.8A CN201610044246A CN105511836A CN 105511836 A CN105511836 A CN 105511836A CN 201610044246 A CN201610044246 A CN 201610044246A CN 105511836 A CN105511836 A CN 105511836A
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- China
- Prior art keywords
- mask
- tunnel
- addend
- adds
- computing
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
Abstract
The present invention provides the circuits that a kind of high-speed multi-mode time mould adds operation, including one 32 adder circuits, the adder circuit includes 4 input terminals and an output end, 4 input terminals are respectively the input terminal of addend y, the input terminal of summand x, mask mask input terminal and scheme control end, output end is used to export addition results s,
. Mask is used for the highest bit mask of every 16 bit of addend y, summand x or 8 bits and generates highest order without the addition results of carry. The present invention supports the add operation of 32,1 tunnel, the add operation of 16,2 tunnel and the add operation of 8,4 tunnels simultaneously on the basis of common 32 adders. The present invention provides strength for high speed password realization and supports.
Description
Technical field
Symmetric cryptographic algorithm field of the present invention, particularly relates to the circuit that a kind of high-speed multi-mode time mould adds computing.
Background technology
It is one of modal computing in symmetric cryptographic algorithm that mould adds computing, and the mould that common are 8/16/32 Bit data adds, and the mould efficiently realizing various granularity fast adds computing and can be high speed password and realize providing powerful and support.
Summary of the invention
For solving the problem, the invention provides the circuit that a kind of high-speed multi-mode time mould adds computing, it is characterized in that, comprise the adder circuit of 32, described adder circuit comprises 4 input ends and an output terminal, described 4 input ends are respectively the input end of addend y, the input end of summand x, mask mask input end and Schema control end, and output terminal is for exporting addition results s
Mask is used for the most significant digit shielding by every to addend y, summand x 16 bits or 8 bits.
Further, when x, y are 1 tunnel 31 Bit data, mask is 0x7fffffff.
Further, when x, y are for parallel two-way 16 Bit data, mask is 0x7fff7fff.
Further, when x, y are for parallel 4 tunnel 8 Bit data, mask is 0x7f7f7f7f.
Accompanying drawing explanation
Fig. 1 is electrical block diagram of the present invention.
Embodiment
Below structure of the present invention is described.As shown in Figure 1,
Comprise the adder circuit of 32, the input end of described adder circuit comprises input end (as addend in figure 2), the input end (as addend in figure 1) of summand x, mask mask input end, the Schema control end (as the model selection in Fig. 1 controls) of addend y, and output terminal exports addition results s.
Design concept of the present invention is: on the basis of common 32 totalizers, support 1 32, tunnel additive operation, the additive operation of 16,2 tunnel and the additive operation of 8,4 tunnels simultaneously, just must manage the carry stoping every 16 bits or 8 bits to more high-order generation under 16 or 8 addition scheme.This can complete by following two steps:
The first step, shields the most significant digit of two every 16 bits of operand or 8 bits, is then added (would not produce the carry of leap 16 bit or 8 bit boundaries like this).
Second step, does 1 bit addition to every 16 bits of two operands or 8 bit most significant digits, and adds the carry of being brought into by a secondary high position, to revise its value.
Suppose that x, y are respectively two 32 bit operand.
According to above two steps, parallel 2 tunnel 16 bit addition can be expressed as:
s＝(x&0x7fff7fff)+(y&0x7fff7fff)
Parallel 4 tunnel 8 bit addition can be expressed as:
s＝(x&0x7f7f7f7f)+(y&0x7f7f7f7f)
To sum up, to support the additive operation of 32,1 tunnel, the additive operation of 16,2 tunnel and the additive operation of 8,4 tunnels simultaneously, the mask mask of one 32 bits can be set, be defined as follows:
Unified totalizer is defined as
Beneficial effect of the present invention is:
The present invention, on the basis of common 32 totalizers, by additional a small amount of with, XOR, supports following functions:
1) support that the mould of 32 Bit datas adds computing;
2) support that the mould of two 16 Bit datas adds computing;
3) support that the mould of four 8 Bit datas adds computing.
The present invention supports for high speed password realizes providing powerful.
Claims (4)
1. a high-speed multi-mode time mould adds the circuit of computing, it is characterized in that, comprise the adder circuit of 32, described adder circuit comprises 4 input ends and an output terminal, described 4 input ends are respectively the input end of addend y, the input end of summand x, mask mask input end and Schema control end, output terminal is for exporting addition results s
Mask is used for the most significant digit of every to addend y, summand x 16 bits or 8 bits shield and produce the addition results of most significant digit not with carry.
2. high-speed multi-mode time mould as claimed in claim 1 adds the circuit of computing, and it is characterized in that, when x, y are 1 tunnel 31 Bit data, mask is 0x7fffffff.
3. high-speed multi-mode time mould as claimed in claim 1 adds the circuit of computing, it is characterized in that, when x, y are for parallel two-way 16 Bit data, mask is 0x7fff7fff.
4. high-speed multi-mode time mould as claimed in claim 1 adds the circuit of computing, it is characterized in that, when x, y are for parallel 4 tunnel 8 Bit data, mask is 0x7f7f7f7f.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610044246.8A CN105511836A (en) | 2016-01-22 | 2016-01-22 | High-speed and multimode modulo addition operation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610044246.8A CN105511836A (en) | 2016-01-22 | 2016-01-22 | High-speed and multimode modulo addition operation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105511836A true CN105511836A (en) | 2016-04-20 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610044246.8A Pending CN105511836A (en) | 2016-01-22 | 2016-01-22 | High-speed and multimode modulo addition operation circuit |
Country Status (1)
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| CN (1) | CN105511836A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100020791A1 (en) * | 2004-07-15 | 2010-01-28 | Paul Shore | Method and System for a Gigabit Ethernet IP Telephone Chip with No DSP Core, Which Uses a RISC Core With Instruction Extensions to Support Voice Processing |
| CN102520903A (en) * | 2011-12-13 | 2012-06-27 | 中国科学院自动化研究所 | Length-configurable vector maximum/minimum network supporting reconfigurable fixed floating points |
| CN103176949A (en) * | 2011-12-20 | 2013-06-26 | 中国科学院深圳先进技术研究院 | Circuit and method for achieving fast Fourier transform (FFT) / inverse fast Fourier transform (IFFT) |
| CN205540690U (en) * | 2016-01-22 | 2016-08-31 | 成都三零嘉微电子有限公司 | High -speed multi -mode mould adds circuit of operation |
-
2016
- 2016-01-22 CN CN201610044246.8A patent/CN105511836A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100020791A1 (en) * | 2004-07-15 | 2010-01-28 | Paul Shore | Method and System for a Gigabit Ethernet IP Telephone Chip with No DSP Core, Which Uses a RISC Core With Instruction Extensions to Support Voice Processing |
| CN102520903A (en) * | 2011-12-13 | 2012-06-27 | 中国科学院自动化研究所 | Length-configurable vector maximum/minimum network supporting reconfigurable fixed floating points |
| CN103176949A (en) * | 2011-12-20 | 2013-06-26 | 中国科学院深圳先进技术研究院 | Circuit and method for achieving fast Fourier transform (FFT) / inverse fast Fourier transform (IFFT) |
| CN205540690U (en) * | 2016-01-22 | 2016-08-31 | 成都三零嘉微电子有限公司 | High -speed multi -mode mould adds circuit of operation |
Non-Patent Citations (2)
| Title |
|---|
| DAREK MIHOCKA，ET AL: "《A Proposal for Hardware-Assisted Arithmetic Overflow Detection for Array and Bitfield Operations》", 《HARDWARE ASSISTED ARITHMETIC OVERFLOW DETECTION》 * |
| 杨晋吉，等: "《一种基于多模式加密算法的文件保护方案》", 《计算机应用研究》 * |
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Application publication date: 20160420 |
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