CN104915177A - Mixed type summator and efficient mixed type summator - Google Patents
Mixed type summator and efficient mixed type summator Download PDFInfo
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Abstract
The invention discloses a mixed type summator and an efficient mixed type summator. According to the embodiment, the mixed type summator comprises an operation device and a carry value generation device; the operation device comprises a first four-bit summator body and N four-bit operation units; each four-bit operation unit comprises two second four-bit summator bodies and a first carry selection unit, wherein the carry values of the two second four-bit summator bodies are 0 and 1 respectively, and the output ends are connected to the two input ends of the first carry selection unit respectively; each four-bit operation unit is used for selecting one generated operation result in the corresponding second four-bit summator body according to carry signals; N carry valve output ends which are connected to the carry input ends of the N first carry selection units are arranged in the carry value generation device in a one-to-one corresponding mode. By means of the mixed type summator, the operation rate of the summator can be improved; meanwhile, the smaller territory area is guaranteed, and the power dissipation is accordingly reduced.
Description
Technical Field
The present invention relates to computer technologies, and more particularly, to a hybrid adder and a high-efficiency hybrid adder.
Background
With the development of high performance processors (CPUs), adders are widely used in digital signal Processing, communication, image and video Processing as one of core components in Arithmetic Logic Units (ALUs). The operation of the adder is usually required to be completed in one cycle, and with the higher requirements of the computer on the operating frequency and the data bit width of the CPU chip, the operation rate of the adder becomes a main factor limiting the operating efficiency of the ALU. The existing adders mainly comprise two types, one type is the adder with a higher-order calculation function formed by overlapping typical structures layer by layer, but the adder of the type has longer calculation delay, lower calculation rate and larger layout area; the other is an adder adopting a parallel prefix structure, and although the operation rate is improved to a certain extent, the adder of the type has a larger fan, so that the delay is increased.
Obviously, the adder provided by the prior art is difficult to realize reasonable planning between the operation rate and the layout area.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a hybrid adder and a high-efficiency hybrid adder, which can improve the operation rate of the adder and ensure a smaller layout area, thereby reducing power consumption.
Compared with the prior art, the hybrid adder provided by the invention comprises: arithmetic means and carry value generating means; the arithmetic device comprises a first 4-bit adder and N4-bit arithmetic units which are sequentially arranged, wherein the carry value of the first 4-bit adder is 0, and N is an integer between 1 and 7;
each 4-bit operation unit comprises two second 4-bit adders and a first carry selection unit which are parallel, the carry value of one second 4-bit adder is 0, the carry value of the other second 4-bit adder is 1, the output ends of the two second 4-bit adders are connected to two data input ends of the first carry selection unit in a one-to-one correspondence mode, and the first carry selection unit comprises the two data input ends, a carry input end and an output end; each 4-bit operation unit is used for selecting an operation result generated by one of the two second 4-bit adders according to a carry signal received by a carry input end of the first carry selection unit and outputting the selected operation result through the output end;
the carry value generating device is provided with N carry value output ends, the N carry value output ends are connected to the carry input ends of the N first carry selection units in a one-to-one correspondence mode, and the carry value generating device is used for transmitting carry signals to the first carry selection units connected with the carry value output ends through each carry value output end.
The hybrid adder as described above, wherein each bit of the first 4-bit adder and N4-bit arithmetic units arranged in sequence corresponds to each bit of the operand one by one, the nth carry value output end of the carry value generating device is configured to output a carry signal according to bits 1 to 4N of the operand, where N is greater than or equal to 1 and less than or equal to N.
The hybrid adder as described above, wherein N ═ 7;
the carry value generating device comprises 7 combination logic modules, each combination logic module comprises 4 pairs of input ends and 1 pair of output ends, the 4 pairs of input ends of the nth combination logic module correspond to 4n-3 to 4n bits of an operand, each combination logic module comprises a first combination logic unit, a second combination logic unit and a third combination logic unit, the first combination logic unit, the second combination logic unit and the third combination logic unit respectively comprise 2 pairs of input ends and 1 pair of output ends, wherein the first combination logic unit and the second combination logic unit are connected in parallel, the 2 pairs of input ends of the first combination logic unit and the 2 pairs of input ends of the second combination logic unit are used as the 4 pairs of input ends of the combination logic module, and the 1 pair of output ends of the first combination logic unit and the 1 pair of output ends of the second combination logic unit are connected to the 2 pairs of input ends of the third combination logic unit in a one-to-one correspondence manner, the 1 pair of output ends of the third combinational logic unit are used as the 1 pair of output ends of the combinational logic module; each combinational logic module is used for outputting a first signal and a second signal by a first combinational logic unit and a second combinational logic unit respectively according to the operands corresponding to the 4 pairs of input ends, so that a third signal is output by a third combinational logic unit according to the first signal and the second signal, wherein the first signal, the second signal and the third signal respectively comprise a carry value generation signal and a carry value propagation signal, and N is more than or equal to 1 and less than or equal to N;
the carry value generating device further comprises 3 fourth combinational logic cells and 6 carry generating logic cells, wherein the input terminal of the 1 st of the fourth combinational logic cells is connected to the output terminals of the 3 rd and 4 th combinational logic modules, the input terminal of the 2 nd of the fourth combinational logic cells is connected to the output terminals of the 5 th and 6 th combinational logic modules, the input terminal of the 3 rd of the fourth combinational logic cells is connected to the output terminals of the 6 th and 7 th combinational logic modules, the input terminal of the 1 st of the carry generating logic cells is connected to the output terminals of the 1 st and 2 nd of the combinational logic modules, the input terminal of the 2 nd of the carry generating logic cells is connected to the output terminal of the 1 st of the carry generating logic cells and the output terminal of the 3 rd of the carry generating logic cells, and the input terminal of the 3 rd of the carry generating logic cells is connected to the 1 st of the carry generating logic cells An output of said member and an output of said fourth combinational logic cell of 1, an input of said carry-generation logic cell of 4 th being connected to an output of said carry-generation logic cell of 3 rd and an output of said combinational logic cell of 5 th, an input of said carry-generation logic cell of 5 th being connected to an output of said carry-generation logic cell of 3 rd and an output of said fourth combinational logic cell of 2 nd, an input of said carry-generation logic cell of 6 th being connected to an output of said carry-generation logic cell of 3 rd and an output of said fourth combinational logic cell of 3 rd;
the output end of the 1 st combinational logic module and the output end of the 6 carry generation logic units are connected to the carry input ends of the 7 4-bit operation units in a one-to-one correspondence manner, wherein the carry generation signal in the third signal output by the 1 st combinational logic module is specifically a carry signal input to the 1 st 4-bit operation unit.
The hybrid adder as described above, wherein the carry value generating apparatus further includes 6 buffers, the 1 st buffer is connected between the output terminal of the 1 st combinational logic block and the input terminal of the 1 st 4-bit operation unit, the 2 nd buffer is connected between the output terminal of the 1 st 4-bit operation unit and the input terminal of the 2 nd 4-bit operation unit, the 3 rd buffer is connected between the output terminal of the 3 rd combinational logic block and the input terminal of the 2 nd 4-bit operation unit, the 4 th buffer is connected between the output terminal of the 5 th combinational logic block and the input terminal of the 4 th carry generation logic unit, the 5 th buffer is connected between the output terminal of the 2 nd combinational logic unit and the input terminal of the 5 th carry generation logic unit, the 6 th said buffer is connected between the output of the 7 th said combinational logic block and the input of the 3 rd said fourth combinational logic cell.
The invention also provides a high-efficiency mixed adder, which comprises: a high-order operation module and a low-order operation module;
the high-order operation module comprises two parallel hybrid adders and a second carry selection unit, wherein the carry value of one hybrid adder is 0, the carry value of the other hybrid adder is 1, the output ends of the two hybrid adders are connected to two data input ends of the second carry selection unit in a one-to-one correspondence mode, and the second carry selection unit comprises the two data input ends, a carry input end and an output end; the high-order operation module is used for selecting an operation result generated by one of the two mixed adders according to a carry signal received by a carry input end of the second carry selection unit and outputting the selected operation result through the output end;
the low-order operation module comprises a hybrid adder according to any one of the above claims, and further comprises a low-order output terminal and a carry output terminal, wherein the low-order output terminal is used as a low 4 x (N +1) order output terminal of the high-efficiency hybrid adder, and the carry output terminal is connected to the carry input terminal of the second carry selection unit and is used for transmitting a carry signal to the second carry selection unit.
The high-efficiency hybrid adder as described above, wherein the low order operation module further comprises a first control signal input terminal, and the high-efficiency hybrid adder is configured to perform an addition operation when the input of the first control signal input terminal is 0 and perform a subtraction operation when the input of the first control signal input terminal is 1.
The high-efficiency hybrid adder as described above further comprises: the mode selection unit is arranged between the low-order operation module and the second carry selection unit, the carry output end of the low-order operation module is connected to the input end of the mode selection unit, the output end of the mode selection unit is connected to the carry input end of the second carry selection unit, and the mode selection unit further comprises a mode selection input end and a second control signal input end;
the mode selection unit selects an output value of a low-order output end of the low-order operation module when the input of the mode selection input end is 1; or,
the mode selection unit selects an input value of the second control signal input terminal when an input of the mode selection input terminal is 0.
The high-efficiency hybrid adder as described above, wherein if the input at the mode selection input terminal is 0, the lower operation module is configured to perform an addition operation when the input at the first control signal input terminal is 0, and to perform a subtraction operation when the input at the first control signal input terminal is 1, and the upper operation module is configured to perform an addition operation when the input at the second control signal input terminal is 0, and to perform a subtraction operation when the input at the second control signal input terminal is 1.
The invention provides a hybrid adder and a high-efficiency hybrid adder, wherein the hybrid adder carries out summation operation and carry operation of operands simultaneously through an arithmetic device and a carry value generating device, specifically, when the carry value generating device generates a carry value, two parallel second 4-bit adders of each 4-bit arithmetic unit in the arithmetic device calculate two operation results when the carry values are 0 and 1, so that when a first carry selecting unit of the 4-bit arithmetic unit obtains the actually generated carry value, a result matched with the actual carry value is directly selected from the operation results obtained by the two parallel second 4-bit adders. The hybrid adder provided by the embodiment can ensure that the adder has a smaller layout area while increasing the operation rate, thereby reducing the power consumption.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.
Fig. 1 is a schematic structural diagram of a hybrid adder according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a 4-bit arithmetic unit according to the embodiment shown in FIG. 1;
fig. 3 is a schematic structural diagram of another hybrid adder according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of the input and output of the first combinational logic cell of the embodiment shown in FIG. 3;
FIG. 5 is a schematic diagram of the first combinational logic cell shown in FIG. 4;
FIG. 6 is a schematic diagram illustrating the input and output of the carry generation logic unit of the embodiment shown in FIG. 3;
FIG. 7 is a schematic diagram of the carry generation logic unit shown in FIG. 6;
FIG. 8 is a schematic diagram of a buffer according to the embodiment shown in FIG. 3;
fig. 9 is a schematic structural diagram of an efficient hybrid adder according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
The steps illustrated in the flow charts of the figures may be performed in a computer system such as a set of computer-executable instructions. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed in an order different than here.
Fig. 1 is a schematic structural diagram of a hybrid adder according to an embodiment of the present invention. As shown in fig. 1, the hybrid adder 100 provided in the present embodiment includes: an arithmetic unit 110 and a carry value generation unit 120; the operation device 110 includes a first 4-bit adder 111 and N4-bit operation units 112, which are sequentially arranged, wherein the carry value of the first 4-bit adder 111 is 0, and N may be an integer between 1 and 7; the hybrid adder 100 provided in this embodiment is configured to perform a 4 × N +1 bit addition and subtraction operation, for example, when N is 7, the hybrid adder 100 is configured to perform a 32 bit addition and subtraction operation.
FIG. 2 is a schematic diagram of a 4-bit arithmetic unit according to the embodiment shown in FIG. 1. As shown in fig. 2, each 4-bit operation unit 112 in the hybrid adder 100 provided in this embodiment includes two parallel second 4-bit adders 113 and a first carry selection unit 114, wherein a carry value of one of the second 4-bit adders 113 is 0, a carry value of the other second 4-bit adder is 1, output ends of the two second 4-bit adders 113 are connected to two data input ends of the first carry selection unit 114 in a one-to-one correspondence manner, and the first carry selection unit 114 includes two data input ends of the first carry selection unit 114A data input, a carry input and an output; each 4-bit operation unit 112 is configured to select an operation result generated by one of the two second 4-bit adders 113 according to a carry signal received by a carry input terminal of the first carry selection unit 114, and output the selected operation result through an output terminal. In this embodiment, two parallel second 4-bit adders 113 are used to calculate the same number of bits of the operand, for example, taking N as 7 as an example, two second 4-bit adders 113 in the 1 st 4-bit arithmetic unit 112 are both used to calculate 5-8 bits of the 32-bit operand, two second 4-bit adders 113 in the 2 nd 4-bit arithmetic unit 112 are both used to calculate 9-12 bits of the 32-bit operand, and so on. As shown in fig. 2, for performing a summation operation on bits j to i of an operand, a [ i: j ]]And B [ i: j ]]Carry values input to the two second 4-bit adders 113 are 0 and 1, respectively, and a carry signal input to the first carry select unit 114 is Gj-1:1The carry signal indicating the 4-bit operation unit 112 is obtained by carrying the operand 1 to j-1 bits, the output value of the 4-bit operation unit 112 is obtained by carrying the operand j to i bits, and the carry signal input to the first carry selection unit 114 is Gj-1:1Obtained, expressed as: result [ i: j ]]。
The carry value generating device 120 in the hybrid adder 100 provided in this embodiment is provided with N carry value outputs 121, where the N carry value outputs 121 are connected to the carry input terminals of the N first carry selecting units 114 in a one-to-one correspondence manner, and are used for transmitting a carry signal to the first carry selecting unit 114 connected to the carry value output 121 through each carry value output 121.
In the present embodiment, by providing two second 4-bit adders 113 in parallel to each 4-bit operation unit 112 in the operation device 110, two operation results when carry values are 0 and 1, respectively, can be calculated at the same time, and at the same time, a carry signal corresponding to each 4-bit operation unit 112 is generated by the carry value generation device 120 and transmitted to the first carry selection unit 114 corresponding thereto, so that each 4-bit operation unit 112 selects the two operation results that have been calculated according to the carry device input to the first carry selection unit 114. That is, in this embodiment, by providing a redundant operation, the carry value is calculated in two cases during operation, so that when the first carry selection unit 114 obtains the carry signal corresponding to the carry value, one of the calculated operation results can be directly selected, that is, the operation result corresponding to the operand can be output. The structure of the 4-bit operation unit in the hybrid adder 100 provided in this embodiment reduces the hardware overhead caused by carry generation, reduces the operation delay, and improves the operation rate to a great extent, for example, the operation frequency of 2 gigahertz (GHz) can be reached under a 40 nanometer (nm) process with the support of using a hardware description language and an Electronic Design Automation (EDA) tool.
It should be noted that, the first 4-bit adder 111 in the present embodiment is used for calculating 1 to 4 bits of the operand, and since the 1 to 4 bits of the operand are the lowest bits and the carry value is constant 0, the operation can be directly performed by the first 4-bit adder 111; in the present embodiment, the first 4-bit adder 111 and the second 4-bit adder 113 may be of the same type or of different types, and may be, for example, a 4-bit serial adder or a 4-bit parallel adder.
In a specific implementation, each bit of the first 4-bit adder 111 and each bit of the N4-bit arithmetic units 112, which are sequentially arranged, corresponds to each bit of the operand one by one, the nth carry value output end 121 of the carry value generating device 120 is configured to output a carry signal according to bits 1 to 4N of the operand, where N is greater than or equal to 1 and less than or equal to N, and since the nth 4-bit arithmetic unit 112 is configured to calculate bits 4N +1 to 4N +4 of the operand, a carry signal generated by bits 1 to 4N of the operand needs to be acquired; the carry value generating device 120 in the present embodiment may adopt a sparse tree structure to design the carry value generating device 120 so as to generate a carry signal corresponding to each of 1-4N bits, where N is an integer between 1 and N, and the carry signal output by the carry value output terminal 121 is further used for passing down to generate a carry signal required by the subsequent 4-bit operation unit 112. Because the present embodiment uses the 4-bit adder to perform summation operation, correspondingly, the carry value generation device 120 may perform carry operation by using each 4 bits of the operand as a group, and transmit the carry operation result of the lower 4 bits to the higher bits to perform carry operation, and when the carry value generation device 120 provided in the present embodiment is formed by using the sparse tree structure, the carry value generation device 120 may be formed by using a smaller number of logic gates, which is beneficial to reducing layout area and reducing power consumption.
The hybrid adder provided in this embodiment performs sum operation and carry operation of operands simultaneously by using the arithmetic device and the carry value generation device, and specifically, while the carry value generation device generates a carry value, two parallel second 4-bit adders of each 4-bit arithmetic unit in the arithmetic device calculate two operation results when the carry value is 0 and 1, so that when the first carry selection unit of the 4-bit arithmetic unit obtains an actually generated carry value, a result matched with the actual carry value is directly selected from the operation results obtained by the two parallel second 4-bit adders. The hybrid adder provided by the embodiment can ensure that the hybrid adder has a smaller layout area while improving the operation rate, thereby reducing the power consumption.
It should be noted that, in the present embodiment, based on the operation time of the sum operation and the carry operation, the basic sum operation unit is formed by using the 4-bit adder, so that the execution cycles of the sum operation and the carry operation are matched, and the parallel degree is better, so as to reduce the delay of the hybrid adder 100 to the maximum extent.
Further, the carry value generating apparatus 120 in this embodiment further includes a first control signal input terminal Cin1So that the hybrid adder 100 is at the first control signal input terminal Cin1Performs an addition operation when the input of (1) is the input of the first control signal input terminal, and performs a subtraction operation when the input of (1) is the input of the first control signal input terminal; specifically, the relational expression for realizing the subtraction function is as follows:thus, the addition and subtraction can be effectively integrated by negating the subtrahend of the operand and then adding 1 to the subtrahend by the carry input, e.g., negating the subtrahend using an exclusive or gate, and the process of the subtraction operation can be described by the code: assign B ═ Src2^ 32{ Cin1}}. The specific meaning of the code is C when the subtraction operation is performedin1Is 1, operands Src2 and Cin1After XOR, inverting Src 2; when performing addition operation Cin1Is 0 and the operands are unchanged after the exclusive or.
Fig. 3 is a schematic structural diagram of another hybrid adder according to an embodiment of the present invention. As shown in fig. 3, specifically, N is 7 as an example, that is, the hybrid adder 100 shown in fig. 3 specifically includes 7 4-bit operation units 112, and the hybrid adder 100 is configured to perform 32-bit addition and subtraction operations.
The present embodiment provides a specific structure of the carry value generating apparatus 120, the carry value generating apparatus 120 includes 7 combinational logic modules 122, each combinational logic module 122 includes 4 pairs of input terminals and 1 pair of output terminals, 4 pairs of input terminals of the nth combinational logic module 122 correspond to 4n-3 to 4n bits of the operand, each combinational logic module 122 includes a first, a second and a third combinational logic unit 122a, the first, the second and the third combinational logic unit 122a include 2 pairs of input terminals and 1 pair of output terminals respectively, the first and second combinational logic units 122a are connected in parallel, 2 pairs of input ends of the first combinational logic unit 122a and 2 pairs of input ends of the second combinational logic unit 122a are used as 4 pairs of input ends of the combinational logic module 122, and 1 pair of output ends of the first combinational logic unit 122a and 1 pair of output ends of the second combinational logic unit 122a are connected to 2 pairs of input ends of the third combinational logic unit 122a in a one-to-one correspondence manner; each combinational logic module 122 is configured to output a first signal and a second signal by the first and second combinational logic units 122a, respectively, according to the operands corresponding to the 4 pairs of input terminals, and thereby output a third signal by the third combinational logic unit 122a according to the first signal and the second signal, wherein the first, second, and third signals respectively include a carry value generation signal and a carry value propagation signal.
This exampleCarry value generating apparatus 120 in the supply further includes 3 fourth combinational logic cells 122b and 6 carry generating logic cells 123, wherein an input terminal of the 1 st fourth combinational logic cell 122b is connected to output terminals of the 3 rd and 4 th combinational logic blocks 122, an input terminal of the 2 nd fourth combinational logic cell 122b is connected to output terminals of the 5 th and 6 th combinational logic blocks 122, an input terminal of the 3 rd fourth combinational logic cell 122b is connected to output terminals of the 6 th and 7 th combinational logic blocks 122, an input terminal of the 1 st carry generating logic cell 123 is connected to output terminals of the 1 st and 2 nd combinational logic blocks 122, an input terminal of the 2 nd carry generating logic cell 123 is connected to an output terminal of the 1 st carry generating logic cell 123 and an output terminal of the 3 rd combinational logic block 122, an input terminal of the 3 rd carry generating logic cell 123 is connected to an output terminal of the 1 st carry generating logic cell 123 and an output terminal of the 1 st carry generating logic cell 123 The output of four combinational logic cell 122b, the input of 4 th carry generation logic cell 123 is connected to the output of 3 rd carry generation logic cell 123 and the output of 5 th combinational logic block 122, the input of 5 th carry generation logic cell 123 is connected to the output of 3 rd carry generation logic cell 123 and the output of 2 nd combinational logic cell 122b, the input of 6 th carry generation logic cell 123 is connected to the output of 3 rd carry generation logic cell 123 and the output of 3 rd combinational logic cell 122 b; and, the output end of the 1 st combinational logic module 122 and the output end of the 6 carry generation logic units 123 are connected to the carry input ends of the 7 4-bit operation units 112 in a one-to-one correspondence manner, wherein, the carry generation signal in the third signal output by the 1 st combinational logic module 122 is specifically the carry signal input to the 1 st 4-bit operation unit 122, the carry value relay signal in the third signal is used as one input signal of the 1 st carry generation logic unit 123, and in addition, the third signals output by the 2 nd to 7 th combinational logic modules 122 are all used as the input signals of the logic units connected thereto. It should be noted that the first control signal input terminal C in the embodiment shown in fig. 3in1Connected to the input of the 1 st combinational logic block 122, which functions as the first control signal input in the above-described embodimentCin1The same applies by providing the first control signal input terminal Cin1The input value of (a) implements a subtraction operation.
Further, the carry value generating apparatus 120 of the hybrid adder 100 in the embodiment shown in fig. 3 further includes 6 buffers 124, wherein the 1 st buffer 124 is connected between the output terminal of the 1 st combinational logic block 122 and the input terminal of the 1 st 4-bit operation unit 112, the 2 nd buffer 124 is connected between the output terminal of the 1 st carry generation logic unit 123 and the input terminal of the 2 nd 4-bit operation unit 112, the 3 rd buffer 124 is connected between the output terminal of the 3 rd combinational logic block 122 and the input terminal of the 2 nd carry generation logic unit 123, the 4 th buffer 124 is connected between the output terminal of the 5 th combinational logic block 122 and the input terminal of the 4 th carry generation logic unit 123, the 5 th buffer 124 is connected between the output terminal of the 2 nd combinational logic unit 122b and the input terminal of the 5 th carry generation logic unit 123, a 6 th buffer 124 is connected between the output of the 7 th combinatorial logic block 122 and the input of the 3 rd combinatorial logic unit 122 b. As shown in fig. 2, the present embodiment provides a buffer 124 at a position in the carry value generating device 120 where the delay may be large due to the long connection, so as to improve the driving, minimize the load on the critical path, thereby enhancing the signal strength and further improving the operation rate.
It should be noted that fig. 3 shows the 1 st combinational logic module 122 by a dashed box, the structure of the other 6 combinational logic modules 122 is the same as that of the 1 st combinational logic module, 4 pairs of input terminals are used for inputting the corresponding number of bits of the operand, the first, second and third logic units in the combinational logic module 122 are shown by 122a, the 3 fourth combinational logic units in the carry value generating device 120 are shown by 122b, and the specific structure and logical operation capability of the fourth combinational logic unit 122b are the same as those of the first, second and third logic units 122 a.
Optionally, fig. 4 is an input/output schematic diagram of the first combinational logic unit in the embodiment shown in fig. 3, and fig. 5 is a structure of the first combinational logic unit shown in fig. 4Fig. 6 is a schematic diagram of input and output of the carry generation logic unit in the embodiment shown in fig. 3, fig. 7 is a schematic diagram of a structure of the carry generation logic unit shown in fig. 6, fig. 8 is a schematic diagram of a structure of a buffer in the embodiment shown in fig. 3, and the bits of the operation bits corresponding to the input signal and the output signal in fig. 8 are the same. Referring to fig. 3 to 8, the first combinational logic unit 122a includes two logic units, specifically, a carry generation logic unit 123 and a carry propagation logic unit, and in fig. 4 to 7, the signal input by the 2 pairs of input terminals of the first combinational logic unit 122a is Gi:k、Gk-1:jAnd P isi:k、Pk-1:j1 the signal output by the pair of output terminals is Gi:j、Pi:jWhere G represents the input and output of the carry generation logic 123, P represents the input and output of the carry propagation logic, i, k-1, and j represent the number of bits of the operand, and i ≧ k, k-1 ≧ j, the logic formulas in the logic shown in FIGS. 5 and 7 include: gi:j＝Gi:k+Pi:kGk-1:j，Pi:j＝Pi:kPk-1:jWherein G is equal to k when i is equal to k and k-1 is equal to ji:i≡Gi，Pi:i≡PiDefining the input of the first control input terminal as: g0:0≡Cin1Initial value P0:00 [ identical to ] or; the structure and logic formulas of the second, third and fourth combinational logic cells are the same as those of the first combinational logic cell 122a shown in fig. 5 and 7 described above. As can be seen from fig. 3, since the sum operation only requires the output signal G of the carry generation logic unit 123, the carry generation logic units 123 are all connected to the 4-bit operation unit 112, and the buffer 124 can be used to minimize the load on the critical path, and the logic relations of the input signal and the output signal are the same.
Further, the embodiment of the present invention provides a high-efficiency hybrid adder, which is not formed by simply setting N of the hybrid adder 100 shown in fig. 1 to a larger value, but formed by combining carry selection with the structure of the hybrid adder 100 in the embodiment shown in fig. 1 or fig. 3. As shown in the figureFig. 9 is a schematic structural diagram of an efficient hybrid adder according to an embodiment of the present invention, and this embodiment specifically illustrates an example of forming a 64-bit efficient hybrid adder 10, where the 64-bit efficient hybrid adder 10 includes: a high-order operation module 11 and a low-order operation module 12; the high-order operation module 11 includes two parallel hybrid adders 100 and a second carry selection unit 130 as shown in fig. 3, the carry value of one hybrid adder 100 is 0, the carry value of the other hybrid adder 100 is 1, the output ends of the two hybrid adders 100 are connected to two data input ends of the second carry selection unit 130 in a one-to-one correspondence manner, and the second carry selection unit 130 includes two data input ends, a carry input end and an output end; the high-order operation module 11 is configured to select an operation result generated by one of the two hybrid adders 100 according to a carry signal received by a carry input end of the second carry selection unit 130, and output the selected operation result through an output end; the second carry select unit 130 functions as the first carry select unit 114 in the 4-bit operation unit 112 shown in fig. 2. In addition, the low-order operation module 12 includes a hybrid adder 100 shown in fig. 3, and the low-order operation module 12 further includes a low-order output terminal and a carry output terminal CoutThe low-order output terminal is used as the low-order 32-order output terminal of the high-efficiency hybrid adder 10 for outputting the Result [32:1 ] of the addition and subtraction operation]And the carry output terminal is connected to the carry input terminal of the second carry selection unit 130, and is used for transmitting a carry signal to the second carry selection unit 130, so that the high-efficiency hybrid adder 10 performs a 64-bit addition and subtraction operation.
Similarly to the above embodiments, the operation manner of the lower 32 bits in this embodiment is the same as that of the above embodiment shown in fig. 3, the operation of the upper 32 bits adopts the structure of carry selection to calculate the operation result of the operand with 33 to 64 bits, also calculates the operation result when the carry signal is 0 and 1 respectively, and selects one of the obtained results according to the carry signal obtained from the 32 th bit to directly output the operation result; in addition, the first control signal input terminal C can be set to the low-order operation module 12 as wellin1Such that the high-efficiency hybrid adder 10 is atA control signal input terminal Cin1Performs an addition operation when the input of (a) is 0, and performs an addition operation at a first control signal input terminal Cin1Is 1, the process of the subtraction operation can be described by the following codes: assign B ═ Src2^ 64{ Cin1}}。
Furthermore, the high-efficiency hybrid adder 10 provided in this embodiment further includes a mode selection unit 140 disposed between the lower operation module 12 and the second carry selection unit 130, specifically, the carry output terminal of the lower operation module 12 is connected to the input terminal of the mode selection unit 140, the output terminal of the mode selection unit 140 is connected to the carry input terminal of the second carry selection unit 130, the mode selection unit 140 further includes a mode selection input terminal SIMD64 and a second control signal input terminal Cin2(ii) a The mode selection unit 140 selects the lower output terminal C of the lower operation block 12 when the input of the mode selection input terminal SIMD64 is 1outSuch that the high-efficiency hybrid adder 10 performs a 64-bit addition-subtraction operation, or the mode selection unit 140 selects the second control signal input terminal C when the input of the mode selection input terminal SIMD64 is 0in2So that the high-efficiency hybrid adder 10 can perform 2 sets of 32-bit Single Instruction Multiple Data (SIMD) mode addition and subtraction operations, i.e., the calculation of 64-bit operand fixed-point addition and subtraction can be realized. The usage characteristics of each input signal and output signal in the high-efficiency hybrid adder 10 shown in fig. 9 are shown in table 1 below:
TABLE 1
The Sign bits (Sign1 and Sign2) are used to indicate the Sign of the operand, specifically a positive or negative number, the location of the input and Cin1And Cin2The same is true.
In this embodiment, based on the hybrid adder 100 provided in the embodiments shown in fig. 1 to fig. 8, a carry selection manner is further adopted to calculate addition and subtraction operations of high 4 × N +1 bits and low 4 × N +1 bits, respectively, so as to form a more efficient hybrid adder 10, and the mode selection unit 140 is added between the high bit operation module 11 and the low bit operation module 12, so that the efficient hybrid adder 10 can implement operations of two modes, has the capability of performing fixed-point operation on operands, and improves the application range of the efficient hybrid adder 10 provided in this embodiment.
In a specific implementation, when the input of the mode selection input terminal SIMD64 in this embodiment is 0, the higher operation module 11 and the lower operation module 12 respectively perform operations, and the lower operation module 12 is used for performing operations at the first control signal input terminal Cin1Performs an addition operation when the input of (a) is 0, and performs an addition operation at a first control signal input terminal Cin1Performs a subtraction operation when the input of (1), and the high-order operation module 11 is used for inputting a second control signal at the input end Cin2Performs an addition operation when the input of (a) is 0, and performs an addition operation at a second control signal input terminal Cin2Performing a subtraction operation when the input of (1); it should be noted that the first control signal input terminal Cin1And a second control signal input terminal Cin2The input values may be the same or different.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (9)
1. A hybrid adder, comprising: arithmetic means and carry value generating means; the arithmetic device comprises a first 4-bit adder and N4-bit arithmetic units which are sequentially arranged, wherein the carry value of the first 4-bit adder is 0, and N is an integer between 1 and 7;
each 4-bit operation unit comprises two second 4-bit adders and a first carry selection unit which are parallel, the carry value of one second 4-bit adder is 0, the carry value of the other second 4-bit adder is 1, the output ends of the two second 4-bit adders are connected to two data input ends of the first carry selection unit in a one-to-one correspondence mode, and the first carry selection unit comprises the two data input ends, a carry input end and an output end; each 4-bit operation unit is used for selecting an operation result generated by one of the two second 4-bit adders according to a carry signal received by a carry input end of the first carry selection unit and outputting the selected operation result through the output end;
the carry value generating device is provided with N carry value output ends, the N carry value output ends are connected to the carry input ends of the N first carry selection units in a one-to-one correspondence mode, and the carry value generating device is used for transmitting carry signals to the first carry selection units connected with the carry value output ends through each carry value output end.
2. The hybrid adder according to claim 1, wherein each bit of the first 4-bit adder and N4-bit arithmetic units arranged in sequence has a one-to-one correspondence with each bit of the operand, and the nth carry value output terminal of the carry value generating apparatus is configured to output a carry signal according to bits 1 to 4N of the operand, where N is greater than or equal to 1 and less than or equal to N.
3. The hybrid summer according to claim 1, wherein N-7;
the carry value generating device comprises 7 combination logic modules, each combination logic module comprises 4 pairs of input ends and 1 pair of output ends, the 4 pairs of input ends of the nth combination logic module correspond to 4n-3 to 4n bits of an operand, each combination logic module comprises a first combination logic unit, a second combination logic unit and a third combination logic unit, the first combination logic unit, the second combination logic unit and the third combination logic unit respectively comprise 2 pairs of input ends and 1 pair of output ends, wherein the first combination logic unit and the second combination logic unit are connected in parallel, the 2 pairs of input ends of the first combination logic unit and the 2 pairs of input ends of the second combination logic unit are used as the 4 pairs of input ends of the combination logic module, and the 1 pair of output ends of the first combination logic unit and the 1 pair of output ends of the second combination logic unit are connected to the 2 pairs of input ends of the third combination logic unit in a one-to-one correspondence manner, the 1 pair of output ends of the third combinational logic unit are used as the 1 pair of output ends of the combinational logic module; each combinational logic module is used for outputting a first signal and a second signal by a first combinational logic unit and a second combinational logic unit respectively according to the operands corresponding to the 4 pairs of input ends, so that a third signal is output by a third combinational logic unit according to the first signal and the second signal, wherein the first signal, the second signal and the third signal respectively comprise a carry value generation signal and a carry value propagation signal, and N is more than or equal to 1 and less than or equal to N;
the carry value generating device further comprises 3 fourth combinational logic cells and 6 carry generating logic cells, wherein the input terminal of the 1 st of the fourth combinational logic cells is connected to the output terminals of the 3 rd and 4 th combinational logic modules, the input terminal of the 2 nd of the fourth combinational logic cells is connected to the output terminals of the 5 th and 6 th combinational logic modules, the input terminal of the 3 rd of the fourth combinational logic cells is connected to the output terminals of the 6 th and 7 th combinational logic modules, the input terminal of the 1 st of the carry generating logic cells is connected to the output terminals of the 1 st and 2 nd of the combinational logic modules, the input terminal of the 2 nd of the carry generating logic cells is connected to the output terminal of the 1 st of the carry generating logic cells and the output terminal of the 3 rd of the carry generating logic cells, and the input terminal of the 3 rd of the carry generating logic cells is connected to the 1 st of the carry generating logic cells An output of said member and an output of said fourth combinational logic cell of 1, an input of said carry-generation logic cell of 4 th being connected to an output of said carry-generation logic cell of 3 rd and an output of said combinational logic cell of 5 th, an input of said carry-generation logic cell of 5 th being connected to an output of said carry-generation logic cell of 3 rd and an output of said fourth combinational logic cell of 2 nd, an input of said carry-generation logic cell of 6 th being connected to an output of said carry-generation logic cell of 3 rd and an output of said fourth combinational logic cell of 3 rd;
the output end of the 1 st combinational logic module and the output end of the 6 carry generation logic units are connected to the carry input ends of the 7 4-bit operation units in a one-to-one correspondence manner, wherein the carry generation signal in the third signal output by the 1 st combinational logic module is specifically a carry signal input to the 1 st 4-bit operation unit.
4. The hybrid adder according to claim 3, wherein the carry value generation apparatus further comprises 6 buffers, a 1 st of the buffers is connected between an output of a 1 st of the combinational logic blocks and an input of a 1 st of the 4-bit operation units, a 2 nd of the buffers is connected between an output of a 1 st of the carry generation logic units and an input of a 2 nd of the 4-bit operation units, a 3 rd of the buffers is connected between an output of a 3 rd of the combinational logic blocks and an input of a 2 nd of the carry generation logic units, a 4 th of the buffers is connected between an output of a 5 th of the combinational logic blocks and an input of a 4 th of the carry generation logic units, a 5 th of the buffers is connected between an output of a 2 nd of the fourth combinational logic units and an input of a 5 th of the carry generation logic units, the 6 th said buffer is connected between the output of the 7 th said combinational logic block and the input of the 3 rd said fourth combinational logic cell.
5. The hybrid adder according to claim 3, wherein the carry value generating means further comprises a first control signal input, the first control signal input being a further input of the 1 st combinational logic block, the hybrid adder being configured to perform an addition operation when the input of the first control signal input is 0 and to perform a subtraction operation when the input of the first control signal input is 1.
6. An efficient hybrid adder, comprising: a high-order operation module and a low-order operation module;
the high-order operation module comprises two parallel hybrid adders and a second carry selection unit as claimed in any one of claims 1 to 4, wherein the carry value of one hybrid adder is 0, the carry value of the other hybrid adder is 1, the output ends of the two hybrid adders are connected to two data input ends of the second carry selection unit in a one-to-one correspondence manner, and the second carry selection unit comprises the two data input ends, a carry input end and an output end; the high-order operation module is used for selecting an operation result generated by one of the two mixed adders according to a carry signal received by a carry input end of the second carry selection unit and outputting the selected operation result through the output end;
the low-order operation module comprises a hybrid adder according to any one of claims 1 to 4, and further comprises a low-order output terminal as the low 4 x (N +1) order output terminal of the high-efficiency hybrid adder, and a carry output terminal connected to the carry input terminal of the second carry selection unit for transmitting a carry signal to the second carry selection unit.
7. The high-efficiency hybrid adder according to claim 6, wherein the low order operation block further comprises a first control signal input, the high-efficiency hybrid adder configured to perform an addition operation when the input to the first control signal input is 0 and to perform a subtraction operation when the input to the first control signal input is 1.
8. The high-efficiency hybrid adder according to claim 7, further comprising: the mode selection unit is arranged between the low-order operation module and the second carry selection unit, the carry output end of the low-order operation module is connected to the input end of the mode selection unit, the output end of the mode selection unit is connected to the carry input end of the second carry selection unit, and the mode selection unit further comprises a mode selection input end and a second control signal input end;
the mode selection unit selects an output value of a low-order output end of the low-order operation module when the input of the mode selection input end is 1; or,
the mode selection unit selects an input value of the second control signal input terminal when an input of the mode selection input terminal is 0.
9. The high-efficiency hybrid adder according to claim 8, wherein if the input at the mode select input is 0, the low-order operation module is configured to perform an addition operation when the input at the first control signal input is 0 and a subtraction operation when the input at the first control signal input is 1, and the high-order operation module is configured to perform an addition operation when the input at the second control signal input is 0 and a subtraction operation when the input at the second control signal input is 1.
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