CN105511835A - Asynchronous FIFO controller and method for preventing asynchronous FIFO cache data overflow - Google Patents
Asynchronous FIFO controller and method for preventing asynchronous FIFO cache data overflow Download PDFInfo
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Abstract
Embodiments of the invention disclose an asynchronous FIFO controller and a method for preventing asynchronous FIFO cache data overflow. The method comprises: an asynchronous FIFO controller obtaining to-be-obtained data size of a second FIFO cache; the asynchronous FIFO controller obtaining the existed data size of the second FIFO cache; the asynchronous FIFO controller adding the to-be-obtained data size and the existed data size of the second FIFO cache, to obtain data total amount; the asynchronous FIFO controller comparing the data total amount with the depth of the second FIFO cache; and when the data total amount is not less than the depth of the second FIFO cache, the asynchronous FIFO controller sending a stop indication signal to a first FIFO cache.
Description
Technical field
The present invention relates to integrated circuit (IC, IntegratedCircuit) design field, particularly relate to a kind of asynchronous first-in first-out (FIFO, FirstInputFirstOutput) controller and prevent the method for the data cached spilling of asynchronous FIFO.
Background technology
In IC, often have multiple clock zone, asynchronous FIFO buffer memory, as a kind of effective method, is widely used in the signal transacting of cross clock domain.But asynchronous FIFO buffer memory needs all to be provided with its effect of interface guarantee realizing handshake mechanism in two clock zones.When the mechanism having a clock zone to have no idea to realize shaking hands, asynchronous FIFO buffer memory just has the risk of data from overflow.
The current disposal route for this problem is the degree of depth of increasing the 2nd FIFO buffer memory, guarantees that it can not overflow.But for the larger 2nd FIFO buffer memory of data bit wide, increasing depths can cause huge hardware spending.
Summary of the invention
For solving the problems of the technologies described above, the embodiment of the present invention provides a kind of asynchronous FIFO controller and prevents the method for the data cached spilling of asynchronous FIFO, while preventing the data cached spilling of asynchronous FIFO, can reduce hardware spending.
Technical scheme of the present invention is achieved in that
First aspect, embodiments provide a kind of asynchronous FIFO controller, described controller comprises: the first counter, the second counter, totalizer and comparer, wherein,
Described first counter, for obtaining the 2nd FIFO buffer memory data volume to be obtained; And by data transfers to be obtained for described 2nd FIFO buffer memory to described totalizer;
Described second counter, for obtaining already present data volume in described 2nd FIFO buffer memory; And by already present data transfers in described 2nd FIFO buffer memory to described totalizer;
Described totalizer, for data volume to be obtained for described 2nd FIFO buffer memory being added with already present data volume in described 2nd FIFO buffer memory, obtains data total amount; And described data total amount is transferred to described comparer;
Described comparer, for the degree of depth of described data total amount and described 2nd FIFO buffer memory is compared, when described data total amount is not less than the degree of depth of described 2nd FIFO buffer memory, send to a described FIFO buffer memory and stop indicator signal, wherein, described stopping indicator signal being used to indicate a described FIFO buffer memory stopping and exporting request signal.
Further, the first input end mouth of described first counter is connected with the request output terminal of a FIFO buffer memory, the request signal that the request output terminal for obtaining a FIFO buffer memory exports;
Second input port of described first counter is connected with the valid input end of described 2nd FIFO buffer memory, for obtaining the valid signal of the valid input end input of the 2nd FIFO buffer memory;
Described first counter, subtracts 1 during for adding 1 during by receiving request signal and receiving the valid signal of input, obtains the data volume that the 2nd FIFO buffer memory is to be obtained.
Further, the first input end mouth of described second counter can be connected with the valid input end of described 2nd FIFO buffer memory, for obtaining the valid signal of the valid input end input of the 2nd FIFO buffer memory;
Second input port of described second counter can be connected with the valid output terminal of described 2nd FIFO buffer memory, the valid signal that the valid output terminal for obtaining the 2nd FIFO buffer memory exports;
Described second counter, subtracts 1 during for adding 1 and receive the valid signal of output during valid signal by receiving input, obtains already present data volume in the 2nd FIFO buffer memory.
Further, described second counter is connected with the indicator register of described 2nd FIFO buffer memory, for obtaining already present data volume in the 2nd FIFO buffer memory from described indicator register.
Further, described second counter, the mode for the read-write pointer by reading described 2nd FIFO buffer memory obtains already present data volume in the 2nd FIFO buffer memory.
Further, described comparer, exports strobe signal for the request output terminal to a FIFO buffer memory, sends request signal to make a described FIFO buffer memory refusal to second clock territory.
Second aspect, embodiments provide a kind of method preventing the data cached spilling of asynchronous first-in first-out FIFO, described method comprises:
Asynchronous FIFO controller obtains the 2nd FIFO buffer memory data volume to be obtained;
Described asynchronous FIFO controller obtains already present data volume in described 2nd FIFO buffer memory;
Data volume to be obtained for described 2nd FIFO buffer memory is added with already present data volume in described 2nd FIFO buffer memory by described asynchronous FIFO controller, obtains data total amount;
The degree of depth of described data total amount and described 2nd FIFO buffer memory compares by described asynchronous FIFO controller;
When described data total amount is not less than the degree of depth of described 2nd FIFO buffer memory, described asynchronous FIFO controller sends to a FIFO buffer memory and stops indicator signal; Wherein, described stopping indicator signal being used to indicate a described FIFO buffer memory stopping and exporting request signal.
Further, described asynchronous FIFO controller obtains the 2nd FIFO buffer memory data volume to be obtained, comprising:
The request signal that the request output terminal that described asynchronous FIFO controller obtains a described FIFO buffer memory exports;
Described asynchronous FIFO controller obtains the valid signal of the valid input end input of described 2nd FIFO buffer memory;
Subtract 1 when adding 1 when described asynchronous FIFO controller is by receiving described request signal and receive the valid signal of described input, obtain the data volume that described 2nd FIFO buffer memory is to be obtained.
Further, described asynchronous FIFO controller obtains already present data volume in described 2nd FIFO buffer memory, comprising:
Described asynchronous FIFO controller obtains the valid signal of the valid input end input of described 2nd FIFO buffer memory;
The valid signal that the valid output terminal that described asynchronous FIFO controller obtains described 2nd FIFO buffer memory exports;
Subtract 1 when described asynchronous FIFO controller is by adding 1 and receive the valid signal of described output during the valid signal that receives described input, obtain already present data volume in described 2nd FIFO buffer memory.
Further, described asynchronous FIFO controller obtains already present data volume in described 2nd FIFO buffer memory, comprising:
Described asynchronous FIFO controller obtains already present data volume in described 2nd FIFO buffer memory from the indicator register of described 2nd FIFO buffer memory; Wherein, described indicator register comprises and is used to indicate already present data volume in described 2nd FIFO buffer memory.
Further, described asynchronous FIFO controller obtains already present data volume in described 2nd FIFO buffer memory, comprising:
Described asynchronous FIFO controller obtains already present data volume in described 2nd FIFO buffer memory by the read-write pointer reading described 2nd FIFO buffer memory.
Further, described asynchronous FIFO controller sends to a FIFO buffer memory and stops indicator signal, comprise: described asynchronous FIFO controller exports strobe signal to the request output terminal of a FIFO buffer memory, send request signal to make a FIFO buffer memory refusal to second clock territory.
Embodiments provide a kind of asynchronous FIFO controller and prevent the method for the data cached spilling of asynchronous FIFO, by fifo controller, the data total amount of existing data bulk and data bulk to be received in the 2nd FIFO buffer memory is counted, subsequently data total amount and the 2nd FIFO buffer memory degree of depth are compared, when data total amount is more than the 2nd FIFO buffer memory degree of depth, fifo controller stops a FIFO buffer memory and exports request request signal; Thus while preventing the data cached spilling of asynchronous FIFO, hardware spending can be reduced.
Accompanying drawing explanation
Fig. 1 is the structural representation of the asynchronous FIFO buffer memory of prior art;
The schematic diagram of a kind of asynchronous FIFO buffer structure that Fig. 2 provides for the embodiment of the present invention;
The structural representation of a kind of asynchronous FIFO controller that Fig. 3 provides for the embodiment of the present invention;
The structural representation of the another kind of asynchronous FIFO controller that Fig. 4 provides for the embodiment of the present invention;
The structural representation of another asynchronous FIFO controller that Fig. 5 provides for the embodiment of the present invention;
The structural representation of another asynchronous FIFO controller that Fig. 6 provides for the embodiment of the present invention;
A kind of method flow schematic diagram preventing the data cached spilling of asynchronous FIFO that Fig. 7 provides for the embodiment of the present invention;
The method flow schematic diagram of the data volume that a kind of asynchronous FIFO controller acquisition the 2nd FIFO buffer memory that Fig. 8 provides for the embodiment of the present invention is to be obtained;
Fig. 9 obtains the method flow schematic diagram of already present data volume in the 2nd FIFO buffer memory for a kind of asynchronous FIFO controller that the embodiment of the present invention provides.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described.
Basic thought of the present invention is: by counting the data total amount of existing data bulk and data bulk to be received in the 2nd FIFO buffer memory, subsequently data total amount and the 2nd FIFO buffer memory degree of depth are compared, make when data total amount is more than the 2nd FIFO buffer memory degree of depth, stop the 2nd FIFO buffer memory and receive data, thus make just can realize by counter and comparer the spilling that prevents asynchronous FIFO data cached, reduce hardware spending compared to the mode strengthening the 2nd FIFO degree of depth in prior art.
The structure of the asynchronous FIFO buffer memory of prior art shown in Figure 1, comprises the first clock zone, second clock territory, a FIFO buffer memory and the 2nd FIFO buffer memory.Wherein, a FIFO buffer memory is process address tunnel (such as address, request and ready), the 2nd FIFO caching process data channel (such as data and valid).
When the 2nd FIFO buffer memory do not possess realize handshake mechanism time, while the first clock zone sends request, address address passes to second clock territory from the first clock zone through a FIFO buffer memory.Through several all after dates, data data sends to the first clock zone from second clock territory by the 2nd FIFO buffer memory, and data pass simultaneously only have a data effective index signal valid.The receiver module of the first clock zone side generally can be designed to directly receive data, eliminates link of shaking hands.
Above-mentioned processing procedure can cause, and no matter whether the 2nd FIFO buffer memory fills up in second clock territory, all data can be passed to the 2nd FIFO buffer memory, if the data of the 2nd FIFO buffer memory are not taken out by the first clock zone in time, the 2nd FIFO buffer memory will data from overflow.
In the prior art shown in Fig. 1 the structure of asynchronous FIFO buffer memory basis on, see Fig. 2, it illustrates the structure of a kind of asynchronous FIFO buffer memory that the embodiment of the present invention provides, Fig. 2 compared to Figure 1 comparatively, adds fifo controller.
Composition graphs 2, see Fig. 3, it illustrates the structure of a kind of asynchronous FIFO controller 30 that the embodiment of the present invention provides, asynchronous FIFO controller 30 can comprise: the first counter 301, second counter 302, totalizer 303 and comparer 304,
Wherein, described first counter 301, for obtaining the 2nd FIFO buffer memory data volume to be obtained; And by data transfers to be obtained for described 2nd FIFO buffer memory to described totalizer 303;
Described second counter 302, for obtaining already present data volume in described 2nd FIFO buffer memory; And by already present data transfers in described 2nd FIFO buffer memory to described totalizer 303;
Described totalizer 303, for data volume to be obtained for described 2nd FIFO buffer memory being added with already present data volume in described 2nd FIFO buffer memory, obtains data total amount; And described data total amount is transferred to described comparer 304;
Described comparer 304, for the degree of depth of described data total amount and described 2nd FIFO buffer memory is compared, when described data total amount is not less than the degree of depth of described 2nd FIFO buffer memory, send to a described FIFO buffer memory and stop indicator signal, wherein, described stopping indicator signal being used to indicate a described FIFO buffer memory stopping and exporting request signal.
It should be noted that, owing to considering in the process of conventional asynchronous FIFO caching process, second time domain is after the request receiving very first time territory, need after several cycles, just send data to the 2nd FIFO buffer memory, therefore, the embodiment of the present invention is when determining whether the data in the 2nd FIFO buffer memory reach the 2nd FIFO buffer memory degree of depth, the second time domain several cycles after the request receiving very first time territory are needed just to send to the data to be received of the 2nd FIFO buffer memory to consider, therefore, fifo controller 30 obtains the data to be received of the 2nd FIFO buffer memory by the first counter 301.
Exemplarily, as shown in Figure 4, the first input end mouth of described first counter 301 can be connected with the request output terminal of a FIFO buffer memory, the request signal that the request output terminal obtaining a FIFO buffer memory exports; Second input port of described first counter 301 can be connected with the valid input end of described 2nd FIFO buffer memory, obtains the valid signal of the valid input end input of the 2nd FIFO buffer memory; Subtract 1 when adding 1 when the first counter 301 is by receiving request signal and receive the valid signal of input, obtain the data volume that the 2nd FIFO buffer memory is to be obtained;
It should be noted that, for the acquisition of already present data volume in the 2nd FIFO buffer memory, need the obtain manner deciding the second counter 302 according to the concrete structure of the 2nd FIFO buffer memory;
Alternatively, see Fig. 4, the first input end mouth of described second counter 302 can be connected with the valid input end of described 2nd FIFO buffer memory, obtains the valid signal of the valid input end input of the 2nd FIFO buffer memory; Second input port of described second counter 302 can be connected with the valid output terminal of described 2nd FIFO buffer memory, the valid signal that the valid output terminal obtaining the 2nd FIFO buffer memory exports; Subtract 1 during by adding 1 and receive the valid signal of output during the valid signal that receives input, obtain already present data volume in the 2nd FIFO buffer memory;
Alternatively, when the 2nd FIFO buffer memory comprises the indicator register being used to indicate self already present data volume, except the mode shown in Fig. 4, see Fig. 5, described second counter 302 can also be connected with the indicator register of described 2nd FIFO buffer memory, and obtains already present data volume in the 2nd FIFO buffer memory from described indicator register;
Alternatively, when having read-write pointer in the 2nd FIFO buffer memory, except the mode shown in Fig. 4, see Fig. 6, described second counter 302 can also obtain already present data volume in the 2nd FIFO buffer memory by the mode of the read-write pointer reading described 2nd FIFO buffer memory.
Exemplarily, when described data total amount is not less than the degree of depth of described 2nd FIFO buffer memory, comparer 304 can export strobe signal to the request output terminal of a FIFO buffer memory, request signal is sent to second clock territory to make a FIFO buffer memory refusal, and then can make second clock territory stop at some cycles after the 2nd FIFO buffer memory described in subtend send data, thus ensure that the data in the 2nd FIFO buffering can not be overflowed.
In sum, because counter, totalizer and comparer will be less than the hardware spending required for increasing the 2nd FIFO buffer memory degree of depth out and away in device expense, therefore, the asynchronous FIFO controller 30 that the present embodiment provides while preventing the data cached spilling of asynchronous FIFO, can reduce hardware spending.
Embodiments provide a kind of asynchronous FIFO controller 30, respectively the data total amount of existing data bulk in the 2nd FIFO buffer memory data bulk to be received and the 2nd FIFO buffer memory is counted by the first counter 301 and the second counter 302, subsequently data total amount and the 2nd FIFO buffer memory degree of depth are compared, when data total amount is more than the 2nd FIFO buffer memory degree of depth, asynchronous FIFO controller stops a FIFO buffer memory and exports request request signal; Thus while preventing the data cached spilling of asynchronous FIFO, hardware spending can be reduced.
Based on the technical conceive that previous embodiment is identical, see Fig. 7, it illustrates a kind of method flow preventing the data cached spilling of asynchronous FIFO that the embodiment of the present invention provides, the method can be applied to asynchronous FIFO controller as shown in Figure 3, and the method can comprise:
S701: asynchronous FIFO controller obtains the 2nd FIFO buffer memory data volume to be obtained;
S702: asynchronous FIFO controller obtains already present data volume in described 2nd FIFO buffer memory;
S703: data volume to be obtained for described 2nd FIFO buffer memory is added with already present data volume in described 2nd FIFO buffer memory by asynchronous FIFO controller, obtains data total amount;
S704: the degree of depth of described data total amount and the 2nd FIFO buffer memory compares by asynchronous FIFO controller;
S705: when described data total amount is not less than the degree of depth of described 2nd FIFO buffer memory, asynchronous FIFO controller sends to a described FIFO buffer memory and stops indicator signal;
Wherein, stop indicator signal being used to indicate a described FIFO buffer memory to stop exporting request signal.
It should be noted that, owing to considering in the process of conventional asynchronous FIFO caching process, second time domain is after the request receiving very first time territory, need after several cycles, just send data to the 2nd FIFO buffer memory, therefore, the embodiment of the present invention, when determining whether the data in the 2nd FIFO buffer memory reach the 2nd FIFO buffer memory degree of depth, needs the second time domain several cycles after the request receiving very first time territory just to send to the data to be received of the 2nd FIFO buffer memory to consider.
Exemplarily, see Fig. 8, step S701 specifically can comprise:
S7011a: asynchronous FIFO controller is connected with the request output terminal of a FIFO buffer memory, the request signal that the request output terminal obtaining a FIFO buffer memory exports;
S7011b: asynchronous FIFO controller is connected with the valid input end of described 2nd FIFO buffer memory, obtains the valid signal of the valid input end input of the 2nd FIFO buffer memory;
S7012: subtract 1 when adding 1 when asynchronous FIFO controller is by receiving request signal and receive the valid signal of input, obtains the data volume that the 2nd FIFO buffer memory is to be obtained;
It should be noted that, step S702 needs to decide according to the concrete structure of the 2nd FIFO buffer memory, present embodiments provides following concrete mode:
Alternatively, see Fig. 9, step S702 specifically can comprise:
S7021a: asynchronous FIFO controller is connected with the valid input end of described 2nd FIFO buffer memory, obtains the valid signal of the valid input end input of the 2nd FIFO buffer memory;
S7021b: asynchronous FIFO controller is connected with the valid output terminal of described 2nd FIFO buffer memory, the valid signal that the valid output terminal obtaining the 2nd FIFO buffer memory exports;
S7022: subtract 1 when asynchronous FIFO controller is by adding 1 and receive the valid signal of output during the valid signal that receives input, obtains already present data volume in the 2nd FIFO buffer memory;
Alternatively, when the 2nd FIFO buffer memory comprises the indicator register being used to indicate self already present data volume, except the mode described in Fig. 9, step S702 is specifically as follows: asynchronous FIFO controller is connected with the indicator register of described 2nd FIFO buffer memory, and obtains already present data volume in the 2nd FIFO buffer memory from described indicator register;
Alternatively, when having read-write pointer in the 2nd FIFO buffer memory, except the mode described in Fig. 9, step S702 is specifically as follows: asynchronous FIFO controller obtains already present data volume in the 2nd FIFO buffer memory by the read-write pointer reading described 2nd FIFO buffer memory.
Exemplarily, when described data total amount is not less than the degree of depth of described 2nd FIFO buffer memory, described asynchronous FIFO controller sends to a FIFO buffer memory and stops indicator signal specifically can comprising: asynchronous FIFO controller exports strobe signal to the request output terminal of a FIFO buffer memory, request signal is sent to second clock territory to make a FIFO buffer memory refusal, and then can make second clock territory stop at some cycles after the 2nd FIFO buffer memory described in subtend send data, thus ensure that the data in the 2nd FIFO buffering can not be overflowed.
Embodiments provide a kind of method preventing the data cached spilling of asynchronous FIFO, by fifo controller, the data total amount of existing data bulk and data bulk to be received in the 2nd FIFO buffer memory is counted, subsequently data total amount and the 2nd FIFO buffer memory degree of depth are compared, when data total amount is more than the 2nd FIFO buffer memory degree of depth, fifo controller stops a FIFO buffer memory and exports request request signal; Thus while preventing the data cached spilling of asynchronous FIFO, hardware spending can be reduced.
Those skilled in the art should understand, embodiments of the invention can be provided as method, system or computer program.Therefore, the present invention can adopt the form of hardware embodiment, software implementation or the embodiment in conjunction with software and hardware aspect.And the present invention can adopt in one or more form wherein including the upper computer program implemented of computer-usable storage medium (including but not limited to magnetic disk memory and optical memory etc.) of computer usable program code.
The present invention describes with reference to according to the process flow diagram of the method for the embodiment of the present invention, equipment (system) and computer program and/or block scheme.Should understand can by the combination of the flow process in each flow process in computer program instructions realization flow figure and/or block scheme and/or square frame and process flow diagram and/or block scheme and/or square frame.These computer program instructions can being provided to the processor of multi-purpose computer, special purpose computer, Embedded Processor or other programmable data processing device to produce a machine, making the instruction performed by the processor of computing machine or other programmable data processing device produce device for realizing the function of specifying in process flow diagram flow process or multiple flow process and/or block scheme square frame or multiple square frame.
These computer program instructions also can be stored in can in the computer-readable memory that works in a specific way of vectoring computer or other programmable data processing device, the instruction making to be stored in this computer-readable memory produces the manufacture comprising command device, and this command device realizes the function of specifying in process flow diagram flow process or multiple flow process and/or block scheme square frame or multiple square frame.
These computer program instructions also can be loaded in computing machine or other programmable data processing device, make on computing machine or other programmable devices, to perform sequence of operations step to produce computer implemented process, thus the instruction performed on computing machine or other programmable devices is provided for the step realizing the function of specifying in process flow diagram flow process or multiple flow process and/or block scheme square frame or multiple square frame.
The above, be only preferred embodiment of the present invention, be not intended to limit protection scope of the present invention.
Claims (12)
1. an asynchronous FIFO controller, is characterized in that, described controller comprises: the first counter, the second counter, totalizer and comparer, wherein,
Described first counter, for obtaining the 2nd FIFO buffer memory data volume to be obtained; And by data transfers to be obtained for described 2nd FIFO buffer memory to described totalizer;
Described second counter, for obtaining already present data volume in described 2nd FIFO buffer memory; And by already present data transfers in described 2nd FIFO buffer memory to described totalizer;
Described totalizer, for data volume to be obtained for described 2nd FIFO buffer memory being added with already present data volume in described 2nd FIFO buffer memory, obtains data total amount; And described data total amount is transferred to described comparer;
Described comparer, for the degree of depth of described data total amount and described 2nd FIFO buffer memory is compared, when described data total amount is not less than the degree of depth of described 2nd FIFO buffer memory, send to a described FIFO buffer memory and stop indicator signal, wherein, described stopping indicator signal being used to indicate a described FIFO buffer memory stopping and exporting request signal.
2. controller according to claim 1, is characterized in that, the first input end mouth of described first counter is connected with the request output terminal of a FIFO buffer memory, the request signal that the request output terminal for obtaining a FIFO buffer memory exports;
Second input port of described first counter is connected with the valid input end of described 2nd FIFO buffer memory, for obtaining the valid signal of the valid input end input of the 2nd FIFO buffer memory;
Described first counter, subtracts 1 during for adding 1 during by receiving request signal and receiving the valid signal of input, obtains the data volume that the 2nd FIFO buffer memory is to be obtained.
3. controller according to claim 2, is characterized in that, the first input end mouth of described second counter can be connected with the valid input end of described 2nd FIFO buffer memory, for obtaining the valid signal of the valid input end input of the 2nd FIFO buffer memory;
Second input port of described second counter can be connected with the valid output terminal of described 2nd FIFO buffer memory, the valid signal that the valid output terminal for obtaining the 2nd FIFO buffer memory exports;
Described second counter, subtracts 1 during for adding 1 and receive the valid signal of output during valid signal by receiving input, obtains already present data volume in the 2nd FIFO buffer memory.
4. controller according to claim 2, is characterized in that, described second counter is connected with the indicator register of described 2nd FIFO buffer memory, for obtaining already present data volume in the 2nd FIFO buffer memory from described indicator register.
5. controller according to claim 2, is characterized in that, described second counter, and the mode for the read-write pointer by reading described 2nd FIFO buffer memory obtains already present data volume in the 2nd FIFO buffer memory.
6. the controller according to any one of claim 1 to 5, it is characterized in that, described comparer, exports strobe signal for the request output terminal to a FIFO buffer memory, sends request signal to make a described FIFO buffer memory refusal to second clock territory.
7. prevent a method for the data cached spilling of asynchronous first-in first-out FIFO, it is characterized in that, described method comprises:
Asynchronous FIFO controller obtains the 2nd FIFO buffer memory data volume to be obtained;
Described asynchronous FIFO controller obtains already present data volume in described 2nd FIFO buffer memory;
Data volume to be obtained for described 2nd FIFO buffer memory is added with already present data volume in described 2nd FIFO buffer memory by described asynchronous FIFO controller, obtains data total amount;
The degree of depth of described data total amount and described 2nd FIFO buffer memory compares by described asynchronous FIFO controller;
When described data total amount is not less than the degree of depth of described 2nd FIFO buffer memory, described asynchronous FIFO controller sends to a FIFO buffer memory and stops indicator signal; Wherein, described stopping indicator signal being used to indicate a described FIFO buffer memory stopping and exporting request signal.
8. method according to claim 7, is characterized in that, described asynchronous FIFO controller obtains the 2nd FIFO buffer memory data volume to be obtained, comprising:
The request signal that the request output terminal that described asynchronous FIFO controller obtains a described FIFO buffer memory exports;
Described asynchronous FIFO controller obtains the valid signal of the valid input end input of described 2nd FIFO buffer memory;
Subtract 1 when adding 1 when described asynchronous FIFO controller is by receiving described request signal and receive the valid signal of described input, obtain the data volume that described 2nd FIFO buffer memory is to be obtained.
9. method according to claim 8, is characterized in that, described asynchronous FIFO controller obtains already present data volume in described 2nd FIFO buffer memory, comprising:
Described asynchronous FIFO controller obtains the valid signal of the valid input end input of described 2nd FIFO buffer memory;
The valid signal that the valid output terminal that described asynchronous FIFO controller obtains described 2nd FIFO buffer memory exports;
Subtract 1 when described asynchronous FIFO controller is by adding 1 and receive the valid signal of described output during the valid signal that receives described input, obtain already present data volume in described 2nd FIFO buffer memory.
10. method according to claim 8, is characterized in that, described asynchronous FIFO controller obtains already present data volume in described 2nd FIFO buffer memory, comprising:
Described asynchronous FIFO controller obtains already present data volume in described 2nd FIFO buffer memory from the indicator register of described 2nd FIFO buffer memory; Wherein, described indicator register comprises and is used to indicate already present data volume in described 2nd FIFO buffer memory.
11. methods according to claim 8, is characterized in that, described asynchronous FIFO controller obtains already present data volume in described 2nd FIFO buffer memory, comprising:
Described asynchronous FIFO controller obtains already present data volume in described 2nd FIFO buffer memory by the read-write pointer reading described 2nd FIFO buffer memory.
12. methods according to any one of claim 7 to 11, it is characterized in that, described asynchronous FIFO controller sends to a FIFO buffer memory and stops indicator signal, comprise: described asynchronous FIFO controller exports strobe signal to the request output terminal of a FIFO buffer memory, send request signal to make a FIFO buffer memory refusal to second clock territory.
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| PCT/CN2015/071669 WO2016045288A1 (en) | 2014-09-24 | 2015-01-27 | Asynchronous fifo controller and method for preventing data overflow of asynchronous fifo buffer |
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| CN111367495A (en) * | 2020-03-06 | 2020-07-03 | 电子科技大学 | Asynchronous first-in first-out data cache controller |
| CN115904307A (en) * | 2023-03-08 | 2023-04-04 | 鹏城实验室 | Data buffer overflow processing method and communication system |
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| CN101907986B (en) * | 2010-08-30 | 2013-11-06 | 威盛电子股份有限公司 | Data processing equipment and data processing method accessing multiple memories |
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| US20010017860A1 (en) * | 2000-02-29 | 2001-08-30 | Hajime Hata | Communication control device and method |
| US20040148467A1 (en) * | 2003-01-16 | 2004-07-29 | Ip-First, Llc. | Microprocessor and apparatus for performing fast speculative pop operation from a stack memory cache |
| CN101110259A (en) * | 2007-08-22 | 2008-01-23 | 威盛电子股份有限公司 | First-in first-out memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110188059A (en) * | 2019-05-17 | 2019-08-30 | 西安微电子技术研究所 | The flow control type FIFO buffer structure and method of the unified configuration of data valid bit |
| CN110188059B (en) * | 2019-05-17 | 2020-10-27 | 西安微电子技术研究所 | Flow control type FIFO (first in first out) cache device and method for unified configuration of data valid bits |
| CN111367495A (en) * | 2020-03-06 | 2020-07-03 | 电子科技大学 | Asynchronous first-in first-out data cache controller |
| CN111367495B (en) * | 2020-03-06 | 2023-03-28 | 电子科技大学 | Asynchronous first-in first-out data cache controller |
| CN115904307A (en) * | 2023-03-08 | 2023-04-04 | 鹏城实验室 | Data buffer overflow processing method and communication system |
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| WO2016045288A1 (en) | 2016-03-31 |
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