CN105511347A - System and method for simulating information acquisition process of I2C bus by means of FPGA - Google Patents
System and method for simulating information acquisition process of I2C bus by means of FPGA Download PDFInfo
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- CN105511347A CN105511347A CN201510873367.9A CN201510873367A CN105511347A CN 105511347 A CN105511347 A CN 105511347A CN 201510873367 A CN201510873367 A CN 201510873367A CN 105511347 A CN105511347 A CN 105511347A
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- information
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- slave
- main control
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25314—Modular structure, modules
Abstract
The invention discloses a system and a method for simulating the information acquisition process of an I2C bus by means of an FPGA, and relates to the technical field of the information acquisition and transmission of routing and switching equipment. The system comprises an information transmission module, an acquisition control module, an information acquisition module and I2C interface control modules, wherein the functions of the above modules are realized by the FPGA. When a master control device needs to acquire the status information of a slave device, the acquisition control module controls the information acquisition module to invoke the I2C interface control modules to acquire the status information of the slave device. Meanwhile, the information acquisition module sends the status information of the slave device to the information transmission module. The information transmission module uploads the status information acquired by the information acquisition module to the master control device. According to the technical scheme of the invention, the status information uploading period of the slave device is shortened, and the switching efficiency of routing and switching equipment is improved. Meanwhile, the status information acquisition process of the slave device is simplified. The FPGA parameters of each module can be configured by the master control device. Therefore, the system and the method are wide in application range.
Description
Technical field
The present invention relates to the acquisition of information Transfer Technology field of route exchange device, be specifically related to a kind of by FPGA Simulation with I
2c bus carries out the system and method for acquisition of information.
Background technology
Along with the development of the communication technology, the performance requirement of people to route-exchanging device improves constantly.Route-exchanging device often has multiple from equipment or from device, main control equipment interrogates each slave (from equipment or from device), to realize the object of the status information obtaining slave in time by CPU wheel.
But, due to from equipment or the uncertainty from device state, therefore the software resource that takies of the numerous uncertain slave of CPU wheel news is more, and the acquisition cycle of the status information of single slave is longer, CPU obtains at every turn and all can take whole cpu i/f, route exchange device to switch efficiency lower.
Summary of the invention
For the defect existed in prior art, the technical matters that the present invention solves is: shortening slave status information calls time, and that improves route exchange device switches efficiency, simplifies the acquisition process of slave status information.The present invention can configure the FPGA parameter of each module by main control equipment, the scope of application is more extensive.
For reaching above object, provided by the invention by FPGA Simulation with I
2c bus carries out the system of acquisition of information, and described system comprises the information transfer module, acquisition control module, information acquisition module and at least 1 I that are realized by FPGA
2c interface control module; Information transfer module, acquisition control module all communicate with the main control equipment of route-exchanging device, and acquisition control module communicates with information acquisition module, information acquisition module respectively with all I
2c interface control module communicates;
Described acquisition control module is used for: when main control equipment needs to obtain the status information of slave, send the collection request enable signal obtaining corresponding slave to information acquisition module;
Described information acquisition module is used for: receive after gathering request enable signal, call I
2c interface control module works, and extracts I
2the status information that C interface control module obtains, sends status information to information transfer module;
Described I
2c interface control module is used for: Simulation with I
2c bus controller, provides and passes through I to slave
2c bus carries out the interactive interface of condition managing information, initiates read-write operation to slave, obtains the status information of slave;
Described information transfer module is used for: the status information that information acquisition module obtains is uploaded to main control equipment.
On the basis of technique scheme, described information acquisition module extracts I
2during the status information that C interface control module obtains, arrange and obtain complement mark and be sent completely mark to information transfer module; Described information transfer module specifically for: store information acquisition module send status information, by interrupt or SM set mode refresh obtain complement mark, with notify main control equipment upgrade current state information; After receiving the response of main control equipment, the status information that information acquisition module obtains is uploaded to main control equipment.
On the basis of technique scheme, described acquisition control module is used for: when described main control equipment needs periodically obtain the status information of slave, sends according to timing cycle length the collection request enable signal obtaining slave to information acquisition module.
Provided by the invention based on said system by FPGA Simulation with I
2c bus carries out the method for acquisition of information, and the method comprises the following steps:
S1: when main control equipment needs to obtain the status information of slave, calls acquisition control module and sends the collection request enable signal obtaining corresponding slave to information acquisition module, forward S2 to;
S2: information acquisition module calls the I be connected with corresponding slave after receiving and gathering request enable signal
2c interface control module, current I
2c interface control module initiates read-write operation to corresponding slave, obtains the status information of slave, forwards S3 to;
S3: information acquisition module extracts I
2the status information that C interface control module obtains, current state information is sent to main control equipment by information transfer die, and current state information is updated to the status information of corresponding slave by main control equipment, terminates.
On the basis of technique scheme, S3 specifically comprises the following steps:
S301: information acquisition module extracts I
2the status information that C interface control module obtains, arranges acquisition complement mark, status information and acquisition complement mark is sent to information transfer module, forwards S302 to;
S302: after information transfer module storaging state information, by interrupting or SM set mode refreshing acquisition complement mark, to notify that main control equipment upgrades current state information; After information transfer module receives the response of main control equipment, current state information is uploaded to main control equipment, main control equipment reads current state information and after current state information being updated to the status information of corresponding slave, removes the complement mark of the refreshing in information transfer module.
On the basis of technique scheme, main control equipment described in S1 needs the situation of status information obtaining slave to be: main control equipment learns slave initialization, needs the work state information obtaining all slaves.
On the basis of technique scheme, main control equipment described in S1 needs the situation of status information obtaining slave to be: when main control equipment learns that slave state changes, need the status information upgrading the slave changed.
On the basis of technique scheme, main control equipment described in S1 needs the situation of status information obtaining slave to be: main control equipment needs the status information of periodic refresh slave, and now acquisition control module described in S1 sends according to timing cycle length the collection request enable signal obtaining corresponding slave to information acquisition module.
Compared with prior art, the invention has the advantages that:
(1) taken turns by CPU with main control equipment in prior art and interrogate compared with each slave, of the present invention by FPGA Simulation with I
2c bus carries out the system of acquisition of information, and between main control equipment and slave, main control equipment does not need directly to be connected to multiple slave.Therefore, when system of the present invention obtains the status information of slave, without the need to specifically carrying out interface emulates, only simple register configuration operation need be carried out by FPGA to module each in system; Meanwhile, the CPU of main control equipment also without the need to carrying out concrete operation, CPU only needs more new state information or receive FPGA request time, status information is processed.
In view of this, the software resource that the present invention can take at CPU is less, the state of each slave of monitoring in real time, when state changes by FPGA Simulation with I
2c interface control module carries out collection and the management of slave status information, can not only shorten slave status information on call time, that improves route exchange device switches efficiency, and operating process is fairly simple, is convenient to people and uses.
(2), when system of the present invention uses, the FPGA parameter of each module can be configured by main control equipment, such as, configure the I communicated with according to different slaves
2the parameter of C interface control module, the scope of application is more extensive.
Accompanying drawing explanation
Fig. 1 is by FPGA Simulation with I in the embodiment of the present invention
2c bus carries out the structured flowchart of the system of acquisition of information.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.
Shown in Figure 1, in the embodiment of the present invention by FPGA Simulation with I
2c bus carries out the system of acquisition of information, comprises the information transfer module, acquisition control module, information acquisition module and at least 1 I that are realized by FPGA (Field-ProgrammableGateArray, field programmable gate array)
2c interface control module; Information transfer module, acquisition control module all communicate with the main control equipment of route-exchanging device, and acquisition control module communicates with information acquisition module, information acquisition module respectively with all I
2c interface control module communicates.
Acquisition control module is used for: when main control equipment needs the status information obtaining slave (from equipment or from device), send obtain the collection request enable signal of corresponding slave to information acquisition module; When main control equipment needs periodicity to obtain the status information of slave, send according to timing cycle length the collection request enable signal obtaining slave to information acquisition module.
Information acquisition module is used for: receive after gathering request enable signal, call I
2c interface control module works, and extracts I
2the status information that C interface control module obtains, sends status information to information transfer module.
I
2c interface control module is used for: Simulation with I
2c bus controller, provides and passes through I to slave
2c bus carries out the interactive interface of condition managing information, initiates read-write operation to slave, obtains the status information of slave.
Information transfer module is used for: the status information that information acquisition module obtains is uploaded to main control equipment.
Information acquisition module extracts I
2during the status information that C interface control module obtains, arrange and obtain complement mark and be sent completely mark to information transfer module.Information transfer module specifically for: store information acquisition module send status information, by interrupt or SM set mode refresh obtain complement mark, with notify main control equipment upgrade current state information; After receiving the response of main control equipment, the status information that information acquisition module obtains is uploaded to main control equipment.
In the embodiment of the present invention based on said system by FPGA Simulation with I
2c bus carries out the method for acquisition of information, comprises the following steps:
S1: when main control equipment needs to obtain the status information of slave, calls acquisition control module and sends the collection request enable signal obtaining corresponding slave to information acquisition module, forward S2 to.
S2: information acquisition module calls the I be connected with corresponding slave after receiving and gathering request enable signal
2c interface control module, current I
2c interface control module initiates read-write operation to corresponding slave, obtains the status information of slave, forwards S3 to.
S3: information acquisition module extracts I
2the status information that C interface control module obtains, current state information is sent to main control equipment by information transfer die, and current state information is updated to the status information of corresponding slave by main control equipment, terminates.
S3 specifically comprises the following steps:
S301: information acquisition module extracts I
2the status information that C interface control module obtains, arranges acquisition complement mark, status information and acquisition complement mark is sent to information transfer module, forwards S302 to.
S302: after information transfer module storaging state information, by interrupting or SM set mode refreshing acquisition complement mark, to notify that main control equipment upgrades current state information.After information transfer module receives the response of main control equipment, current state information is uploaded to main control equipment, main control equipment reads current state information and after current state information being updated to the status information of corresponding slave, removes the complement mark of the refreshing in information transfer module.
In S1, main control equipment needs the situation of the status information obtaining slave to comprise following 4 kinds: 1, main control equipment learns slave initialization, needs the work state information obtaining all slaves; 2, when main control equipment learns that slave state changes, the status information upgrading the slave changed is needed; 3, main control equipment needs the status information of periodic refresh slave; 4, other particular/special requirements of main control equipment.
In S1, main control equipment needs the situation of status information obtaining slave to be main control equipment when needing the status information of periodic refresh slave, and acquisition control module sends according to timing cycle length the collection request enable signal obtaining corresponding slave to information acquisition module.
The present invention is not limited to above-mentioned embodiment, and for those skilled in the art, under the premise without departing from the principles of the invention, can also make some improvements and modifications, these improvements and modifications are also considered as within protection scope of the present invention.The content be not described in detail in this instructions belongs to the known prior art of professional and technical personnel in the field.
Claims (8)
1. one kind is passed through FPGA Simulation with I
2c bus carries out the system of acquisition of information, it is characterized in that, described system comprises the information transfer module, acquisition control module, information acquisition module and at least 1 I that are realized by FPGA
2c interface control module; Information transfer module, acquisition control module all communicate with the main control equipment of route-exchanging device, and acquisition control module communicates with information acquisition module, information acquisition module respectively with all I
2c interface control module communicates;
Described acquisition control module is used for: when main control equipment needs to obtain the status information of slave, send the collection request enable signal obtaining corresponding slave to information acquisition module;
Described information acquisition module is used for: receive after gathering request enable signal, call I
2c interface control module works, and extracts I
2the status information that C interface control module obtains, sends status information to information transfer module;
Described I
2c interface control module is used for: Simulation with I
2c bus controller, provides and passes through I to slave
2c bus carries out the interactive interface of condition managing information, initiates read-write operation to slave, obtains the status information of slave;
Described information transfer module is used for: the status information that information acquisition module obtains is uploaded to main control equipment.
2. as claimed in claim 1 by FPGA Simulation with I
2c bus carries out the system of acquisition of information, it is characterized in that: described information acquisition module extracts I
2during the status information that C interface control module obtains, arrange and obtain complement mark and be sent completely mark to information transfer module; Described information transfer module specifically for: store information acquisition module send status information, by interrupt or SM set mode refresh obtain complement mark, with notify main control equipment upgrade current state information; After receiving the response of main control equipment, the status information that information acquisition module obtains is uploaded to main control equipment.
3. as claimed in claim 1 or 2 by FPGA Simulation with I
2c bus carries out the system of acquisition of information, it is characterized in that, described acquisition control module is used for: when described main control equipment needs periodically obtain the status information of slave, sends according to timing cycle length the collection request enable signal obtaining slave to information acquisition module.
4. one kind based on system described in any one of claims 1 to 3 by FPGA Simulation with I
2c bus carries out the method for acquisition of information, it is characterized in that, the method comprises the following steps:
S1: when main control equipment needs to obtain the status information of slave, calls acquisition control module and sends the collection request enable signal obtaining corresponding slave to information acquisition module, forward S2 to;
S2: information acquisition module calls the I be connected with corresponding slave after receiving and gathering request enable signal
2c interface control module, current I
2c interface control module initiates read-write operation to corresponding slave, obtains the status information of slave, forwards S3 to;
S3: information acquisition module extracts I
2the status information that C interface control module obtains, current state information is sent to main control equipment by information transfer die, and current state information is updated to the status information of corresponding slave by main control equipment, terminates.
5. as claimed in claim 4 by FPGA Simulation with I
2c bus carries out the method for acquisition of information, it is characterized in that, S3 specifically comprises the following steps:
S301: information acquisition module extracts I
2the status information that C interface control module obtains, arranges acquisition complement mark, status information and acquisition complement mark is sent to information transfer module, forwards S302 to;
S302: after information transfer module storaging state information, by interrupting or SM set mode refreshing acquisition complement mark, to notify that main control equipment upgrades current state information; After information transfer module receives the response of main control equipment, current state information is uploaded to main control equipment, main control equipment reads current state information and after current state information being updated to the status information of corresponding slave, removes the complement mark of the refreshing in information transfer module.
6. as claimed in claim 4 by FPGA Simulation with I
2c bus carries out the method for acquisition of information, it is characterized in that: main control equipment described in S1 needs the situation of status information obtaining slave to be: main control equipment learns slave initialization, needs the work state information obtaining all slaves.
7. as claimed in claim 4 by FPGA Simulation with I
2c bus carries out the method for acquisition of information, it is characterized in that: main control equipment described in S1 needs the situation of status information obtaining slave to be: when main control equipment learns that slave state changes, need the status information upgrading the slave changed.
8. as claimed in claim 4 by FPGA Simulation with I
2c bus carries out the method for acquisition of information, it is characterized in that: main control equipment described in S1 needs the situation of status information obtaining slave to be: main control equipment needs the status information of periodic refresh slave, and now acquisition control module described in S1 sends according to timing cycle length the collection request enable signal obtaining corresponding slave to information acquisition module.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510873367.9A CN105511347A (en) | 2015-12-02 | 2015-12-02 | System and method for simulating information acquisition process of I2C bus by means of FPGA |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510873367.9A CN105511347A (en) | 2015-12-02 | 2015-12-02 | System and method for simulating information acquisition process of I2C bus by means of FPGA |
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Citations (5)
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|---|---|---|---|---|
| CN101788939A (en) * | 2009-01-22 | 2010-07-28 | 中兴通讯股份有限公司 | Controller status-monitoring device and method |
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| CN102841869A (en) * | 2012-07-03 | 2012-12-26 | 深圳市邦彦信息技术有限公司 | Multi-channel I2C controller based on FPGA |
| CN104333473A (en) * | 2014-11-20 | 2015-02-04 | 武汉烽火网络有限责任公司 | System and method for uniformly managing route switching device information interface |
| US20150288559A1 (en) * | 2014-04-03 | 2015-10-08 | Hitachi Metals, Ltd. | Relay System and Switching Device |
-
2015
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101788939A (en) * | 2009-01-22 | 2010-07-28 | 中兴通讯股份有限公司 | Controller status-monitoring device and method |
| CN102243619A (en) * | 2011-06-23 | 2011-11-16 | 天津光电通信技术有限公司 | FPGA (Field Programmable Gate Array)-based method for realizing multi-path I2C (Inter-Integrated Circuit) bus port expansion |
| CN102841869A (en) * | 2012-07-03 | 2012-12-26 | 深圳市邦彦信息技术有限公司 | Multi-channel I2C controller based on FPGA |
| US20150288559A1 (en) * | 2014-04-03 | 2015-10-08 | Hitachi Metals, Ltd. | Relay System and Switching Device |
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| Title |
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Application publication date: 20160420 |
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