CN105489756B - Preparation method based on the full limitation phase transition storage of level from selective etching - Google Patents
Preparation method based on the full limitation phase transition storage of level from selective etching Download PDFInfo
- Publication number
- CN105489756B CN105489756B CN201510881785.2A CN201510881785A CN105489756B CN 105489756 B CN105489756 B CN 105489756B CN 201510881785 A CN201510881785 A CN 201510881785A CN 105489756 B CN105489756 B CN 105489756B
- Authority
- CN
- China
- Prior art keywords
- phase
- layer
- horizontally
- change material
- preparation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Patterning of the switching material
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
A kind of preparation method of full limitation phase transition storage of level based on from selective etching proposed by the present invention, solves GST fillings difficulty and the problem of the dependence to chemically-mechanicapolish polishing (CMP) technique.Corrosion rate difference of the GeSbTe alloys in alkaline solution under crystalline state and amorphous state exceedes an order of magnitude, and only the GeSbTe alloy materials in horizontally-opposed electrode gap can be arranged into amorphous state by heating electrode pair GeSbTe alloys application electric pulse.So by corroding appropriate time in alkaline solution, GeSbTe alloy autoregistrations can be filled into horizontal electrode gap.It is simple for process, there is no the limitation in volume to the limitation phase transformation node to be prepared.The present invention realizes junior unit power consumption, big device functional reliability, compatible with existing CMOS technology for quick, has extraordinary commercial application prospect.
Description
Technical field
The present invention relates to micro ＆ nano technology field, more particularly to a kind of full limitation phase change memory of level based on from selective etching
The preparation method of device.
Background technology
Phase transition storage PCRAM (phase change random access memory) is using chalcogenide compound as storage
Medium, converted by the fuel factor control phase-change material of electric current between crystalline state (low-resistance) and amorphous state (high resistant) and realize information
Write-in and erasing, the reading of information is realized by the change of detection storage region resistance.PCRAM have it is non-volatile, it is and current
Most memory is compared, have device size is small, low in energy consumption, reading speed is fast, Flouride-resistani acid phesphatase, can realize multistage store and
Many advantages, such as compatible with existing CMOS technology, it is most possibly to substitute current FLASH and stored as following main flow
One of semiconductor nonvolatile memory.
At present, the main problem that PCRAM phase transition storages face is that operation electric current is excessive, the requirement to drive circuit compared with
Height, limit reduction, the lifting of storage speed and the raising of storage density of storage power consumption.Reduced in PCRAM volume production structure
One kind is to prepare smaller size of nanometer plug electrode in the method for effective phase variable volume；Another kind of method is to prepare phase transformation material
Expect restrictive, the volume that phase transformation is available for by reducing reduces effective phase variable volume.It is proposed by the present invention to be based on from selection
The preparation method of the full limitation phase transition storage of level of corrosion, on the one hand, closed using the GeSbTe being under crystalline state and amorphous state
Corrosion rate difference of the gold in alkaline solution exceedes the physics law of an order of magnitude, can pass through alkaline solution erosion removal
GeSbTe alloys under crystalline state, so as to realize the screening to GeSbTe alloy difference physics states corresponding region；On the other hand,
Can and only can be by the GeSbTe in horizontally-opposed electrode gap by heating electrode pair phase-change material application electric pulse
Alloy material is arranged to amorphous state, and by the screening of alkaline solution wet etching, this is self aligned preparation technology, and technique will
Ask low, there is no the limitation in volume to the limitation phase transformation node to be prepared, it is simple and easy to do.
To solve the above-mentioned problems in the prior art, the present invention proposes a kind of complete based on the level from selective etching
Limit the preparation method of phase transition storage.
The invention discloses a kind of preparation method of the full limitation phase transition storage of level based on from selective etching, this method
Including：
Step 1：On the substrate 101, the first electric insulating material layer 201 is deposited；
Step 2：On the first electric insulating material layer 201, water is prepared using the method for " photoetching-thin-film deposition-stripping "
Flat opposed electrode layer 301 and horizontally-opposed electrode gap 3011；
Step 3：On the first electric insulating material layer 201 and horizontally-opposed electrode layer 301 and horizontally-opposed electrode stitches
In gap 3011, phase-change material layers 401 are prepared using the method for " photoetching-thin-film deposition-stripping "；
Step 4：The first electric heating insulating barrier 201, horizontally-opposed electrode layer 301 and phase-change material layers 401 exposure it is upper
Surface, the second electric insulating material layer 202 is prepared using the method for " photoetching-thin-film deposition-stripping ", is passivated phase-change material layers
401 and expose the electrode tips 3012 of horizontally-opposed electrode layer 301；
Step 5：Anneal and electric pulse is applied to phase-change material layers 401 by electrode tips 3012, it is decrystallized to be located at water
Phase-change material layers 401 in flat opposite electrode gap 3011, and wet etching removes the second electric insulating material layer 202 successively,
Alkaline solution wet etching only retains the phase-change material node layer 4011 in horizontally-opposed electrode gap 3011；
Step 6：It is sudden and violent in the first electric insulating material layer 201, horizontally-opposed electrode layer 301 and phase-change material node layer 4011
On the surface of dew, the 3rd thermo electric material layer 203 is prepared using the method for " photoetching-thin-film deposition-stripping ", so as to be passivated device,
Device is completed to prepare.
On the one hand, using in corrosion rate difference in alkaline solution of crystalline state and amorphous state GeSbTe alloys more than one
The physics law of the individual order of magnitude, the GeSbTe alloys that can be in by alkaline solution erosion removal under crystalline state, so as to realize pair
The screening of GeSbTe alloy difference physics states corresponding region；On the other hand, electric pulse is applied by heating electrode pair phase-change material
GeSbTe alloy materials in horizontally-opposed electrode gap can and can be only arranged to amorphous state, and it is molten by alkalescence
The screening of liquid wet etching, this is self aligned preparation technology, and technological requirement is low, is not had to the limitation phase transformation node to be prepared
Limitation in volume, it is simple and easy to do.The present invention for it is quick realize junior unit power consumption, big device functional reliability, with it is existing
CMOS technology is compatible, has extraordinary commercial application prospect.
Brief description of the drawings
For the object, technical solutions and advantages of the present invention are more clearly understood, below in conjunction with specific embodiment, and reference
Accompanying drawing, the present invention is described in further detail, wherein：
Fig. 1 is the flow of the preparation method of the level full limitation phase transition storage provided by the invention based on from selective etching
Figure；
Fig. 2-7 is a kind of preparation method preparation technology schematic flow sheet of phase transition storage based on patterned substrate.
Embodiment
Refer to shown in Fig. 1, the present invention provides a kind of full limitation phase of level based on from selective etching proposed by the present invention
The preparation method of transition storage, solves the problem of difficult and to chemically mechanical polishing (CMP) technique the dependence of GST fillings.Place
Corrosion rate difference of the GeSbTe alloys in alkaline solution under crystalline state and amorphous state exceedes an order of magnitude.Pass through electric arteries and veins
GeSbTe alloy materials in horizontally-opposed electrode gap and only can be arranged to amorphous state by punching.So by
Corrode appropriate time in alkaline solution, GeSbTe alloy autoregistrations can be filled into horizontal electrode gap.
The present invention provides a kind of preparation method of the full limitation phase transition storage of level based on from selective etching, this method bag
Include：
Step 1：On the substrate 101, the first electric insulating material layer 201 is deposited；
Wherein, the effect of substrate 101 is that provider part prepares required physical support, and its material can be silicon, nitrogen
Change gallium, sapphire, carborundum or glass.
Wherein, the effect of the first electric insulating material layer 201 is the electric heating insulation environment needed during the work of provider part,
Silica prepared by silicon nitride and thermal oxidation process prepared by prioritizing selection LPCVD methods, its film features thickness is between 5 to 500
Nanometer.
Step 2：On the first electric insulating material layer 201, water is prepared using the method for " photoetching-thin-film deposition-stripping "
Flat opposed electrode layer 301 and horizontally-opposed electrode gap 3011；
Wherein, the effect of horizontally-opposed electrode layer 301 is to provide the control passage of the electric pulse required for phase transition process,
By being heated to phase-change material, induced phase transition process, its film features thickness is between 1 to 300 nanometers；
Wherein, the thickness of the area in horizontally-opposed electrode gap 3011 and the phase-change material layers of subsequent deposition directly affects
To the volume for the phase-change material node that can finally prepare, the feature size dimension in horizontally-opposed electrode gap 3011 arrives between 1
1000 nanometers.
Step 3：On the first electric insulating material layer 201 and horizontally-opposed electrode layer 301 and horizontally-opposed electrode stitches
In gap 3011, phase-change material layers 401 are prepared using the method for " photoetching-thin-film deposition-stripping "；
Step 4：The first electric heating insulating barrier 201, horizontally-opposed electrode layer 301 and phase-change material layers 401 exposure it is upper
Surface, the second electric insulating material layer 202 is prepared using the method for " photoetching-thin-film deposition-stripping ", is passivated phase-change material layers
401, and expose the electrode tips 3012 of horizontally-opposed electrode layer 301；
Wherein, the effect of the second electric insulating material layer 202 be passivated phase-change material layers, be follow-up annealing process and
The decrystallized phase-change material layers process in horizontally-opposed electrode gap 3011 of electric pulse does passivation protection, and its characteristic thickness is situated between
In 1 to 500 nanometers.
Step 5：Anneal and electric pulse is applied to phase-change material layers 401 by electrode tips 3012, it is decrystallized to be located at water
Phase-change material layers 401 in flat opposite electrode gap 3011, and wet etching removes the second electric insulating material layer 202 successively,
Alkaline solution wet etching only retains the phase-change material node layer 4011 in horizontally-opposed electrode gap 3011；
Wherein, initial crystalline of the phase-change material layers after preparation is mostly amorphous state, passes through more than 200 degrees Celsius quickly move back
Fire, which is handled, can uniformly be arranged to phase-change material layers crystalline state, and the phase-change material under crystalline state is soluble in alkaline solution.Pass through contact
Electrode tip 3012 applies electric pulse to phase-change material layers, can and only can be by the phase transformation material in horizontally-opposed electrode gap
Material is arranged to amorphous state.Second electric insulating material layer is first removed by solution (such as HF, BOE) wet etching, exposes phase transformation
Material layer, and the phase-change material in crystalline state is removed by alkaline solution (such as TMAH, KOH, NaOH) wet etching, formation is only located
It is confined in amorphous phase-change material in horizontally-opposed electrode gap, this is a self aligned preparation technology, simple to operate, weight
It is multiple reliable.
Step 6：It is sudden and violent in the first electric insulating material layer 201, horizontally-opposed electrode layer 301 and phase-change material node layer 4011
On the surface of dew, the 3rd thermo electric material layer 203 is prepared using the method for " photoetching-thin-film deposition-stripping ", so as to be passivated device,
Device is completed to prepare.
Wherein, the effect of the 3rd thermo electric material layer 203 is to be passivated phase-change material node layer again.
In summary, wherein, the material of first, second, and third electric insulating material layer 201,202 and 203 can be silicon
Oxynitrides, any one or a few the combination in nitride or oxide, be by sputtering method, vapour deposition method, chemistry
A kind of system in vapour deposition, laser-assisted deposition method, atomic layer deposition strategy, thermal oxidation method or metallo-organic decomposition process
It is standby.
Wherein, the material of horizontally-opposed electrode layer 301 and electrode tips 3012 can be tungsten, titanium nitride, nickel, aluminium, titanium,
One or more of combinations in gold, silver, copper, platinum simple substance and its oxide, it is by sputtering method, vapour deposition method, chemical gas
One or several kinds of preparations in phase sedimentation, atomic layer deposition method, metallo-organic decomposition process.
Wherein, the material of phase-change material layers 401 and phase-change material node 4011 can be GeSbTe series alloys, be to pass through
One or several kinds of preparations in sputtering method, CVD method, atomic layer deposition method.
Particular embodiments described above, the purpose of the present invention, technical scheme and beneficial effect are carried out further in detail
Describe in detail bright, it should be understood that the foregoing is only the present invention specific embodiment, be not intended to limit the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution and improvements done etc., the protection of the present invention should be included in
Within the scope of.
Claims (7)
1. a kind of preparation method of the full limitation phase transition storage of level based on from selective etching, this method include：
Step 1：On substrate (101), the first electric insulating material layer (201) is deposited；
Step 2：On the first electric insulating material layer (201), water is prepared using the method for " photoetching-thin-film deposition-stripping "
Flat opposed electrode layer (301) and horizontally-opposed electrode gap (3011)；
Step 3：On the first electric insulating material layer (201) and horizontally-opposed electrode layer (301) and horizontally-opposed electrode stitches
In gap (3011), phase-change material layers (401) are prepared using the method for " photoetching-thin-film deposition-stripping "；
Step 4：In the exposure of the first electric heating insulating barrier (201), horizontally-opposed electrode layer (301) and phase-change material layers (401)
Upper surface, the second electric insulating material layer (202) is prepared using the method for " photoetching-thin-film deposition-stripping ", is passivated phase transformation material
The bed of material (401) and the electrode tips (3012) for exposing horizontally-opposed electrode layer (301)；
Step 5：Anneal and electric pulse is applied to phase-change material layers (401) by electrode tips (3012), it is decrystallized to be located at water
Phase-change material layers (401) in flat opposite electrode gap (3011), and wet etching removes the second electric insulating material layer successively
(202), alkaline solution wet etching only retains the phase-change material node layer in horizontally-opposed electrode gap (3011)
(4011)；
Step 6：In the first electric insulating material layer (201), horizontally-opposed electrode layer (301) and phase-change material node layer (4011)
On exposed surface, the 3rd thermo electric material layer (203) is prepared using the method for " photoetching-thin-film deposition-stripping ", so as to deactivator
Part, complete device and prepare, wherein phase-change material layers (401) and the material of phase-change material node layer (4011) are that GeSbTe series is closed
Gold.
2. the preparation method of the level full limitation phase transition storage according to claim 1 based on from selective etching, substrate
(101) material is silicon, gallium nitride or sapphire.
3. the preparation method of the level full limitation phase transition storage according to claim 2 based on from selective etching, wherein
The material of first, second, and third electric insulating material layer (201), (202) and (203) is the oxynitrides of silicon, nitride
Or the combination of any one or a few in oxide.
4. the preparation method of the level full limitation phase transition storage according to claim 1 based on from selective etching, wherein
First, second, and third electric insulating material layer (201), (202) and (203) is formed sediment by sputtering method, vapour deposition method, chemical gaseous phase
It is prepared by one kind in area method, laser-assisted deposition method, atomic layer deposition strategy, thermal oxidation method or metallo-organic decomposition process.
5. the preparation method of the level full limitation phase transition storage according to claim 1 based on from selective etching, wherein
The material of horizontally-opposed electrode layer (301) and electrode tips (3012) is tungsten, titanium nitride, nickel, aluminium, titanium, gold, silver, copper or platinum
One or more of combinations in metal simple-substance and its oxide.
6. the preparation method of the level full limitation phase transition storage according to claim 5 based on from selective etching, wherein
The material of horizontally-opposed electrode layer (301) and electrode tips (3012) is by sputtering method, vapour deposition method, chemical vapor deposition
One or several kinds of preparations in method, atomic layer deposition method or metallo-organic decomposition process.
7. the preparation method of the level full limitation phase transition storage according to claim 1 based on from selective etching, wherein
Phase-change material layers (401) and phase-change material node layer (4011) are by sputtering method, CVD method or ald
One or several kinds of preparations in method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510881785.2A CN105489756B (en) | 2015-12-03 | 2015-12-03 | Preparation method based on the full limitation phase transition storage of level from selective etching |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510881785.2A CN105489756B (en) | 2015-12-03 | 2015-12-03 | Preparation method based on the full limitation phase transition storage of level from selective etching |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105489756A CN105489756A (en) | 2016-04-13 |
| CN105489756B true CN105489756B (en) | 2018-01-12 |
Family
ID=55676611
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510881785.2A Expired - Fee Related CN105489756B (en) | 2015-12-03 | 2015-12-03 | Preparation method based on the full limitation phase transition storage of level from selective etching |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105489756B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100405629C (en) * | 2002-12-13 | 2008-07-23 | 英特尔公司 | Horizontal phase change memory and producing method thereof |
| CN103105325A (en) * | 2013-01-31 | 2013-05-15 | 中国科学院半导体研究所 | Method for detecting phase change mechanism of horizontal full-restriction phase change quantum dot |
| CN105070827A (en) * | 2015-07-15 | 2015-11-18 | 中国科学院半导体研究所 | Self-aligning preparation method for horizontal total-restriction phase change memory based on corrosion |
-
2015
- 2015-12-03 CN CN201510881785.2A patent/CN105489756B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100405629C (en) * | 2002-12-13 | 2008-07-23 | 英特尔公司 | Horizontal phase change memory and producing method thereof |
| CN103105325A (en) * | 2013-01-31 | 2013-05-15 | 中国科学院半导体研究所 | Method for detecting phase change mechanism of horizontal full-restriction phase change quantum dot |
| CN105070827A (en) * | 2015-07-15 | 2015-11-18 | 中国科学院半导体研究所 | Self-aligning preparation method for horizontal total-restriction phase change memory based on corrosion |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105489756A (en) | 2016-04-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Munjal et al. | Advances in resistive switching based memory devices | |
| Goux et al. | Electrochemical processes and device improvement in conductive bridge RAM cells | |
| CN101582485B (en) | Doping modified phase change material and phase change storage unit containing same and preparation method thereof | |
| CN104966717B (en) | A kind of storage arrangement and the method that the storage arrangement is provided | |
| CN101924072B (en) | Phase change memory having stabilized microstructure and integrated circuit manufacturing method | |
| CN101556986B (en) | Multi-state resistive switching material, thin film prepared therewith, multi-sate resistive switching memory element and application of memory element in memory device | |
| CN101989644A (en) | Method for improving data retention capacity of resistor random memory | |
| TWI451532B (en) | Memory element and memory device | |
| CN102903845A (en) | Resistive random access memory and manufacture method thereof | |
| EP2930760B1 (en) | Method for forming memory device | |
| TW201231684A (en) | Quaternary gallium tellurium antimony (M-GaTeSb) based phase change memory devices | |
| CN102683348A (en) | Memory element and memory device | |
| CN102227015A (en) | Phase transition storage material and preparation method thereof | |
| TW200908225A (en) | Resistor random access memory structure having a defined small area of electrical contact | |
| CN103682095B (en) | A kind of resistance-variable storing device with selectivity characteristic and preparation method thereof | |
| CN101931049B (en) | Anti-fatigue phase change storage unit with low power consumption and preparation method thereof | |
| CN103427022A (en) | Phase change memory structure containing sandwich-type electrodes and producing method thereof | |
| CN102593350B (en) | Phase change memory cell and producing method thereof | |
| CN101916823B (en) | Phase change storage device based on antimony telluride composite phase change material and preparation method thereof | |
| CN101159314A (en) | Memory cell of resistor type stochastic memory and preparation method thereof | |
| CN105489756B (en) | Preparation method based on the full limitation phase transition storage of level from selective etching | |
| TW200933883A (en) | Phase-change material, memory unit, and method for storing/reading data electrically | |
| CN102130297B (en) | Resistive random access memory based on P/N type oxide laminated structure and preparation method thereof | |
| CN100397561C (en) | Process for preparing nano phase change storage device unit | |
| CN103105325B (en) | Method for detecting phase change mechanism of horizontal full-restriction phase change quantum dot |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180112 Termination date: 20181203 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |