CN105489477B - A kind of semiconductor devices and its manufacturing method - Google Patents
A kind of semiconductor devices and its manufacturing method Download PDFInfo
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- CN105489477B CN105489477B CN201410479915.5A CN201410479915A CN105489477B CN 105489477 B CN105489477 B CN 105489477B CN 201410479915 A CN201410479915 A CN 201410479915A CN 105489477 B CN105489477 B CN 105489477B
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Abstract
The invention discloses a kind of manufacturing methods of semiconductor devices, including step：Semiconductor substrate is provided, the substrate has first area and second area；The lamination of the first semiconductor layer and the second semiconductor layer is formed over the substrate；Device architecture is formed on the second semiconductor layer of first area and second area；The second semiconductor layer for etching the device architecture both sides of first area, to form etched hole；By the first semiconductor layer under at least grid of etched hole erosion removal first area, to form cavity, the first semiconductor layer near only remaining isolation structure；The filled media material in cavity and etched hole.The present invention may be implemented to realize SOI device by body substrate, meanwhile, the thickness of oxygen buried layer can be adjusted by the thickness of the first semiconductor layer of formation, meet the needs of different components, simple for process, and the technique is easy to androgynous substrate devices and integrates.
Description
Technical field
The invention belongs to field of semiconductor manufacture more particularly to a kind of semiconductor devices and its manufacturing methods.
Background technology
Constantly reduce with the characteristic size of device, after entering nanoscale especially 22nm or less sizes, closes on
The Limits properties of Semiconductor Physics device are comed one after another, such as capacity loss, leakage current increase, noise and increasing, latch-up and short
Channelling effect etc., in order to overcome the problems, such as these, SOI (silicon-on-insulator, Silicon-On-Insulator) technology is come into being.
SOI substrate divides thick-layer and thin layer SOI, and the thickness of the top layer silicon of thin layer SOI device, which is less than under grid, is maximally depleted layer
Width, when the thickness of top layer silicon is thinning, device exhausts (Fully from part depletion (Partially Depletion) to whole
Depletion) change, be ultra-thin SOI (Ultra thin SOI, UTSOI) when top layer silicon is less than 50nm, SOI device is whole
It exhausts, the device all exhausted has larger current driving capability, steep sub-threshold slope, smaller short channel, narrow raceway groove
Effect and the advantages that completely eliminating Kink effects, especially suitable for the application of high speed, low pressure, low consumption circuit, ultra-thin SOI becomes
The ideal solution of 22nm or less dimension process.
However, the cost of SOI substrate is higher at present, and the specification of the SOI substrate provided is more single, can not be according to device
Need adjust the thickness of each layer.
Invention content
It is an object of the invention to overcome deficiency in the prior art, a kind of semiconductor devices and its manufacturing method are provided,
SOI device is realized using body substrate and to bury oxygen thickness adjustable.
To achieve the above object, the technical scheme is that：
A kind of manufacturing method of semiconductor devices, including step：
Semiconductor substrate is provided, the substrate has first area and second area；
The lamination of the first semiconductor layer and the second semiconductor layer is formed over the substrate, and the lamination is formed in substrate
Isolation structure；
Device architecture is formed on the second semiconductor layer of first area and second area；
The second semiconductor layer for etching the device architecture both sides of first area, to form etched hole；
The first semiconductor layer under the grid of the device architecture of erosion removal first area is carried out by etched hole, to be formed
Cavity, only the first semiconductor layer near residue isolation structure；
The filled media material in cavity and etched hole.
Optionally, the step of lamination for forming the first semiconductor layer and the second semiconductor layer over the substrate is specially：
The first semiconductor layer of epitaxial growth and the second semiconductor layer successively on a semiconductor substrate.
Optionally, the substrate is silicon substrate, and first semiconductor layer is GexSi1-x, wherein 0<x<1, described second
Semiconductor layer is silicon.
Optionally, it is specially the step of filled media material in cavity and etched hole：
Using ALD or CVD techniques, first medium layer is filled up in the cavities and forms first Jie on the inner wall of etched hole
Matter layer；Second dielectric layer is filled up in etched hole.
Optionally, the first medium layer is high K medium material, and second dielectric layer is silica.
Optionally, further include step：
The first semiconductor layer near remaining isolation structure and thereon the second semiconductor layer are etched, to form groove, and
Fill oxide in the trench.
In addition, the present invention also provides the semiconductor devices that the above method is formed, including first area and second area,
In,
First area includes：
Semiconductor substrate；
First medium layer in semiconductor substrate and the second semiconductor layer thereon；
The first device architecture on second semiconductor layer, the first medium layer are located at least in the grid of the first device architecture
Lower section；
Through the etched hole of the second semiconductor layer, it is located at the both sides of the grid of the first device architecture, is filled in etched hole
Dielectric material；
And in side of the etched hole far from the first device architecture, it is formed through the second semiconductor layer and first medium layer
Isolated groove；
Second area includes：
Semiconductor substrate；
The lamination of the first semiconductor layer and the second semiconductor layer in semiconductor substrate；
The second device architecture on second semiconductor layer.
Optionally, the dielectric material in the etched hole includes first medium layer on etched hole inner wall and fills up etched hole
Second dielectric layer.
Optionally, the first medium layer is high K medium material, and second dielectric layer is silica.
The manufacturing method of the semiconductor devices of the present invention, forms the first semiconductor layer and the second semiconductor layer on substrate,
And it is formed on device, then, the first semiconductor layer is removed by etching etched hole in the second semiconductor layer, and again
Layer of dielectric material is formed, in this manner it is achieved that SOI device is realized by body substrate, meanwhile, the thickness of oxygen buried layer can
It is adjusted with thickness by the first semiconductor layer of formation, meets the needs of different components, it is simple for process, and the technique
It is integrated to be easy to androgynous substrate devices.
Description of the drawings
It, below will be to attached drawing needed in the embodiment in order to illustrate more clearly of the technical solution that the present invention is implemented
It is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, general for this field
For logical technical staff, without creative efforts, other drawings may also be obtained based on these drawings.
Fig. 1 shows the flow chart of the manufacturing method of the semiconductor devices of the present invention；
Fig. 2-Fig. 9 is that the cross section structure in each manufacturing process for manufacture semiconductor devices according to the embodiment of the present invention is illustrated
Figure.
Specific implementation mode
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, below in conjunction with the accompanying drawings to the present invention
Specific implementation mode be described in detail.
Many details are elaborated in the following description to facilitate a thorough understanding of the present invention, still the present invention can be with
Implemented different from other manner described here using other, those skilled in the art can be without prejudice to intension of the present invention
In the case of do similar popularization, therefore the present invention is not limited by following public specific embodiment.
Secondly, combination schematic diagram of the present invention is described in detail, when describing the embodiments of the present invention, for purposes of illustration only, table
Show that the sectional view of device architecture can disobey general proportion and make partial enlargement, and the schematic diagram is example, is not answered herein
Limit the scope of protection of the invention.In addition, three-dimensional space that should be comprising length, width and depth in actual fabrication.
Refering to what is shown in Fig. 1, the present invention provides a kind of manufacturing methods of semiconductor devices, including：Semiconductor substrate is provided,
The substrate has first area and second area；The first semiconductor layer stacked gradually and the second half are formed over the substrate
Conductor layer；Device architecture is formed on the second semiconductor layer of first area and second area；Etch the device junction of first area
Second semiconductor layer of structure both sides, to form etched hole；Pass through at least device architecture of etched hole erosion removal first area
The first semiconductor layer under grid, to form cavity；The filled media material in cavity and etched hole.
The manufacturing method of the device of the present invention, by forming the first and second semiconductor layers on a semiconductor substrate, at it
Upper formation device then removes the first semiconductor layer, and re-form Jie by etching etched hole in the second semiconductor layer
The material bed of material, in this manner it is achieved that SOI device is realized by body substrate, meanwhile, the thickness of oxygen buried layer can pass through
The thickness of the first semiconductor layer formed is adjusted, and meets the needs of different components, simple for process, and the technique is easy to same
Body substrate device is integrated.
Technical solution in order to better understand the present invention and technique effect, below with reference to the semiconductor devices of the present invention
Manufacturing method flow chart Fig. 1 and specific embodiment be described in detail.
First, in step S01, semiconductor substrate 100 is provided, the substrate has first area 1001 and second area
1002, with reference to shown in figure 2.
In embodiments of the present invention, the semiconductor substrate 100 can be Si substrates, Ge substrates, SiGe substrate etc..At it
Can also be the substrate for including other elements semiconductor or compound semiconductor, such as GaAs, InP or SiC in his embodiment
Deng, can also be laminated construction, such as Si/SiGe etc..In the present embodiment, the semiconductor substrate 100 is body silicon substrate.The
One region 1001 and second area 1002 are for being respectively formed different types of device, in the embodiment of the present invention, first area
1001 are used to form the device of SOI, and second area 1002 is used to form the device of body silicon.
Then, in step S02, the first semiconductor layer 102 and the second semiconductor layer 104 are formed on the substrate 100
Lamination is formed with the isolation structure 106 of the lamination in substrate, with reference to shown in figure 2.
In the present embodiment, epitaxial growth (EPI) technique may be used, epitaxial growth successively on body silicon substrate 100
Semi-conductor layer 102 and the second semiconductor layer 104, wherein first semiconductor layer can be GexSi1-x, wherein 0<x<1,
Thickness can be 1-200nm, typically can be with 5nm or 10nm；Second semiconductor layer can be silicon, and thickness can be 3-
200nm can be typically 5nm or 10nm.Epitaxy technique can form the higher semiconductor layer of quality, be formed by improve
The performance of device.After being epitaxially formed the first and second semiconductor layers, can carry out the first and second semiconductor layers 102,104 and
The etching of substrate 100, to form isolation structure 106, the second semiconductor layer 104 between isolation structure 106 is active area.
In the present invention, the thickness of the first semiconductor layer can be selected according to the needs of device, after thickness determines
The thickness of the dielectric material of continuous filling, that is, in SOI substrate oxygen buried layer effect；Second semiconductor layer is used for the shape of device
At thickness is configured according to the specific requirements of device, is equivalent to the effect of top layer silicon in SOI substrate, the second half is led at this
When the thickness of body layer is less than 50nm, it can be used for being formed UTSOI devices.
Then, in step S03, the shaper on the second semiconductor layer 104 of first area 1001 and second area 1002
Part structure 1101,1102, with reference to shown in figure 2.
Device architecture 1101,1102 can be formed according to traditional technique, front gate or rear grid technique may be used.At this
In embodiment, device architecture is formed using rear grid technique, first, forms gate dielectric layer and puppet on the second semiconductor layer 104
Grid (not shown) and its side wall 1141,1142, gate dielectric layer can be thermal oxide layer or other suitable dielectric materials, such as
Silica, silicon nitride etc. can be silica, can be formed by the method for thermal oxide in one embodiment.Pseudo- grid
It can be non-crystalline silicon, polysilicon or silica etc., can be non-crystalline silicon in one embodiment.Side wall 1141,1142 can have
There is single or multi-layer structure, can be situated between by silicon nitride, silica, silicon oxynitride, silicon carbide, fluoride-doped silica glass, low k electricity
Material and combinations thereof and/or other suitable materials are formed, and side wall 1141,1142 can be nitridation in one embodiment
The double-layer structure of silicon and silica.
Then, source-drain area is formed in pseudo- grid both sides, in one embodiment, by epi dopant in the second semiconductor layer
The source-drain area 116 of silicon is formed on 104.It is of course also possible to form source-drain area in the second semiconductor layer by ion implanting.
Then, it covers interlayer dielectric layer 120 in pseudo- grid both sides and by wet etching, removes pseudo- grid and gate dielectric layer, and
The lamination 1121,1122 of gate dielectric layer and grid is re-formed, which can be high K medium material (for example, and oxidation
Silicon is compared, the material with high-k) or other suitable dielectric materials, high K medium material such as hafnium base oxide should
Grid can be that metal gate electrode can be one or more layers structure, may include metal material or polysilicon or their group
It closes, metal material such as Ti, TiAlx、TiN、TaNx、HfN、TiCx、TaCxEtc..
To, device architecture is formd on the second semiconductor layer, the embodiment for being here formed as device architecture is merely illustrative,
Arbitrary required device architecture can be formed as needed.As needed, the device architecture on first area and second area can
To be formed using identical or different material.
Then, in step S04, the second semiconductor layer 104 of 1101 both sides of device architecture of first area 1001 is etched, with
Etched hole 124 is formed, with reference to shown in figure 3.
After forming device architecture, continue the dielectric layer 120 between device upper caldding layer, with reference to shown in figure 3.In the present invention
In, before the step of forming contact hole, form etched hole 124.In the present embodiment, specifically, interlayer dielectric layer 120 it
The first mask layer 122 of upper formation, which covers second area 1002, under the cover of the first mask layer 122,
Interlayer dielectric layer 120, source-drain area 116 and the second semiconductor layer 104 of first area 1001 are etched, is led until exposing the first half
Body layer 102, to form etched hole 124, as shown in Figure 3.
Then, in step S05, at least device architecture of erosion removal first area 1001 is carried out by etched hole 124
The first semiconductor layer 102 under grid, to form cavity 130, with reference to shown in figure 4.
In the present embodiment, etch period can be set according to etch rate so that after etching, only remaining isolation structure
The first semiconductor layer 102 near 106, as shown in figure 4, in this way, rectangular under the device architecture 1101 of first area 1001
At cavity 130.
Certainly, in other embodiments, it can also further perform etching, remove the first whole semiconductor layers,
Cavity is formed under entire second semiconductor layer in one region.
Then, in step S06, the filled media material 130,132 in cavity 130 and etched hole 124, with reference to shown in figure 5.
In the present embodiment, it is possible, firstly, to by ALD (atomic layer deposition) or CVD (chemical vapor deposition) technique, carries out
The filling of first medium material 131, the first medium material can be oxide material or high K medium material or other insulation
Dielectric material, when filling up cavity formation first medium layer 131, also deposition has the first medium layer on the inner wall of etched hole 124
131；Then, etched hole 124 is filled with second medium material, second medium material can be the dielectric materials such as silica, go forward side by side
Row planarization, until exposure interlayer dielectric layer 120, forms second dielectric layer 132 in etched hole, to be filled up with dielectric material
Cavity and etched hole, with reference to shown in figure 5.
In other embodiments, the filling of cavity can also be carried out using other methods, such as thermal oxide may be used
Method is aoxidized so that the oxide material of substrate and the second semiconductor layer fills up cavity, then, performs etching the filling in hole.
Then, more preferably, the first semiconductor layer 102 near isolation structure 106 can be removed, specifically, in interlayer
The second mask layer 135 is formed on dielectric layer, under the cover of the second mask layer 135 etch interlayer dielectric layer 120, source-drain area 116,
Second semiconductor layer 104 and the first semiconductor layer 102, to form groove 134 so that the first semiconductor layer near isolation structure
102 further get rid of, as shown in Figure 6；Then, which is filled up with the dielectric material 136 of oxide, such as silica
Deng as shown in Figure 7.In this way, the device architecture of similar SOI substrate is formd in first area 1001, in 1002 shape of second area
At the device architecture of similar body silicon substrate.
Then, other necessary techniques can be carried out.
Third mask layer 140 can be formed on interlayer dielectric layer 120, in third mask layer 140 according to common process
Under masking, the etching of interlayer dielectric layer is performed etching, contact hole 142 is formed, with reference to shown in figure 8；Then, metal material is carried out
Filling, and planarized, until exposure interlayer dielectric layer 120, (not shown to form source and drain contact 144 and gate contact
Go out), with reference to shown in figure 9.
So far the semiconductor devices of method constructed in accordance is formd.Refering to what is shown in Fig. 9, including first area 1001
With second area 1002, wherein
First area includes：
Semiconductor substrate 100；
First medium layer 131 in semiconductor substrate and the second semiconductor layer 104 thereon；
The first device architecture 1101 on second semiconductor layer 104, the first medium layer are located at least in the first device junction
1121 lower section of grid of structure；
Through the etched hole 124 of the second semiconductor layer, in the both sides of the grid 1121 of the first device architecture, etched hole
Filled with dielectric material 131,132；
Second area includes：
Semiconductor substrate 100；
The lamination of the first semiconductor layer 102 and the second semiconductor layer 104 in semiconductor substrate；
The second device architecture 1102 on second semiconductor layer 104.
The present invention semiconductor devices in, source and drain contact 144 be formed in on the source-drain area of etched hole side 116.
In an embodiment of the present invention, the dielectric material in the etched hole 124 includes first Jie on etched hole inner wall
Matter layer 131 and the second dielectric layer 132 for filling up etched hole, such as first medium layer can be able to be high K medium material, and second is situated between
Matter layer can be silica.
In an embodiment of the present invention, first medium layer 131 is formed in the lower section of the entire device architecture of first area,
That is under the second semiconductor layer all be first medium layer, as shown in figure 9, and be formed through in substrate 100 interlayer dielectric layer 120,
The isolated groove 136 of source-drain area 116, the second semiconductor layer 104 and first medium layer 131.
The above described is only a preferred embodiment of the present invention, being not intended to limit the present invention in any form.
Although the present invention has been disclosed in the preferred embodiments as above, however, it is not intended to limit the invention.It is any to be familiar with ability
The technical staff in domain, without departing from the scope of the technical proposal of the invention, all using in the methods and techniques of the disclosure above
Appearance makes many possible changes and modifications to technical solution of the present invention, or is revised as the equivalent embodiment of equivalent variations.Therefore,
Every content without departing from technical solution of the present invention is made to the above embodiment any simple according to the technical essence of the invention
Modification, equivalent variations and modification, in the range of still falling within technical solution of the present invention protection.
Claims (9)
1. a kind of manufacturing method of semiconductor devices, which is characterized in that including step：
Semiconductor substrate is provided, the substrate has first area and second area；
Form the lamination of the first semiconductor layer and the second semiconductor layer over the substrate, be formed in substrate the lamination every
From structure；
Device architecture is formed on the second semiconductor layer of first area and second area；
The second semiconductor layer for etching the device architecture both sides of first area, to form etched hole；
The first semiconductor layer under the grid of the device architecture of erosion removal first area is carried out by etched hole, to form sky
Chamber, only the first semiconductor layer near residue isolation structure；
The filled media material in cavity and etched hole.
2. manufacturing method according to claim 1, which is characterized in that form the first semiconductor layer successively over the substrate
It is specially with the step of lamination of the second semiconductor layer：
The first semiconductor layer of epitaxial growth and the second semiconductor layer successively on a semiconductor substrate.
3. manufacturing method according to claim 2, which is characterized in that the substrate is silicon substrate, first semiconductor
Layer is GexSi1-x, wherein 0<x<1, second semiconductor layer is silicon.
4. manufacturing method according to claim 1, which is characterized in that the step of filled media material in cavity and etched hole
It is rapid to be specially：
Using ALD or CVD techniques, first medium layer is filled up in the cavities and forms first medium on the inner wall of etched hole
Layer；Second dielectric layer is filled up in etched hole.
5. manufacturing method according to claim 4, which is characterized in that the first medium layer be high K medium material, second
Dielectric layer is silica.
6. manufacturing method according to claim 1, which is characterized in that further include step：
The first semiconductor layer near remaining isolation structure and thereon the second semiconductor layer are etched, to form groove, and in ditch
Fill oxide in slot.
7. a kind of semiconductor devices, which is characterized in that including first area and second area, wherein first area includes：
Semiconductor substrate；
First medium layer in semiconductor substrate and the second semiconductor layer thereon；
The first device architecture on second semiconductor layer, the first medium layer are located at least under the grid of the first device architecture
Side；
Through the etched hole of the second semiconductor layer, it is located at the both sides of the grid of the first device architecture, medium is filled in etched hole
Material；
And in side of the etched hole far from the first device architecture, it is formed through the isolation of the second semiconductor layer and first medium layer
Groove；
Second area includes：
Semiconductor substrate；
The lamination of the first semiconductor layer and the second semiconductor layer in semiconductor substrate；
The second device architecture on second semiconductor layer.
8. semiconductor devices according to claim 7, which is characterized in that the dielectric material in the etched hole includes etching
First medium layer on the inner wall of hole and the second dielectric layer for filling up etched hole.
9. semiconductor devices according to claim 8, which is characterized in that the first medium layer is high K medium material, the
Second medium layer is silica.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102332451A (en) * | 2010-07-13 | 2012-01-25 | 中国科学院微电子研究所 | Nano-wire stacked structure, formation method thereof and semiconductor layer patterning method |
| CN102867852A (en) * | 2011-07-04 | 2013-01-09 | 中国科学院微电子研究所 | Transistor and method for forming same |
| CN103730363A (en) * | 2012-10-11 | 2014-04-16 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN103794542A (en) * | 2012-10-30 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor substrate |
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2014
- 2014-09-18 CN CN201410479915.5A patent/CN105489477B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102332451A (en) * | 2010-07-13 | 2012-01-25 | 中国科学院微电子研究所 | Nano-wire stacked structure, formation method thereof and semiconductor layer patterning method |
| CN102867852A (en) * | 2011-07-04 | 2013-01-09 | 中国科学院微电子研究所 | Transistor and method for forming same |
| CN103730363A (en) * | 2012-10-11 | 2014-04-16 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN103794542A (en) * | 2012-10-30 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor substrate |
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