CN105489154B - Display device and driving method thereof - Google Patents
Display device and driving method thereof Download PDFInfo
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- CN105489154B CN105489154B CN201511026913.1A CN201511026913A CN105489154B CN 105489154 B CN105489154 B CN 105489154B CN 201511026913 A CN201511026913 A CN 201511026913A CN 105489154 B CN105489154 B CN 105489154B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
A display device is described, which includes a plurality of pixel circuits; a plurality of data lines; the driving chip provides a first data signal and a second data signal; the first data signal is a time-varying signal, the second data signal is a constant voltage signal, and the potential of the second data signal is lower than the lowest potential of the first data signal; the first multi-path selection unit is used for converting the first data signals into a plurality of first-order data signals and transmitting the first-order data signals to a plurality of data lines; the second multi-path selection unit is used for converting the second data signals into a plurality of second secondary data signals and transmitting the second secondary data signals to the data lines; in a data writing stage of the pixel circuit, the data line receives a first secondary data signal from the first multi-path selection unit; the data line receives a second sub-level data signal from the second multiplexing unit in an off-phase of the pixel circuit. According to the display device provided by the embodiment of the invention, the actual data writing time of each pixel circuit is equal, the picture display is uniform, and the display unevenness is avoided.
Description
Technical field
The present invention relates to display technology fields, more particularly to the driving method of a kind of display device and the display device.
Background technology
With the development of display technology, the resolution ratio of display device is higher and higher, and data line is more and more, causes display surface
Circuit is excessive at pallet rank, influences narrow frame at step and talks about.Therefore, in the prior art, it is proposed that a kind of to use multi-path choice list
First (Demultiplexer, DEMUX), uses a data channel, time-division multiplex input data signal.
It please refers to Fig.1 and Fig. 2, Fig. 1 is a kind of multi-path choice unit in the prior art, Fig. 2 is multi-path choice list in Fig. 1
The sequence diagram of member.To select way to illustrate problems of the prior art for 6 multiple selector.Referring to FIG. 1, this is existing
There is the multi-path choice unit in technology to include：One input terminal, the input terminal are used for input data line signal DATA；Six PMOS
Transistor；Six output ends, respectively to different data line output drive signals.The grid of six PMOS transistors is connected to six
A different timing control end is respectively intended to input the signal always of different six, is opened successively with controlling six PMOS transistors
It opens.The source electrode of six PMOS transistors is all connected to input terminal, and drain electrode is connected to different data lines, will when transistor is opened
Data line signal DATA is output to corresponding data line.As shown in Figure 1, the grid of six transistors be connected respectively to CKH1,
The drain electrode of CKH2, CKH3, CKH4, CKH5 and CKH6, six transistors are connected respectively to R1, G1, B1, R2, B2 and G2 six
Data line.
Referring to FIG. 2, at the t1 moment, CKH1 becomes low level pulse signal, and the transistor for being connected to CKH1 is opened, other
Transistor is closed, and DEMUX circuits are to R1 output data line signals DATA；At the t2 moment, CKH2 becomes low level pulse signal, even
The transistor for being connected to CKH2 is opened, other transistors are closed, and DEMUX circuits are to G1 output data line signals DATA；At the t3 moment,
CKH3 becomes low level pulse signal, and the transistor for being connected to CKH3 is opened, other transistors are closed, and DEMUX circuits are defeated to B1
Go out data line signal DATA；At the t4 moment, CKH4 becomes low level pulse signal, and the transistor for being connected to CKH4 is opened, other
Transistor is closed, and DEMUX circuits are to R2 output data line signals DATA；At the t5 moment, CKH5 becomes low level pulse signal, even
The transistor for being connected to CKH5 is opened, other transistors are closed, and DEMUX circuits are to G2 output data line signals DATA；At the t6 moment,
CKH6 becomes low level pulse signal, and the transistor for being connected to CKH6 is opened, other transistors are closed, and DEMUX circuits are defeated to B2
Go out data line signal DATA.As it can be seen that by DEMUX circuits, six circuit-switched data lines can will be input to by data line signal DATA all the way
In, by Time-sharing control, realize the driving of different data line respective pixel.
However conventionally, as different transistor opening sequence different therefore different data line input
Signal time is also different,, still can be to pixel due to the effect of parasitic capacitance on data line after data line stops input signal
It charges, the two day data line charging time difference for causing different moments to be opened.And between the time that two transistors are opened
Every bigger, corresponding data line charging time difference is also bigger, and display effect will produce difference when showing identical image, cause to show
Show bad.Also, increase with the selection way of DEMUX, display is bad more apparent.
Invention content
In view of this, the embodiment of the present invention provides a kind of display device, including：
Multiple pixel circuits；
It is coupled to the multiple data lines of the multiple pixel circuit；
Driving chip, for providing the first data-signal and the second data-signal；First data-signal is time-varying
Signal, potential minimum are the first current potential；Second data-signal is constant voltage signal, and current potential is the second current potential；Described
Two current potentials are less than first current potential；
First multi-path choice unit, including a first input end and multiple first output ends, the first input end with
The driving chip connection, each first output end is connect with a data line, by first data-signal
Multiple first secondary data signal transmissions are converted to the multiple data lines, the first secondary data signal is believed for time-varying
Number, potential minimum is the first current potential；
Second multi-path choice unit, including second input terminal and multiple second output terminals, second input terminal with
The driving chip connection, each second output terminal is connect with a data line, by second data-signal
Multiple second subprime data signal transmissions are converted to the multiple data lines, the second subprime data-signal is believed for constant pressure
Number, current potential is the second current potential；
Wherein, in the data write phase of the pixel circuit, the data line reception with pixel circuit coupling comes from
First secondary data signal of the first multi-path choice unit；In the turn off phase of the pixel circuit, with pixel electricity
The data line of road coupling receives the second subprime data-signal from the second multi-path choice unit, wherein the pixel electricity
The turn off phase on road is in after the data write phase of the pixel circuit.
The embodiment of the present invention also provides a kind of driving method of above-mentioned display device, including：
Pixel circuit data write phase, in the pixel circuit data write phase, with pixel circuit coupling
Data line receives the first secondary data signal from the first multi-path choice unit；When the first secondary data signal is
Varying signal, potential minimum are the first current potential；
Pixel circuit turn off phase connects in the pixel circuit turn off phase with the data line of pixel circuit coupling
Receive the second subprime data-signal from the second multi-path choice unit；The second subprime data-signal is constant voltage signal,
Its current potential is the second current potential, wherein second current potential is less than first current potential；
Wherein, the turn off phase of the pixel circuit is in after the data write phase of the pixel circuit.
Compared with prior art, the present invention at least has the advantages that one of prominent as follows：It is provided in an embodiment of the present invention aobvious
Showing device and driving method have the first multi-path choice unit and the second multi-path choice unit, and data line is in data write phase
Receive respectively with turn off phase from the data-signal for not allowing multi-path choice unit to export so that the actual number of each pixel circuit
It it is only the time that the first multi-path choice unit respective transistor is opened according to write time and compensation time, therefore, uniform
Under picture, each pixel circuit is written into identical data, and picture is shown uniformly, and it is uneven (Mura) will not to form display.
Description of the drawings
Fig. 1 is a kind of multi-path choice unit in the prior art；
Fig. 2 is the sequence diagram of multi-path choice unit in Fig. 1；
Fig. 3 is a kind of display device overlooking structure diagram provided in an embodiment of the present invention；
Fig. 4 is a kind of structural schematic diagram of pixel circuit in Fig. 3；
Fig. 5 is the structural schematic diagram of multi-path choice unit in Fig. 3；
Fig. 6 is that multi-path choice unit runs sequence diagram in Fig. 3；
Fig. 7 be Fig. 4 in pixel circuit data write phase rough schematic view.
Specific implementation mode
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with attached drawing and implementation
The present invention will be further described for example.
It should be noted that elaborating detail in the following description in order to fully understand the present invention.But this hair
Bright to be implemented different from other manner described here with a variety of, those skilled in the art can be without prejudice in the present invention
Similar popularization is done in the case of culvert.Therefore the present invention is not limited by following public specific implementation mode.
Referring to FIG. 3, Fig. 3 is a kind of display device overlooking structure diagram provided in an embodiment of the present invention.The present embodiment
In the display device of offer, including substrate 10, on a side surface of substrate 10, it is provided with extend in a first direction a plurality of and sweeps
Retouch line 11 and the multiple data lines extended in a second direction 12, wherein first direction is the horizontal direction of diagram, and second direction is
The vertical direction of diagram, that is, first direction and second direction are substantially perpendicular.Two adjacent scan lines 11 and adjacent two
The intersection of data line 12 surrounds a pixel unit, all scan lines and all data lines intersect surround it is arranged in arrays more
A pixel unit, and pixel circuit 13 is provided in each pixel unit, and multiple data lines 12 be coupled to it is each
Pixel circuit 13, to provide data-signal for each pixel circuit.In being illustrated in the present embodiment, it is schematically shown that 6*7
Pixel unit and six data line D1, D2, D3, D4, D5 and D6, pixel circuit shown in Fig. 3 are also only schematically to say
It is bright, it, should not be using structure shown in the present embodiment as limitation of the invention in actual implementation.
Specifically, referring to FIG. 4, Fig. 4 is a kind of structural schematic diagram of pixel circuit in Fig. 3.Picture provided in this embodiment
Plain circuit is OLED pixel circuit, including a Light-emitting diode LED, multiple third transistor and at least one electricity
Hold C1, and multiple third transistor is PMOS transistor.Further, the pixel electricity of display device provided in this embodiment
Road includes a Light-emitting diode LED, a capacitance C1 and six third transistor T31, T32, T33, T34, T35 and T36.With
It is connected to for the pixel circuit of nth bar scan line and m data lines and illustrates, wherein n is the positive integer more than 1.The
The grid of one third transistor T31 connects (n-1)th scan line, receives the scanning signal Scan (n- of (n-1)th scan line
1), the first pole connects reference voltage line, receives reference voltage Vref, and the second pole connects first node N；Second third transistor
The grid of T32 connects nth bar scan line, receives the scanning signal Scan (n) of nth bar scan line, and the first pole connects first node
N, the second pole connect the second pole of third third transistor T33；The grid of third third transistor T33 connects first node
N, the first pole connect the second pole of the 4th third transistor T34；The first pole of 4th third transistor T34 connects nth bar
Luminous signal data line, receives luminous signal Emit (n), and the first pole connects first voltage line, receives first voltage PVDD；5th
The grid of a third transistor T34 connects the grid of the 4th third transistor T34, and the first pole connects second voltage line, receives
Second voltage PVEE, the second pole are connected to the second pole of second third transistor T32；The grid of 6th third transistor T36
Pole connects the grid of second third transistor T32, and the first pole connects data line Dm, to receive data-signal, the connection of the second pole
To the first pole of third third transistor T33.Wherein, first voltage PVDD, second voltage PVEE and reference voltage Vref
All it is constant voltage, and first voltage PVDD is higher than second voltage PVEE, and reference voltage Vref is that can make PMOS
The low level signal that transistor npn npn is opened.
With continued reference to FIG. 3, in the one side edge of substrate 10, it is provided with driving chip 15, due to providing the first data
Signal and the second data-signal, driving chip 15 and the first multi-path choice cells D EMUX1 and the second multi-path choice cells D EMUX2
Connection.Driving chip 15 provides the first data-signal for the first multi-path choice cells D EMUX1, is the second multi-path choice unit
DEMUX provides the second data-signal, wherein the first data-signal is time varying signal, potential value is kept not within certain moment
Become, and different with the difference at moment, potential minimum is the first current potential, and the second data-signal is constant voltage signal, electricity
Position is the second current potential, and the second current potential is less than the first current potential.
First multi-path choice cells D EMUX1, including a first input end and multiple first output ends, first input end
It being connect with the driving chip 15, each first output end is connect with a data line 12, the first data-signal is converted to
Multiple first secondary data signal transmissions are to multiple data lines 12, wherein the first secondary data signal is also time varying signal, most
Low potential is the first current potential.Second multi-path choice cells D EMUX2, including second input terminal and multiple second output terminals, the
Two input terminals are connect with driving chip 15, and each second output terminal is connect with a data line 12, and the second data-signal is turned
Multiple second subprime data signal transmissions are changed to data line 12, the second subprime data-signal is constant voltage signal, current potential
For the second current potential.
Specifically, please referring to Fig. 5 and Fig. 6, Fig. 5 is the structural schematic diagram of multi-path choice unit in Fig. 3, and Fig. 6 is more in Fig. 3
Road selecting unit runs sequence diagram.Wherein, the first multi-path choice cells D EMUX1 includes first input end P1, for inputting first
Data-signal DATA, and include multiple first switch transistors.First multi-path choice cells D EMUX1's provided in this embodiment
It is 1 to select ratio:6, you can input signal 6 road secondary signal outputs will be generated all the way.First multi-path choice cells D EMUX1 packets
Six the first transistors T11, T12, T13, T14, T15 and T16 are included, the grid of six the first transistors is respectively connected to six
First clock cable CKH1, CKH2, CKH3, CKH4, CKH5 and CKH6, the source electrode of six the first transistors are connected to first
Input terminal P1, and the drain electrode of six the first transistors is respectively connected to six data line D1, D2, D3, D4, D5 and D6.This reality
It applies in example, which is also pmos type transistor, and the characteristic of pmos type transistor is when grid voltage is less than threshold value electricity
When pressure, transistor is opened, the source electrode and drain electrode conducting of transistor, therefore, as six first of the grid of six transistors
When clock signal changes successively, which opens or closes successively, can be with when corresponding the first transistor is opened
First data-signal DATA is transferred to corresponding data line.Wherein the first data-signal DATA is time varying signal, and first
Clock signal is pulse signal, and the pulse frequency phase of the time varying frequency of the first data-signal DATA and the first clock signal
Deng.When corresponding transistor is opened, the moment, corresponding first data-signal DATA was transferred to corresponding data line, transmission
Signal is equal in the current potential at corresponding moment with the first data-signal DATA.That is, the potential minimum of the first data-signal DATA is the
The potential minimum of one current potential, multiple first secondary data signals is also the first current potential.
Correspondingly, the second multi-path choice cells D EMUX2 includes the second input terminal P2, for inputting the second data-signal
VINIT, and include multiple second switch transistors.The selection ratio of second multi-path choice cells D EMUX2 is similarly 1:6.More than second
Road selecting unit DEMUX2 includes six second transistors T11, T12, T13, T14, T15 and T16, six second transistors
Grid is respectively connected to six second clock signal wire CKBH1, CKBH2, CKBH3, CKBH4, CKBH5 and CKBH6, six second
The source electrode of transistor is connected to the second input terminal P2, and the drain electrode of six second transistors is respectively connected to six data lines
D1, D2, D3, D4, D5 and D6.In the present embodiment, which is also pmos type transistor, when six transistors
Six second clock signals of grid when changing successively, which opens or closes successively, corresponding
When two-transistor is opened, the second data-signal VINIT can be transferred to corresponding data line.Wherein second clock signal is also
Pulse signal, and the pulse frequency of the pulse frequency of second clock signal and the first clock signal is equal.When corresponding crystal
When pipe is opened, the moment, corresponding first data-signal DATA was transferred to corresponding data line, the signal of transmission and the second data
Signal VINIT is equal in the current potential at corresponding moment.Believe equal to the constant pressure of the second current potential that is, the second data-signal VINIT is current potential
Number, multiple second subprime data-signals are also the constant voltage signal that current potential is equal to the second current potential.
Also, the first clock cable that the first transistor of same signal line connection is connected with second transistor and the
Clock signal phase on two clock cables is opposite.For example, the first transistor T11 and second transistor of connection signal line D1
First clock signal CKH1 of T21 and the first transistor T11 connections and the second clock letter being connect with second transistor T21
The opposite in phase of number CKBH1.That is, when the first clock signal CKH1 is that high level signal is (electric higher than the threshold value of pmos type transistor
Pressure) when, second clock signal CKBH1 is low level signal (threshold voltage for being less than pmos type transistor), and when the first clock
When signal CKH1 is low level, second clock signal CKBH1 is high level, that is, the first transistor T11 and second transistor T21
On off state is opposite.The first transistor and the second transistor on off state for being attached to same data line are opposite.
In the data write phase of pixel circuit, is received with the data line of pixel circuit coupling and come from the first multi-path choice
The first secondary data signal of cells D EMUX1；In the turn off phase of pixel circuit, connect with the data line of pixel circuit coupling
Receive the second subprime data-signal from the second multi-path choice cells D EMUX2.Incorporated by reference to reference to fig. 4 to fig. 6, still with Fig. 4 institutes
The pixel circuit shown, and be connected to and illustrated for the pixel circuit of data line D1.T1 in the first stage, luminous signal
Emit (n) is high level signal, and the scanning signal Scan (n-1) of (n-1)th scan line is low level signal, nth bar scan line
Scanning signal Scan (n) be high level signal.At this point, first third transistor T31 is opened, reference voltage Vref is by the
One third transistor T31 enters first node N.At this point, no electric current flows through Light-emitting diode LED, pixel does not shine.Second
Stage t2 is divided into six secondary stages, the first secondary stage according to the data line for being connected to the same multi-path choice unit
T21, second subprime stage t22, third secondary stage t23, the 4th secondary stage t24, the 5th secondary stage t25 and the 6th grade
Stage t26.In six secondary stages, six the first clock signals sequentially input low level pulse, due to pmos type crystal
The switching characteristic of pipe, six the first transistors are opened successively, that is, multiple first clock signals control multiple the first transistors successively
It opens.Similarly, in six secondary stages, six second clock signals sequentially input high level pulse, six second transistors according to
Secondary closing, and the first transistor is opposite with the on off state of second transistor.
For being connected to the pixel unit of data line D1, in pixel circuit, the first secondary stage t21 is that rank is written in data
Section, at this point, first the first transistor T11 is opened, therefore the first data-signal DATA by first the first transistor T11 at
Enter data line D1 for the first secondary data signal, and first second transistor T21 is closed at this time, no normal direction data line D1 is carried
For second subprime signal, at this point, what is transmitted on the data line is low level signal.In the first secondary stage t21, first third
Transistor T31 is closed, and first node N keeps Vref current potentials, i.e. low potential.The scanning signal Scan (n) of nth bar scan line is low
Level signal, second third transistor T32 and the 6th third transistor T36 are opened, and third third transistor T33 is beaten
It opens.First secondary signal passes through the 6th third transistor T36, third third transistor T33 and second third transistor
T32 enters first node N, and the first secondary data signal charges to first node N, third third transistor T33's
Grid potential is raised, and the electric current by third third transistor T33 is made to be gradually reduced.That is, pixel circuit starts compensating for, i.e., pair
For a pixel circuit, data write phase and pixel circuit compensated stage are same stage, data write-in and pixel electricity
Road compensation is carried out at the same time.Referring to FIG. 7, Fig. 7 be Fig. 4 in pixel circuit signal write phase rough schematic view.According to
One secondary data signal it is of different sizes, the current potential of first node N is different, and the current potential of first node N is equal to corresponding the
The current potential of one secondary data signal, the potential minimum after charging are equal to the potential minimum of the first data-signal, that is, are equal to first
Current potential.
Before terminating to second stage t2 after the first secondary stage t21, for being connected to the first data line D1
Pixel circuit for, the as turn off phase of the pixel circuit, that is, for a pixel circuit, pixel circuit is cut
Only the stage is in after the data write phase of the pixel circuit and after the data write phase of pixel circuit.
In the present embodiment, phase III t3 is glow phase, and therefore, the turn off phase of pixel circuit is in data write phase and luminous rank
Between section.In the turn off phase, first first be connected in the first multi-path choice cells D EMUX1 of data line D1 is brilliant
Body pipe T11 is closed, and the first secondary data signal is no longer transferred to data line D1.And it is connected to the second multichannel choosing of data line D1
The first the first transistor T21 selected in cells D EMUX2 is opened, second subprime data signal transmission to D1.Due to the second data
Signal VINIT is constant voltage signal, and current potential is equal to the second current potential.Therefore, in the turn off phase of pixel circuit, due to other signals
It does not change, simplifies circuit still referring to Fig. 7, second of series is accessed in the first pole of third third transistor T33
It is believed that number, current potential is the second current potential, and the grid of third transistor T33 connects first node N, and value is that rank is written in data
First secondary data signal of section input, since the potential minimum of the first secondary data signal is the first current potential, the second current potential is low
In the first current potential, therefore, in turn off phase, since the first electrode potential of third third transistor T33 is lower than grid potential, root
According to the characteristic of pmos type transistor, it can not be filled with the lower current potential of grid potential than third transistor T33, therefore, cut
Only stage, data line D1 no longer charge to first node N, and actual Data writing time is only the first secondary stage t21.
For being connected to other pixel circuits of identical multi-path choice unit, for example, the pixel circuit for being connected to data line D2, number
It is second subprime stage t22 according to the write time, turn off phase is the time before data write phase t22 to glow phase t3,
Data line D2 no longer charges to first node N, and it is second subprime stage t22 to actually enter the write time.
Therefore, for being connected to the same first multi-path choice cells D EMUX1 and the same second multi-path choice unit
Multiple pixel circuits of DEMUX2, real data write phase are all equal, that is, are equal to the time of secondary stage, that is, are equal to
The pulse frequency of clock signal.
It is glow phase, i.e. phase III t3, at this point, first third transistor T31, the after second stage t2
Two third transistor T32 and the 6th third transistor T36 are closed, and luminous signal Emit (n) is low level signal, the 4th
Third transistor T34 and the 5th third transistor T35 is opened, since first voltage PVDD is more than second voltage PVEE,
Third third transistor T33 is also opened, and electric current flows to second voltage line from first voltage line, and diode (LED) shines.
In compared with the prior art, after being connected to the data line closing of pixel circuit, the storage capacitance on data line is to picture
The driving tube of plain circuit charges, and the practical charging time that different moments carry out the pixel circuit of data write-in is unequal.This
There is the display device that embodiment provides the first multi-path choice unit and the second multi-path choice unit, data line to be written in data
Stage and turn off phase receive respectively from the data-signal for not allowing multi-path choice unit to export so that the reality of each pixel circuit
Border Data writing time and compensation time are only the time that the first multi-path choice unit respective transistor is opened, each pixel electricity
The real data write time on road is equal, so that again under monochromatic uniform picture, the signal locked by pixel circuit is consistent, draws
Face is shown uniformly, and it is uneven will not to form display.
More specifically, in display device provided in this embodiment, for any one pixel circuit, in addition to data are written
Except stage, other stages, data line receives the second subprime data-signal from the second multi-path choice unit.Still with connection
To for the pixel circuit of data line D1, the turn off phase in t1 in the first stage, second stage t2, in phase III t3, number
The second subprime data-signal from the second multi-path choice cells D EMUX2 is all received according to line D1.It can thus be avoided at these
Interference of the parasitic capacitance to pixel circuit in phase data line keeps the stabilization of pixel circuit driving tube grid voltage, ensures
The circuit size of diode is flowed through, ensures luminous intensity.
Further, in the present embodiment, the voltage difference of the first current potential and the second current potential is more than or equal to 3 volts, but makes
Second current potential is more preferable to the write-in cut-off effect of pixel circuit data.
It should be noted that schematically illustrating above content is only the present embodiment, in the other embodiment of the present invention
In, there can also be other structures design.
For example, in the present embodiment, the quantity of the first transistor of the first multi-path choice unit is 6, in its of the present invention
In his embodiment, the other values more than 3 are can also be, when the data of the first transistor are more than 3, i.e. the choosing of multi-path choice unit
It selects than being less than 1:When 3, for being connected to the pixel circuit of the same first multi-path choice unit, deadline gap bigger is adopted
With the real data write time gap bigger of existing design, therefore design using the present invention, when can be to avoid being actually written into
Between gap increase.
Also, in the present embodiment, the quantity of the first transistor of the first multi-path choice unit is equal to the second multi-path choice
The quantity of the second transistor of unit, i.e. the selection of the first multi-path choice unit is than the selection equal to the second multi-path choice unit
Than, but in other embodiments of the invention, the selection ratio of first multi-path choice unit rain the second multi-path choice unit also may be used
To be different.
Also, in the present embodiment, illustrated by taking the pixel circuit of 6T1C patterns as an example, in other realities of the present invention
It applies in example, other pixel circuits comprising light emitting diode, multiple third transistor, at least one capacitance can also be made.And
In other embodiments of the invention, pixel circuit can also make liquid crystal display pixel circuit, that is, include a first transistor,
And the 4th transistor is PMOS transistor.It should not be using the structure of the present embodiment as limitation of the invention.
The embodiment of the present invention additionally provides a kind of driving method of above-mentioned display device, including：
Pixel circuit data write phase, in the pixel circuit data write phase, the data with pixel circuit coupling
Line receives the first secondary data signal from the first multi-path choice unit；Wherein the first secondary data signal is time varying signal,
Its potential minimum is the first current potential；
Pixel circuit turn off phase receives in the pixel circuit turn off phase with the data line of pixel circuit coupling
From the second subprime data-signal of the second multi-path choice unit；The second subprime data-signal is constant voltage signal, current potential the
Two current potentials, wherein the second current potential is less than the first current potential；
Wherein, the turn off phase of the pixel circuit is in after the data write phase of the pixel circuit.
Specifically, still referring to Fig. 5 to Fig. 7, illustrate by taking pixel circuit shown in Fig. 4 as an example, details are not described herein.
The above content is combining, specific embodiment is made for the present invention to be further described, and it cannot be said that the present invention's is specific
Implementation is confined to these explanations.For those of ordinary skill in the art to which the present invention belongs, the present invention is not being departed from
Under the premise of design, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to protection scope of the present invention.
Claims (11)
1. a kind of display device, including：
Multiple pixel circuits；
It is coupled to the multiple data lines of the multiple pixel circuit；
Driving chip, for providing the first data-signal and the second data-signal；First data-signal is time varying signal,
Its potential minimum is the first current potential；Second data-signal is constant voltage signal, and current potential is the second current potential；Second current potential
Less than first current potential；
First multi-path choice unit, including a first input end and multiple first output ends, the first input end with it is described
Driving chip connects, and each first output end is connect with a data line, and first data-signal is converted
It is time varying signal to give the multiple data lines, the first secondary data signal for multiple first secondary data signal transmissions,
Potential minimum is the first current potential；
Second multi-path choice unit, including second input terminal and multiple second output terminals, second input terminal with it is described
Driving chip connects, and each second output terminal is connect with a data line, second data-signal is converted
It is constant voltage signal to give the multiple data lines, the second subprime data-signal for multiple second subprime data signal transmissions,
Current potential is the second current potential；
Wherein, it in the data write phase of the pixel circuit, is received from described with the data line of pixel circuit coupling
First secondary data signal of the first multi-path choice unit；In the turn off phase of the pixel circuit, with the pixel circuit coupling
The data line connect receives the second subprime data-signal from the second multi-path choice unit, wherein the pixel circuit
Turn off phase is in after the data write phase of the pixel circuit.
2. display device as described in claim 1, which is characterized in that including：
The first multi-path choice unit includes：
The first input end, for inputting first data-signal；Multiple the first transistors；The multiple the first transistor
Grid be respectively connected to multiple first clock cables, it is defeated that the source electrode of the multiple the first transistor is connected to described first
Enter end, the drain electrode of the multiple the first transistor is respectively connected to the multiple first output end；
The second multi-path choice unit includes：
Second input terminal, for inputting second data-signal；Multiple second transistors；The multiple second transistor
Grid be respectively connected to multiple second clock signal wires, it is defeated that the source electrode of the multiple second transistor is connected to described second
Enter end, the drain electrode of the multiple second transistor is respectively connected to the multiple second output terminal；
The first clock cable for being connected with second transistor of the first transistor that signal wire described in same connects and when second
Clock signal phase on clock signal wire is opposite.
3. display device as claimed in claim 2, the multiple first clock signal control the multiple the first transistor according to
Secondary opening, the multiple second clock signal control the multiple second transistor and close successively.
4. display device as claimed in claim 2, which is characterized in that the first transistor number of the first multi-path choice unit
Amount is more than 3.
5. display device as claimed in claim 4, which is characterized in that the first transistor number of the first multi-path choice unit
Second transistor quantity of the amount equal to the second multi-path choice unit.
6. display device as claimed in claim 2, which is characterized in that the first transistor and the second transistor are
PMOS transistor.
7. display device as described in claim 1, which is characterized in that the pixel circuit includes：Light emitting diode, Duo Ge
Three transistors, at least one capacitance；The multiple third transistor is PMOS transistor.
8. display device as described in claim 1, which is characterized in that the pixel circuit includes：One the 4th transistor, institute
It is PMOS transistor to state the 4th transistor.
9. display device as described in claim 1, which is characterized in that the turn off phase is in data write phase and shines
Between stage.
10. display device as described in claim 1, which is characterized in that the voltage of first current potential and second current potential
Difference is more than or equal to 3 volts.
11. a kind of driving method of display device as described in claim 1, which is characterized in that including：
Pixel circuit data write phase, in the pixel circuit data write phase, the data with pixel circuit coupling
Line receives the first secondary data signal from the first multi-path choice unit；The first secondary data signal is believed for time-varying
Number, potential minimum is the first current potential；
Pixel circuit turn off phase receives in the pixel circuit turn off phase with the data line of pixel circuit coupling
From the second subprime data-signal of the second multi-path choice unit；The second subprime data-signal is constant voltage signal, electricity
Position is the second current potential, wherein second current potential is less than first current potential；
Wherein, the turn off phase of the pixel circuit is in after the data write phase of the pixel circuit.
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| CN108335670A (en) * | 2018-02-06 | 2018-07-27 | 信利（惠州）智能显示有限公司 | Circuit drive method and display panel |
| CN109102771B (en) * | 2018-08-27 | 2022-02-01 | 武汉天马微电子有限公司 | Display panel and display device |
| CN109448631B (en) * | 2019-01-25 | 2019-04-19 | 南京中电熊猫平板显示科技有限公司 | A kind of display device |
| CN110010096B (en) * | 2019-04-19 | 2022-12-06 | 京东方科技集团股份有限公司 | Display panel, driving method thereof and display device |
| CN112927660B (en) * | 2021-02-09 | 2022-12-06 | 重庆京东方光电科技有限公司 | Driving circuit, driving method thereof and display panel |
| CN114446224B (en) * | 2022-02-15 | 2023-04-14 | 上海天马微电子有限公司 | Pixel structure, display panel and display device |
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| CN1253351A (en) * | 1998-11-04 | 2000-05-17 | 国际商业机器公司 | Driving method and circuit used in pixel multiplex circuit |
| CN101542578A (en) * | 2006-08-30 | 2009-09-23 | Ati科技无限责任公司 | Reduced component display driver and method |
| CN101697269A (en) * | 2009-10-30 | 2010-04-21 | 友达光电股份有限公司 | Pixel circuit and pixel driving method |
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| US9058761B2 (en) * | 2009-06-30 | 2015-06-16 | Silicon Laboratories Inc. | System and method for LCD loop control |
| KR20120057214A (en) * | 2010-11-26 | 2012-06-05 | 주식회사 실리콘웍스 | Source driver output circuit of plat panel display device |
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| CN1253351A (en) * | 1998-11-04 | 2000-05-17 | 国际商业机器公司 | Driving method and circuit used in pixel multiplex circuit |
| CN101542578A (en) * | 2006-08-30 | 2009-09-23 | Ati科技无限责任公司 | Reduced component display driver and method |
| CN101697269A (en) * | 2009-10-30 | 2010-04-21 | 友达光电股份有限公司 | Pixel circuit and pixel driving method |
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