CN109102771B - Display panel and display device - Google Patents
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- CN109102771B CN109102771B CN201810982152.4A CN201810982152A CN109102771B CN 109102771 B CN109102771 B CN 109102771B CN 201810982152 A CN201810982152 A CN 201810982152A CN 109102771 B CN109102771 B CN 109102771B
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- 238000013461 design Methods 0.000 description 5
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The embodiment of the invention provides a display panel and a display device, relates to the technical field of display, and is used for reducing voltage drop on a power signal line and improving the display effect of the display panel. The display panel comprises a non-display area, wherein the non-display area is provided with a power supply signal line, and the power supply signal line comprises a first power supply signal line and a second power supply signal line which are electrically connected; the first power signal wire comprises a power signal input end, the second power signal wire comprises a power signal output end, and the first power signal wire and the second power signal wire extend along a first direction and are arranged along a second direction; the width of the first power supply signal line is larger than the width of the second power supply signal line in the second direction. The display panel is used for realizing picture display.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of display, in particular to a display panel and a display device.
[ background of the invention ]
With the continuous development of display technologies, the frame design of the display panel becomes narrower and narrower. As shown in fig. 1, fig. 1 is a schematic diagram of a display panel in the prior art, since a peripheral circuit 30 ' including a gate circuit (demux) and a test shorting bar (shorting bar) circuit occupies a space of a lower frame 1 ' of the display panel, a power signal line 20 ' needs to extend from the lower frame 1 ' to a display area 2 ' in the manner shown in fig. 1. Therefore, how to reasonably arrange the power signal lines 20 'to reduce the voltage drop on the power signal lines 20' and improve the display effect of the display panel becomes a problem to be solved urgently.
[ summary of the invention ]
In view of this, embodiments of the present invention provide a display panel and a display device, so as to reduce a voltage drop on a power signal line and improve a display effect of the display panel.
In one aspect, an embodiment of the present invention provides a display panel, where the display panel includes a non-display area;
the non-display area is provided with a power signal line; the power supply signal line comprises a first power supply signal line and a second power supply signal line which are electrically connected;
the first power signal line includes a power signal input terminal, and the second power signal line includes a power signal output terminal;
the first power supply signal line and the second power supply signal line extend along a first direction and are arranged along a second direction; the first power supply signal line has a width larger than a width of the second power supply signal line in the second direction.
In another aspect, an embodiment of the present invention provides a display device, which includes the display panel described above.
In the embodiment of the invention, the sizes of all parts of the power signal line positioned in the non-display area are specially set, specifically, the width of the first power signal line comprising the power signal input end is set to be larger than that of the second power signal line along the second direction, so that when a power signal enters the power signal line through the power signal input end, the routing resistance on the first power signal line is smaller because the width of the first power signal line is wider. Along the first direction, each part of the first power signal line is equivalent to an equipotential body, so that along the first direction, the distribution of the power signal on the first power signal line is relatively balanced, the phenomenon that the voltage drop (IR drop) is increased due to the fact that the current of certain paths is relatively large in the prior art is avoided, and the display effect of the display panel is effectively improved.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a display panel in the prior art;
FIG. 2 is an enlarged schematic view of the lower frame 1' of FIG. 1;
FIG. 3 is a schematic diagram of a display panel according to an embodiment of the present invention;
fig. 4 is a diagram showing the result of a simulation test on power supply signal lines of the display panels having different structures shown in fig. 1 and 3;
fig. 5 is an enlarged schematic view of the non-display area 2 of fig. 3;
FIG. 6 is an equivalent circuit diagram of the dashed box of FIG. 5;
FIG. 7 is a schematic cross-sectional view along AA' of FIG. 3;
fig. 8 is a schematic diagram of a display device according to an embodiment of the present invention.
[ detailed description ] embodiments
For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It should be understood that although the terms first, second, third, etc. may be used to describe the power supply signal lines in the embodiments of the present invention, the power supply signal lines should not be limited to these terms. These terms are only used to distinguish the power supply signal lines from each other. For example, the first power supply signal line may also be referred to as the second power supply signal line, and similarly, the second power supply signal line may also be referred to as the first power supply signal line without departing from the scope of embodiments of the present invention.
As shown in fig. 1, fig. 1 is a schematic diagram of a display panel in the prior art, wherein a power signal line 20 'located in a lower frame 1' includes a second power signal line 21 'close to a display area 2' and a first power signal line 22 'far from the display area 2'. The second power signal line 21 'is connected to a power signal line (not shown) in the display region 2', and the first power signal line 22 'is connected to the driver chip IC in the lower frame 1'. When the display panel operates, a power supply signal flows from the driver chip IC to the power supply signal line located in the display area 2 'after sequentially passing through the first power supply signal line 22' and the second power supply signal line 21 ', so as to supply the normal operation of each pixel circuit located in the display area 2'.
However, the inventor of the present application found in the course of research that the display panel including the power signal line with such a design has display unevenness, and as a result, the inventor found that: in the second direction y, since the width of the first power supply signal line 22 'is narrow, the resistance of the first power supply signal line 22' is large. In this way, after the power supply signal is transmitted from the driver chip IC to the first power supply signal line 22 ', since the resistance of the first power supply signal line 22 ' is large, the transmission of the power supply signal on the first power supply signal line 22 ' will preferentially select a portion having a relatively small resistance for transmission. Specifically, as shown in fig. 2, fig. 2 is an enlarged schematic diagram of the lower frame 1 ' of fig. 1, wherein the first power signal line 22 ' includes two power signal input terminals 220 ' connected to the driver IC. In which the power supply signal will preferentially propagate during the propagation of the first power supply signal line 22 'along the path 4' near the power supply signal input 220 'as shown in fig. 2, resulting in a larger current on the path 4' and a smaller current on the remaining paths, such as the path 5 'and the path 6'. The large current of the power signal on the path 4 'causes a large voltage drop (IR drop) on the path 4', which increases the voltage drop on the whole power signal line, and causes a large attenuation of the power signal transmitted to the power signal line of the display area 2 ', so that the luminance of each pixel in the display area 2' is affected.
In view of the above, the present invention provides a display panel, as shown in fig. 3, fig. 3 is a schematic diagram of the display panel according to the embodiment of the present invention, wherein the display panel includes a display area 1 and a non-display area 2, the non-display area 2 is provided with a power signal line 21, the power signal line 21 includes a first power signal line 211 and a second power signal line 212 electrically connected, the first power signal line 211 includes a power signal input terminal 2110, the second power signal line 212 includes a power signal output terminal 2120, the first power signal line 211 and the second power signal line 212 extend along a first direction x and are arranged along a second direction y, and a width d1 of the first power signal line 211 is greater than a width d2 of the second power signal line 212 along the second direction y.
When the display panel is operated, a power supply signal is inputted to the power supply signal line 21 through the power supply signal input terminal 2110, and in the power supply signal line 21, the power supply signal is supplied to each pixel circuit (not shown) in the display region 1 from the power supply signal output terminal 2120 after sequentially passing through the first power supply signal line 211 and the second power supply signal line 212.
In the embodiment of the invention, by specially setting the sizes of the portions of the power signal lines 21 in the non-display area 2, specifically, by setting the width of the first power signal line 211 including the power signal input terminal 2110 to be larger than the width of the second power signal line 212 along the second direction y, when the power signal enters the power signal lines through the power signal input terminal 2110, the wiring resistance on the first power signal line 211 is small because the width of the first power signal line 211 is wider. Along the first direction x, each part of the first power signal line 211 is equivalent to an equipotential body, so that the distribution of the power signal on the first power signal line 211 along the first direction x is relatively balanced, thereby avoiding the phenomenon that the current of some paths is relatively large and the voltage drop (IR drop) is increased in the prior art, and effectively improving the display effect of the display panel.
Specifically, under the same test conditions, the inventors of the present application performed the following tests for display panels having different structures as shown in fig. 1 and 3, respectively: voltages of the first power supply signal line and the second power supply signal line at positions corresponding to different pixel columns in the first direction x are recorded by supplying an electric signal of 4.6V to the power supply signal input terminals of the display panels shown in fig. 1 and 3, respectively, and the test results are shown in fig. 4. Where curve case1in corresponds to the voltage of the first power signal line of the power signal line having the structure shown in fig. 3, curve case1out corresponds to the voltage of the second power signal line of the power signal line having the structure shown in fig. 3, curve case2in corresponds to the voltage of the first power signal line of the power signal line having the structure shown in fig. 1, and curve case2out corresponds to the voltage of the second power signal line of the power signal line having the structure shown in fig. 1. The two power supply signal input terminals 220' of the power supply signal line having the structure shown in fig. 1 and the two power supply signal output terminals 2110 of the power supply signal line having the structure shown in fig. 3 are located near the pixel positions of the 500 th and 1600 th columns, respectively. As can be seen from fig. 4, the first power supply signal line and the second power supply signal line have a small difference in voltage at the positions of different pixel columns for the power supply signal line having the structure shown in fig. 3, while the first power supply signal line and the second power supply signal line have a large difference in voltage near the positions of the pixels in the 500 th and 1600 th columns for the power supply signal line having the structure shown in fig. 1. That is, with the power supply signal line having the structure shown in fig. 3, the attenuation of the signal is small as the power supply signal flows, thereby also verifying that the structure shown in fig. 3 can function to reduce the voltage drop across the power supply signal line.
Exemplarily, as shown in fig. 3, the non-display region 2 further includes a driving chip 22; the first power supply signal line 211 is disposed near the driven chip 22; the driver chip 22 supplies a constant voltage signal to the power supply signal input terminal 2110 of the first power supply signal line 211; the power supply signal output terminal 2120 of the second power supply signal line 212 outputs a constant voltage signal to the display area 1 of the display panel to supply normal operation of each pixel circuit (not shown) located in the display area 1.
Alternatively, a ratio of the width d1 of the first power supply signal line 211 to the width d2 of the second power supply signal line 212 in the second direction y is equal to or greater than 1.5. Specifically, the present inventors set the ratio of the width of the first power signal line 211 to the width of the second power signal line 212 to be different ratios in the second direction y by setting the total size space of the wirings of the first power signal line 211 and the second power signal line 212 to be 200 μm. The voltage at different positions in the second power supply signal line 212 in the first direction x is subjected to simulation test. Specifically, as shown in fig. 5, fig. 5 is an enlarged schematic view of the non-display area 2in fig. 3. Three positions, namely, a position 100 near the power signal input terminal 2110, a position 200 at the edge of the second power signal line 212, and a position 300 at the middle of the second power signal line 212 are selected respectively, and the voltages at the three positions are tested, and the results are shown in table 1.
TABLE 1 Voltage test Meter for different locations in a second Power Signal line
As can be seen from table 1, when the ratio of the widths of the first power supply signal line 211 and the second power supply signal line 212 is 6:4 or more, that is, 1.5 or more, the pressure difference at the position 300 and the position 200 is within 0.006V. That is, when the width ratio of the first power supply signal line 211 to the second power supply signal line 212 is set to 1.5 or more, the voltages at different positions on the second power supply signal line 212 can be controlled to be approximately uniform, that is, the currents at different positions on the second power supply signal line 212 can be controlled to be approximately uniform, thereby effectively solving the problem of the increase in voltage drop caused by the concentrated distribution of the currents on the power supply signal lines in the related art.
Alternatively, as shown in fig. 3, the power supply signal line 21 further includes a plurality of third power supply signal lines 213, the third power supply signal lines 213 are located between the first power supply signal line 211 and the second power supply signal line 212, and the third power supply signal lines 213 are connected to the first power supply signal line 211 and the second power supply signal line 212, respectively. Alternatively, the number of the third power signal lines 213 may be set according to the size of the non-display area 2, for example, the number of the third power signal lines 213 may be set to be equal to the number of columns of pixels, or the number of the third power signal lines 213 may be set to be different from the number of columns of pixels, which is not set in the embodiment of the present invention.
Specifically, as shown in fig. 3, the plurality of third power signal lines 213 extend in the second direction y and are arranged in parallel at intervals in the first direction x; the third power signal line 213 includes a first end portion 2131 and a second end portion 2132, the first end portion 2131 being connected to the first power signal line 211; the second end portion 2132 is connected to the second power signal line 212; the width of the third power signal line 213 is smaller than the first power signal line 211 and/or the second power signal line 212 along the first direction x, so that the third power signal line 213 occupies a smaller space of the non-display area 2, and thus other peripheral circuits may be disposed in a blank area, i.e., the peripheral circuits and the power signal lines are collectively disposed to reduce the size of the non-display area, which is advantageous for the design of a narrow-bezel display panel.
In addition, according to the embodiment of the invention, by reasonably designing the widths of the first power signal line 211 and the second power signal line 212, the currents passing through the third power signal line 213 can be uniformly distributed, and the phenomenon that the current on the third power signal line 213 at some positions is too large is avoided, so that the phenomenon that the third power signal line 213 is burned due to heat concentration caused by too large current is avoided. Specifically, referring to fig. 5 and 6, fig. 6 is an equivalent circuit diagram of a dashed box in fig. 5, where R1 denotes an equivalent resistance of the second power signal line 212 at the dashed box portion, R2 denotes an equivalent resistance of the first power signal line 211 at the dashed box portion, and R3 denotes an equivalent resistance of the third power signal line 213 at the dashed box portion. Still along the second direction y, the wiring total size space of the first power supply signal line 211 and the second power supply signal line 212 was set to 200 μm, the width of the first power supply signal line 211 and the width ratio of the second power supply signal line 212 were set to different ratios as shown in table 1, and the currents flowing through R1, through R2, and through R3 at the position 100 and the position 300 were tested, where the position 100 is directed toward the power supply signal input terminal 2110, so that the R2 at the position 100 was not considered, and the results are shown in table 2.
TABLE 2 Current tester for different positions
As can be seen from table 2, as the width ratio of the first power supply signal line 211 and the second power supply signal line 212 decreases, the currents flowing through R1 at the position 100 and R3 at the position 100 become larger and larger, and the currents flowing through R2 at the position 300 and R3 at the position 300 both become smaller and smaller. That is, as the width ratio of the first power signal line 211 to the second power signal line 212 decreases, the distribution of the current on the power signal lines becomes more concentrated, the current flowing through the middle position 300 gradually decreases, and the current flowing through the position 100 close to the power signal input terminal 2110 becomes more and more large, so that there is a possibility that the trace burn phenomenon may occur due to excessive heat caused by excessive current flowing through a certain position.
Referring to fig. 5 and fig. 6, when the first power signal line 211 is narrow, the resistance of the first power signal line 211 is relatively large, that is, the resistance R2 is relatively large, so that the power signal is influenced by the relatively large resistance R2 after entering the first power signal line 211 through the power signal input terminal 2110, and the path close to the power signal input terminal 2110 is preferentially selected for transmission, thereby causing the current to be mainly distributed on the third power signal line 213 close to the power signal input terminal 2110, so that the current on the third power signal line 213 close to the power signal input terminal 2110 is relatively large, that is, the current flowing through R1 at the position 100 and the current flowing through R3 at the position 100 are relatively large as shown in table 2. Based on this, the embodiment of the invention can make the distribution of the current at different positions more uniform by setting the width ratio of the first power supply signal line 211 and the second power supply signal line 212 to 1.5 or more.
In the second direction y, on the basis that the width ratio of the first power signal line 211 to the second power signal line 212 is set to be equal to or greater than 1.5, the width ratio of the first power signal line 211 to the second power signal line 212 is set to be equal to or less than 9 in the embodiment of the present invention, so as to avoid the current distribution unevenness of the power signal flowing into the display area 1 when the second power signal line 212 is set too narrow, due to the resistance of the second power signal line 212 becoming large, when the power signal flows through the second power signal line 212, thereby avoiding the phenomenon that the power signal flowing into the display area 1 is distributed unevenly everywhere and ensuring the display uniformity of the display area 1.
Alternatively, as shown in fig. 7, fig. 7 is a schematic cross-sectional view along AA' of fig. 3, wherein the plurality of third power signal lines 213 are patterned from the first metal layer M1; the first power signal line 211 and the second power signal line 212 are patterned by the second metal layer M2, wherein the first metal layer M1 and the second metal layer M2 are disposed in different layers, so as to avoid occupying too much space on a certain metal layer and to make room for disposing other peripheral circuits. That is, the peripheral circuits and the power signal lines are collectively arranged to reduce the size of the non-display area, which is advantageous for the design of the narrow-bezel display panel.
Illustratively, as shown in fig. 3, the display panel further includes a plurality of data lines 11 located in the display area 1 and a gating unit 23(demux) located in the non-display area 2; the gate unit 23 is connected to the data lines 11, and is configured to provide a gate signal to the corresponding data line 11; specifically, the gating unit 23 may be designed to have a structure of 1: n according to actual requirements, where n is a positive integer greater than or equal to 2, so as to provide signals to the n data lines 11 through one signal line (not shown) led out from the pins of the driving chip, thereby reducing the number of pins of the driving chip. Illustratively, as shown in fig. 3, the gate unit 23 overlaps the third power signal line 213 to reduce the size of the non-display area 2.
Optionally, with continued reference to fig. 3, the display panel further includes a testing unit 24(shorting bar) located in the non-display area 2, where the testing unit 24 is configured to detect whether the data line 11 can work normally after the display panel is manufactured. Illustratively, the test unit 24 overlaps the third power signal line 213 to reduce the size of the non-display area 2. It should be understood that the relative positions of the test unit 24 and the gating unit 23 may have various designs, and the positional relationship shown in fig. 3 is only an illustration, and the embodiment of the present invention does not limit this.
As shown in fig. 8, fig. 8 is a schematic view of a display device according to an embodiment of the present invention, where the display device includes the display panel 400. The specific structure of the display panel 400 has been described in detail in the above embodiments, and is not described herein again. Of course, the display device shown in fig. 8 is only a schematic illustration, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic book, or a television.
In the embodiment of the invention, the sizes of the portions of the power signal lines 21 in the non-display area 2 of the display panel constituting the display device are specially set, specifically, the width of the first power signal line 211 including the power signal input terminal 2110 is set to be larger than the width of the second power signal line 212 along the second direction y, so that when a power signal enters the power signal lines through the power signal input terminal 2110, the wiring resistance on the first power signal line 211 is smaller because the width of the first power signal line 211 is wider. Along the first direction x, each part of the first power signal line 211 is equivalent to an equipotential body, so that the distribution of the power signal on the first power signal line 211 along the first direction x is relatively balanced, thereby avoiding the phenomenon that the voltage drop (IR drop) is increased due to the relatively large current of some paths in the prior art, and effectively improving the display effect of the display device.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. The display panel is characterized by comprising a non-display area, wherein the non-display area further comprises a driving chip;
the non-display area is provided with a power signal line;
the power supply signal line comprises a first power supply signal line and a second power supply signal line which are electrically connected;
the first power signal line includes a power signal input terminal, and the second power signal line includes a power signal output terminal;
the first power supply signal line and the second power supply signal line extend along a first direction and are arranged along a second direction;
a width of the first power supply signal line is larger than a width of the second power supply signal line in the second direction, wherein the first power supply signal line is disposed near the driver chip.
2. The display panel according to claim 1, wherein a ratio of a width of the first power supply signal line to a width of the second power supply signal line in the second direction is 1.5 or more.
3. The display panel according to claim 2, wherein a ratio of a width of the first power supply signal line to a width of the second power supply signal line in the second direction is 9 or less.
4. The display panel according to claim 1,
the driving chip provides a constant voltage signal to a power supply signal input end of the first power supply signal line;
a power supply signal output terminal of the second power supply signal line outputs the constant voltage signal to a display region of the display panel.
5. The display panel according to claim 4, wherein the power supply signal line further comprises a plurality of third power supply signal lines, the third power supply signal lines being located between the first power supply signal line and the second power supply signal line, the third power supply signal lines being connected to the first power supply signal line and the second power supply signal line, respectively.
6. The display panel according to claim 5, wherein a plurality of the third power supply signal lines extend in the second direction, and are arranged at intervals in parallel in the first direction;
the third power signal line includes a first end portion and a second end portion, the first end portion being connected to the first power signal line; the second end portion is connected to the second power signal line;
the third power supply signal line has a smaller width than the first power supply signal line and/or the second power supply signal line in the first direction.
7. The display panel according to claim 5, wherein a plurality of the third power supply signal lines are formed by patterning a first metal layer;
the first power supply signal line and the second power supply signal line are formed by patterning a second metal layer, wherein the first metal layer and the second metal layer are arranged in different layers.
8. The display panel according to claim 5, further comprising a plurality of data lines in a display region and a gate unit in the non-display region;
the gating unit is connected with the data lines and provides gating signals for the corresponding data lines; the gate unit overlaps the third power signal line.
9. The display panel according to claim 8, further comprising a test unit in the non-display area, the test unit being configured to detect the data line; the test unit overlaps the third power supply signal line.
10. A display device characterized in that it comprises a display panel according to any one of claims 1 to 9.
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| CN110689847B (en) * | 2019-11-12 | 2021-03-05 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN110796980B (en) * | 2019-11-29 | 2023-04-25 | 武汉天马微电子有限公司 | Display panel and display device |
| CN111613657B (en) * | 2020-05-28 | 2023-12-12 | 维沃移动通信有限公司 | Display substrate, display device and mobile terminal |
| CN111613656B (en) * | 2020-05-28 | 2023-08-25 | 维沃移动通信有限公司 | Display substrate, display device and mobile terminal |
| CN111883509A (en) * | 2020-07-30 | 2020-11-03 | 昆山国显光电有限公司 | Display panel |
| WO2022061543A1 (en) * | 2020-09-22 | 2022-03-31 | 京东方科技集团股份有限公司 | Display substrate and display device |
| CN116916701A (en) * | 2022-02-23 | 2023-10-20 | 武汉天马微电子有限公司 | Display panel and display device |
| CN115172428A (en) * | 2022-07-22 | 2022-10-11 | 合肥京东方卓印科技有限公司 | Display substrate and display device |
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