CN105487035A - Verifying method and apparatus for FPGA boundary scan system - Google Patents
Verifying method and apparatus for FPGA boundary scan system Download PDFInfo
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- CN105487035A CN105487035A CN201610049752.6A CN201610049752A CN105487035A CN 105487035 A CN105487035 A CN 105487035A CN 201610049752 A CN201610049752 A CN 201610049752A CN 105487035 A CN105487035 A CN 105487035A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318597—JTAG or boundary scan test of memory devices
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Abstract
The invention provides a verifying method and apparatus for an FPGA (Field-Programmable Gate Array) boundary scan system, which are used for debugging the FPGA boundary scan system on a simulation platform. The method includes the following steps: verifying the simulation characteristics of an IO module of an FPGA through an input instruction/output instruction, wherein the verifying step includes verifying the input characteristics of the IO module and verifying the output characteristics of the IO module; verifying instruction processing of the boundary scan system, wherein instructions include a sampling input instruction, an output test instruction, an output enhancement test instruction and an output training test instruction; and verifying internal connection of the boundary scan system and the FPGA through an internal test instruction, wherein a round trip pathway of the FPGA is gated through user configuration. The verifying method and apparatus can comprehensively and thoroughly verify the FPGA boundary scan system and ensure correctness of functions of the FPGA boundary scan system.
Description
Technical field
The present invention relates to ultra-large programmable integrated circuit technical field, particularly relate to verification method and the system of a kind of field programmable gate array (FPGA:Field-ProgrammableGateArray) border scanning system.
Background technology
Along with the appearance of large scale integrated circuit, printed-circuit board manufacturing technology is to little, micro-, thin development, traditional ICT (information and communication technology) (ICT:InformationCommunicationTechnology) tests the test request having had no idea to meet this series products, because the pin of chip is many, components and parts volume is little, the density of plate is large especially, have no idea to carry out lower probe test at all, therefore joint test behavior tissue (JTAG, JointTestActionGroup) border scanning system arises at the historic moment.Employing border scanning system is embedded in the method in FPGA circuit design, can solve a difficult problem for fpga chip positioning problems test.
Realizing in process of the present invention, inventor finds at least there is following technical matters in prior art:
Although FPGA border scanning system can to diagnosing malfunction during chip operation, the correctness of FPGA border scanning system design itself can not be guaranteed completely, thus causes measuring inaccurate problem to chip.
Summary of the invention
The verification method of FPGA border scanning system provided by the invention and system, can carry out comprehensively complete checking to FPGA border scanning system, can ensure the correctness of FPGA border scanning system function.
First aspect, the invention provides a kind of verification method of FPGA border scanning system, for debugging FPGA border scanning system on emulation platform, comprising:
Verified by the analog feature of input instruction/output order to I/O (IO:Input/Output) module of FPGA, wherein said checking comprises the checking of I/O module input characteristics and the checking to I/O module output characteristics;
Verify the instruction process of border scanning system, wherein said instruction comprises sampling input instruction, exports test instruction, exports enhancing test instruction and exports training test instruction;
To be connected with the inside of FPGA border scanning system by close beta instruction and to verify, wherein the loopback path of FPGA is strobed by user's configuration.
Alternatively, the input characteristics/output characteristics of described I/O module comprises voltage characteristic, current characteristics, differential characteristic and input and output directivity characteristics,
The analog feature of the described I/O module to FPGA carries out checking and comprises:
Screening has the IO port of general function as observation port;
Input characteristics/output characteristics user selected by the configured port of FPGA is configured in described I/O module;
When user select be input characteristics time, to border scanning system input sample input instruction and corresponding bit code, when user's selection be output characteristics time, to the instruction of border scanning system input/output test;
When user select be input characteristics time, TDO port is exported screen the sampled result of IO port and desired value compares, when user's selection be output characteristics time, the Output rusults of screened IO port and desired value are compared;
If comparative result is consistent, then determine that the input characteristics/output characteristics of described I/O module is correct, otherwise, provide error reporting.
Alternatively, the described instruction process to border scanning system is carried out checking and is comprised:
Initialization is carried out to I/O module;
To border scanning system input sample input instruction, export test instruction, export enhancing test instruction and export any one in training test instruction;
To the IO port random incoming bit code with general function;
Border scanning system is had the IO port of general function and the result of TDO port output and expectation value to compare;
If comparative result is consistent, then determine that the command adapted thereto Treatment Design of described border scanning system is correct, otherwise, provide erroneous point.
Alternatively, described connection with the inside of FPGA border scanning system by close beta instruction is carried out checking and comprises:
Initialization is carried out to I/O module;
According to the configuration of user to channel selector in programmable logic block, each IO of gating FPGA is to upper loopback path;
To border scanning system input close beta instruction;
From the excited data sequence of the corresponding each port of boundary scan entrance input, again input close beta instruction;
The result export the TDO port of border scanning system and desired value compare;
If comparative result is consistent, then determines that border scanning system is connected correctly with the inside of FPGA, otherwise determine the inside connection error of border scanning system and FPGA.
Second aspect, the invention provides a kind of demo plant of FPGA border scanning system, for debugging FPGA border scanning system on emulation platform, comprising:
First authentication module, for being verified by the analog feature of input instruction/output order to I/O (IO) module of FPGA, wherein said analog feature comprises input characteristics and output characteristics;
Second authentication module, for verifying the instruction process of border scanning system, wherein said instruction comprises sampling input instruction, exports test instruction, exports enhancing test instruction and exports training test instruction;
3rd authentication module, verify for being connected with the inside of FPGA border scanning system by close beta instruction, wherein the loopback path of FPGA is strobed by user's configuration.
Alternatively, the input characteristics of described I/O module comprises voltage characteristic, current characteristics, differential characteristic and input and output directivity characteristics,
Described first authentication module comprises further:
First selection unit, for screen there is general function IO port as observation port;
First dispensing unit, is configured to described I/O module for input characteristics/output characteristics user selected by the configured port of FPGA;
First input block, when user select be input characteristics time, to border scanning system input sample input instruction and corresponding bit code, when user's selection be output characteristics time, to the instruction of border scanning system input/output test and corresponding bit code;
First comparing unit, when user select be input characteristics time, the sampled result of IO port is screened by the institute exported by TDO port and desired value compares, when user's selection be output characteristics time, the Output rusults of screened IO port and desired value are compared;
First determining unit, if comparative result is consistent, then determines that the input characteristics/output characteristics of described I/O module is correct, otherwise, provide error reporting.
Alternatively, described second authentication module comprises further:
First initialization unit, for carrying out initialization to I/O module;
Second input block, for strengthening test instruction to border scanning system input sample input instruction, output test instruction, output and export any one in training test instruction;
3rd input block, for the IO port random incoming bit code with general function;
Second comparing unit, border scanning system is had the IO port of general function and the result of TDO port output and expectation value and compare, the result wherein only exported by TDO port when performing sampling input instruction and expectation value compare;
Second determining unit, if comparative result is consistent, then determines that the command adapted thereto Treatment Design of described border scanning system is correct, otherwise, provide erroneous point.
Alternatively, described 3rd authentication module comprises further:
Second initialization unit, for carrying out initialization to I/O module;
Gating unit, for according to the configuration of user to channel selector in programmable logic block, each IO of gating FPGA is to upper loopback path;
4th input block, for inputting close beta instruction to border scanning system;
5th input block, for the excited data sequence from the corresponding each port of boundary scan entrance input, inputs close beta instruction again;
3rd comparing unit, compares for the result that exported by the TDO port of border scanning system and desired value;
3rd determining unit, if comparative result is consistent, then determines that border scanning system is connected correctly with the inside of FPGA, otherwise determines the inside connection error of border scanning system and FPGA.
The verification method of the FPGA border scanning system that the embodiment of the present invention provides and device, verify from three border scanning systems of aspect to FPGA, cover boundary scan and relevant all characteristics thereof, the completeness of border scanning system checking is ensured from checking angle, the correctness of FPGA border scanning system function can be ensured, when actual chips goes wrong, reach the effect playing boundary scan expectation function, help positioning chip and outward element connection error and capability error.
Accompanying drawing explanation
Fig. 1 is the process flow diagram of the verification method of one embodiment of the invention FPGA border scanning system;
Fig. 2 is the process flow diagram of the analog feature checking of another embodiment of the present invention border scanning system I/O module;
Fig. 3 is the process flow diagram that the instruction process of another embodiment of the present invention to border scanning system is verified;
Fig. 4 is the process flow diagram of the checking that another embodiment of the present invention border scanning system is connected with FPGA inside;
Fig. 5 is the structural representation of the demo plant of one embodiment of the invention FPGA border scanning system.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The invention provides a kind of verification method of FPGA border scanning system, for debugging FPGA border scanning system on emulation platform, as shown in Figure 1, described method comprises:
S11, verified by the input analog feature of instruction/output order to I/O (IO) module of FPGA, wherein said checking comprises the checking of I/O module input characteristics and the checking to I/O module output characteristics;
S12, the instruction process of border scanning system to be verified, wherein said instruction comprises sampling input instruction, export test instruction, export and strengthen test instruction and export training test instruction;
S13, to be connected to verify by close beta (INTEST) instruction to border scanning system with the inside of FPGA, wherein the loopback path of FPGA is strobed by user's configuration.
Border scanning system comprises 4 external signaling interfaces, is test data input (TDI:TestDataInput) port, test pattern selection (TMS:TestModelSelect) port, test clock (TCK:TestingClock) port and test data output (TDO:TestDataOutput) port respectively.In boundary scan standard agreement 1149.1 and 1149.6, describing the mentality of designing of border scanning system and the master die of specific implementation, and proposing as verifying several test instructions that border scanning system designs.Have the test that four instructions can be used for boundary scan: sample sampling input instruction, is mainly used in the correctness that test chip input port circuit connects; Extest exports test instruction, is mainly used in the correctness that test chip output port circuit connects; Extest_pulse exports and strengthens test instruction, is mainly used in the correctness of test chip AC output port circuit; Extest_train exports training test instruction, is mainly used in the correctness of test chip AC output port circuit.
The verification method of the FPGA border scanning system that the embodiment of the present invention provides, verify from three border scanning systems of aspect to FPGA, cover boundary scan and relevant all characteristics thereof, the completeness of border scanning system checking is ensured from checking angle, the correctness of FPGA border scanning system function can be ensured, when actual chips goes wrong, reach the effect playing boundary scan expectation function, help positioning chip and outward element connection error and capability error.
Further, as shown in Figure 2, the analog feature checking flow process of the I/O module of FPGA is as follows:
S21, user select the analog feature wanting test I/O module, have the IO port of general function as observation port according to the analog feature screening that user selects.
Disperse the feature be present in I/O module according to FPGA border scanning system, boundary scan needs to be embodied by the analog feature of IO in test process.Therefore for all analog features that IO exists, all to cover in checking boundary scan module process.Analog feature is mainly divided into two classes, and a class is input characteristics, another kind of, is output characteristics.Wherein, input characteristics and input characteristics comprise voltage characteristic, current characteristics, differential characteristic and input and output directivity characteristics, such as represent that the parameter of input characteristics has lvds25, lvcmos25, vref1, vref2, vref, vref_internal, represent that the parameter of output characteristics has lvds25, lvcmos25.In the middle of FPGA, its IO port part is used for specific use, and a part is used for common input and output.In the process of the checking of the analog feature of the I/O module to FPGA, need to select to have the IO port of general function as observation port.
S22, judge whether the analog feature that user selects is input characteristics;
If user-selected characteristic is input characteristics, then the analog feature checking flow process of the I/O module of FPGA also comprises:
S231, by the configured port of FPGA, the input characteristics that user selects is configured in described I/O module;
S232, to border scanning system input sample input instruction and corresponding bit code, such as 0 and 1;
S233, TDO port is exported screen the sampled result of IO port and desired value compares;
If S234 comparative result is consistent, namely Output rusults is identical with the bit code of input, then determine that the input characteristics of described I/O module is correct, otherwise, provide error reporting, be convenient to follow-up location.
If user-selected characteristic is output characteristics, then the analog feature checking flow process of the I/O module of FPGA also comprises:
S241, by the configured port of FPGA, the output characteristics that user selects is configured in described I/O module;
S242, to the instruction of border scanning system input/output test and corresponding bit code, such as 0 and 1;
S243, the Output rusults of screened IO port and desired value to be compared;
If S244 comparative result is consistent, namely Output rusults is identical with the bit code of input, then determine that the output characteristics of described I/O module is correct, otherwise, provide error reporting, be convenient to follow-up location.
Further, as shown in Figure 3, checking flow process carried out to the instruction process of border scanning system as follows:
S31, FPGA is in wake-up states, the I/O module of border scanning system is initialized as default configuration.
S32, selection one from input instruction of sampling, output test instruction, output enhancing test instruction, output training test instruction multiple instruction.
The test instruction relating to boundary scan in 1149.1 agreements and 1149.6 agreements has 4: sampling input instruction, is mainly used in the correctness that test chip input port circuit connects; Extest exports test instruction, is mainly used in the correctness that test chip output port circuit connects; Extest_pulse exports and strengthens test instruction, is mainly used in the correctness of test chip AC output port circuit; Extest_train exports training test instruction.Need to test these four instructions in boundary scan checking, and these 4 instructions of alternate run ensure not association between instruction mutually.
S33, instruction from border scanning system input port input selection, and perform this instruction.
S34, at IO port random incoming bit code;
S35, the result IO port of border scanning system and TDO exported and expectation value compare, and wherein only have output at TDO port when performing sampling input instruction, the result therefore only exported by TDO port and expectation value compare;
If S36 comparative result is consistent, then determine that the command adapted thereto Treatment Design of described border scanning system is correct, otherwise, provide erroneous point.If comparative result is different, then to provide concrete erroneous point, facilitate contingency question to locate.This erroneous point can by determining that output port and the periodicity of makeing mistakes are determined.
Further, as shown in Figure 4, border scanning system is as follows with the inner checking flow process be connected of FPGA:
S41, FPGA is in wake-up states, the I/O module of border scanning system is initialized as default configuration.
S42, by being configured the channel selector in programmable logic block, with each IO of gating FPGA to upper loopback path.
Because IO forms the input and output path logic closely similar by two parts, therefore A and B two parts first will determining that each IO is right are verified, be looped back to the path of the output port of B from A input port, and be looped back to the path of output port of A from B input port.This needs to determine according to the annexation of I/O module and programmable logic block in net table, a path is configured in programmable logic block, this feature can realize in FPGA programmable logic device (PLD), according to the loopback path configurating programmable logical block envisioned before in FPGA.
S43, to border scanning system input close beta instruction, and to perform.
When first time input close beta instruction, the data of A port and B port can be exchanged.
S44, excited data sequence from the corresponding each port of boundary scan entrance input, input close beta instruction performing again;
After close beta instruction is input to border scanning system by first time, from the excited data sequence of the corresponding each port of boundary scan entrance input, alternately occurs being formed with 0 and 1, again input close beta instruction.
S45, the result exported by the TDO port of border scanning system and desired value compare;
In the result that each I/O module of boundary scan output port successively Serial output is corresponding.The respective value constituting pad_a and pad_b due to connected mode is exchanged, so the result exported from boundary scan output terminal compares with the data inputted from boundary scan input end, in expected results 0 and 1 position with input data and compare and create exchange.
If S46 comparative result meets expection, then determine that border scanning system is connected with the inside of FPGA and close beta instruction performs correct, otherwise determine the inside connection error of border scanning system and FPGA.
Because FPGA internal path can be selected by configuration, then output to inner result from boundary scan, again by loopback path that programmable logic block configures, turn back to border scanning system inside, therefore need not add any circuit, utilize the resource of FPGA own can realize the inner connecting test of border scanning system.
The embodiment of the present invention also provides a kind of demo plant of FPGA border scanning system, and for debugging FPGA border scanning system on emulation platform, as shown in Figure 5, described device comprises:
First authentication module 11, for being verified by the analog feature of input instruction/output order to I/O (IO) module of FPGA, wherein said analog feature comprises input characteristics and output characteristics;
Second authentication module 12, for verifying the instruction process of border scanning system, wherein said instruction comprises sampling input instruction, exports test instruction, exports enhancing test instruction and exports training test instruction;
3rd authentication module 13, verify for being connected with the inside of FPGA border scanning system by close beta instruction, wherein the loopback path of FPGA is strobed by user's configuration.
The demo plant of the FPGA border scanning system that the embodiment of the present invention provides, verify from three border scanning systems of aspect to FPGA, cover boundary scan and relevant all characteristics thereof, the completeness of border scanning system checking is ensured from checking angle, the correctness of FPGA border scanning system function can be ensured, when actual chips goes wrong, reach the effect playing boundary scan expectation function, help positioning chip and outward element connection error and capability error.
Further, the input characteristics of described I/O module comprises voltage characteristic, current characteristics, differential characteristic and input and output directivity characteristics,
Described first authentication module comprises further:
First selection unit, for screen there is general function IO port as observation port;
First dispensing unit, is configured to described I/O module for input characteristics/output characteristics user selected by the configured port of FPGA;
First input block, when user select be input characteristics time, to border scanning system input sample input instruction and corresponding bit code, when user's selection be output characteristics time, to the instruction of border scanning system input/output test and corresponding bit code;
First comparing unit, when user select be input characteristics time, the sampled result of IO port is screened by the institute exported by TDO port and desired value compares, when user's selection be output characteristics time, the Output rusults of screened IO port and desired value are compared;
First determining unit, if comparative result is consistent, then determines that the input characteristics/output characteristics of described I/O module is correct, otherwise, provide error reporting.
Further, described second authentication module comprises further:
First initialization unit, for carrying out initialization to I/O module;
Second input block, for strengthening test instruction to border scanning system input sample input instruction, output test instruction, output and export any one in training test instruction;
3rd input block, for the IO port random incoming bit code with general function;
Second comparing unit, border scanning system is had the IO port of general function and the result of TDO port output and expectation value and compare, the result wherein only exported by TDO port when performing sampling input instruction and expectation value compare;
Second determining unit, if comparative result is consistent, then determines that the command adapted thereto Treatment Design of described border scanning system is correct, otherwise, provide erroneous point.
Further, described 3rd authentication module comprises further:
Second initialization unit, for carrying out initialization to I/O module;
Gating unit, for according to the configuration of user to channel selector in programmable logic block, each IO of gating FPGA is to upper loopback path;
4th input block, for inputting close beta instruction to border scanning system;
5th input block, for the excited data sequence from the corresponding each port of boundary scan entrance input, inputs close beta instruction again;
3rd comparing unit, compares for the result that exported by the TDO port of border scanning system and desired value;
3rd determining unit, if comparative result is consistent, then determines that border scanning system is connected correctly with the inside of FPGA, otherwise determines the inside connection error of border scanning system and FPGA.
One of ordinary skill in the art will appreciate that all or part of flow process realized in above-described embodiment method, that the hardware that can carry out instruction relevant by computer program has come, described program can be stored in a computer read/write memory medium, this program, when performing, can comprise the flow process of the embodiment as above-mentioned each side method.Wherein, described storage medium can be magnetic disc, CD, read-only store-memory body (Read-OnlyMemory, ROM) or random store-memory body (RandomAccessMemory, RAM) etc.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; the change that can expect easily or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claim.
Claims (8)
1. a verification method for FPGA border scanning system, for debugging FPGA border scanning system on emulation platform, is characterized in that, comprising:
Verified by the analog feature of input instruction/output order to the I/O module of FPGA, wherein said checking comprises the checking of I/O module input characteristics and the checking to I/O module output characteristics;
Verify the instruction process of border scanning system, wherein said instruction comprises sampling input instruction, exports test instruction, exports enhancing test instruction and exports training test instruction;
To be connected with the inside of FPGA border scanning system by close beta instruction and to verify, wherein the loopback path of FPGA is strobed by user's configuration.
2. method according to claim 1, is characterized in that, the input characteristics/output characteristics of described I/O module comprises voltage characteristic, current characteristics, differential characteristic and input and output directivity characteristics,
The analog feature of the described I/O module to FPGA carries out checking and comprises:
Screening has the IO port of general function as observation port;
Input characteristics/output characteristics user selected by the configured port of FPGA is configured in described I/O module;
When user select be input characteristics time, to border scanning system input sample input instruction and corresponding bit code, when user's selection be output characteristics time, to the instruction of border scanning system input/output test;
When user select be input characteristics time, TDO port is exported screen the sampled result of IO port and desired value compares, when user's selection be output characteristics time, the Output rusults of screened IO port and desired value are compared;
If comparative result is consistent, then determine that the input characteristics/output characteristics of described I/O module is correct, otherwise, provide error reporting.
3. method according to claim 1, is characterized in that, the described instruction process to border scanning system is carried out checking and comprised:
Initialization is carried out to I/O module;
To border scanning system input sample input instruction, export test instruction, export enhancing test instruction and export any one in training test instruction;
To the IO port random incoming bit code with general function;
Border scanning system is had the IO port of general function and the result of TDO port output and expectation value to compare;
If comparative result is consistent, then determine that the command adapted thereto Treatment Design of described border scanning system is correct, otherwise, provide erroneous point.
4. the method according to any one of claim 1-3, is characterized in that, described connection with the inside of FPGA border scanning system by close beta instruction is carried out checking and comprise:
Initialization is carried out to I/O module;
According to the configuration of user to channel selector in programmable logic block, each IO of gating FPGA is to upper loopback path;
To border scanning system input close beta instruction;
From the excited data sequence of the corresponding each port of boundary scan entrance input, again input close beta instruction;
The result export the TDO port of border scanning system and desired value compare;
If comparative result is consistent, then determines that border scanning system is connected correctly with the inside of FPGA, otherwise determine the inside connection error of border scanning system and FPGA.
5. a demo plant for FPGA border scanning system, for debugging FPGA border scanning system on emulation platform, is characterized in that, comprising:
First authentication module, for being verified by the analog feature of input instruction/output order to I/O (IO) module of FPGA, wherein said analog feature comprises input characteristics and output characteristics;
Second authentication module, for verifying the instruction process of border scanning system, wherein said instruction comprises sampling input instruction, exports test instruction, exports enhancing test instruction and exports training test instruction;
3rd authentication module, verify for being connected with the inside of FPGA border scanning system by close beta instruction, wherein the loopback path of FPGA is strobed by user's configuration.
6. device according to claim 5, is characterized in that, the input characteristics of described I/O module comprises voltage characteristic, current characteristics, differential characteristic and input and output directivity characteristics,
Described first authentication module comprises further:
First selection unit, for screen there is general function IO port as observation port;
First dispensing unit, is configured to described I/O module for input characteristics/output characteristics user selected by the configured port of FPGA;
First input block, when user select be input characteristics time, to border scanning system input sample input instruction and corresponding bit code, when user's selection be output characteristics time, to the instruction of border scanning system input/output test and corresponding bit code;
First comparing unit, when user select be input characteristics time, the sampled result of IO port is screened by the institute exported by TDO port and desired value compares, when user's selection be output characteristics time, the Output rusults of screened IO port and desired value are compared;
First determining unit, if comparative result is consistent, then determines that the input characteristics/output characteristics of described I/O module is correct, otherwise, provide error reporting.
7. device according to claim 5, is characterized in that, described second authentication module comprises further:
First initialization unit, for carrying out initialization to I/O module;
Second input block, for strengthening test instruction to border scanning system input sample input instruction, output test instruction, output and export any one in training test instruction;
3rd input block, for the IO port random incoming bit code with general function;
Second comparing unit, border scanning system is had the IO port of general function and the result of TDO port output and expectation value and compare, the result wherein only exported by TDO port when performing sampling input instruction and expectation value compare;
Second determining unit, if comparative result is consistent, then determines that the command adapted thereto Treatment Design of described border scanning system is correct, otherwise, provide erroneous point.
8. the device according to any one of claim 5-7, is characterized in that, described 3rd authentication module comprises further:
Second initialization unit, for carrying out initialization to I/O module;
Gating unit, for according to the configuration of user to channel selector in programmable logic block, each IO of gating FPGA is to upper loopback path;
4th input block, for inputting close beta instruction to border scanning system;
5th input block, for the excited data sequence from the corresponding each port of boundary scan entrance input, inputs close beta instruction again;
3rd comparing unit, compares for the result that exported by the TDO port of border scanning system and desired value;
3rd determining unit, if comparative result is consistent, then determines that border scanning system is connected correctly with the inside of FPGA, otherwise determines the inside connection error of border scanning system and FPGA.
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| CN106814306A (en) * | 2016-12-23 | 2017-06-09 | 深圳市紫光同创电子有限公司 | A kind of IOL tests verification method and device |
| CN112798944A (en) * | 2021-01-16 | 2021-05-14 | 西安电子科技大学 | FPGA hardware error attribution analysis method based on online real-time data |
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| CN112798944B (en) * | 2021-01-16 | 2022-05-31 | 西安电子科技大学 | FPGA hardware error attribution analysis method based on online real-time data |
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