CN105471286B - Circuit of synchronous rectification, wireless charging system and synchronous rectification method - Google Patents
Circuit of synchronous rectification, wireless charging system and synchronous rectification method Download PDFInfo
- Publication number
- CN105471286B CN105471286B CN201510907800.6A CN201510907800A CN105471286B CN 105471286 B CN105471286 B CN 105471286B CN 201510907800 A CN201510907800 A CN 201510907800A CN 105471286 B CN105471286 B CN 105471286B
- Authority
- CN
- China
- Prior art keywords
- zero
- signal
- output signal
- crossing comparator
- alternating current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000001360 synchronised effect Effects 0.000 title claims abstract description 82
- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 91
- 238000001514 detection method Methods 0.000 claims description 26
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 3
- 238000005070 sampling Methods 0.000 description 6
- 230000005611 electricity Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000004044 response Effects 0.000 description 4
- 230000000630 rising effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- GOLXNESZZPUPJE-UHFFFAOYSA-N spiromesifen Chemical compound CC1=CC(C)=CC(C)=C1C(C(O1)=O)=C(OC(=O)CC(C)(C)C)C11CCCC1 GOLXNESZZPUPJE-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
-
- H02J7/025—
Abstract
The present invention relates to a kind of circuit of synchronous rectification, wireless charging system and synchronous rectification method, wherein circuit of synchronous rectification includes zero-crossing comparator, the signal obtained from coil to be handled, to obtain the first AC signal and the second AC signal；FPGA module, to obtain the dead zone protection time according to the first AC signal and the second AC signal；Metal-oxide-semiconductor drive module, the dead zone protection time to be obtained according to FPGA module forms the drive signal of metal-oxide-semiconductor rectification module；Metal-oxide-semiconductor rectification module, to realize synchronous rectification according to drive signal, and the signal output after synchronous rectification is extremely loaded.Using the circuit of synchronous rectification, wireless charging system and synchronous rectification method of this kind of structure, on the basis of synchronous rectification efficiency is ensured, reduce the requirement of the real-time control sequential of synchronous rectification, it can adaptively follow the AC signal of different frequency that corresponding dead time is set, save the design cost of synchronous rectification control.
Description
Technical field
The present invention relates to electronic technology field, more particularly to wireless charging, a kind of circuit of synchronous rectification is specifically referred to, wireless
Charging system and synchronous rectification method.
Background technology
Compared to diode rectification, synchronous rectification can reduce rectification circuit own loss, improve overall efficiency.Mesh
Before, usually use synchronous rectification in the circuit application high to efficiency requirements.Go out in order to avoid the MOS switch pipe of alternate conduction
Now simultaneously turn on, synchronous rectification control sequential is complex, such sacrifice circuit structural complexity and stability exchange efficiency for.
In existing synchronous rectification, on the basis of the PWM ripple sequential for being mainly built upon accurate sampling primary side switch pipe,
, it is necessary to the PWM ripple sequential for primary side switch pipe of sampling before being sent to secondary metal-oxide-semiconductor driver, then by Digital Signal Processing.This
A little loops can introduce larger time delay, harsher requirement be proposed for control circuit, while whole work can be reduced
Make the efficiency of system.
In addition, the circuit of synchronous rectification of dereliction switch controlled is in order to obtain higher system effectiveness, the friendship before rectification
When stream (AC) electric current is zero, rectifier switch metal-oxide-semiconductor is switched over.Synchronous rectifier is operated in AC discontinuous current moulds as far as possible
Formula (Discontinuous Conduction Mode, abbreviation DCM).In order to realize DCM control, it is necessary to which high performance AC is electric
Zero cross detection circuit is flowed, this just proposes higher requirement to the offset control of wherein comparator, improves circuit of synchronous rectification
Cost and complexity.
Synchronous rectification is accurate sampling primary-side-control signal PWM waveform, it is desirable to which the zero cross detection circuit response time is fast.This
Outside, when the AC signal being sampled has interference, the wrong waveform such as burr occurs in zero passage detection.Compromise considers zero cross detection circuit
Dynamic response, antijamming capability and complexity, be synchronous commutating control circuit design key.
The content of the invention
The purpose of the present invention is to overcome above-mentioned at least one shortcoming referred in the prior art to adjust there is provided one kind
Burr that the sampled signal pulsewidth of whole zero passage detection circuit output and filtering out occurs in the signal, most handle at last after control
Circuit of synchronous rectification, the nothing of signal feeding synchronous rectification driving circuit, the rectification efficiency of raising circuit of synchronous rectification and reliability
Line charging system and synchronous rectification method.
To achieve these goals, circuit of synchronous rectification of the invention, wireless charging system and synchronous rectification method tool
There is following composition：
The circuit of synchronous rectification, it is mainly characterized by, and described circuit of synchronous rectification includes：
Zero-crossing comparator, the signal obtained from coil to be handled, is exchanged with obtaining zero-crossing comparator first
Output signal and the alternating current output signal of zero-crossing comparator first；
FPGA module, to according to the signal acquisition dead zone protection time obtained from coil；
Metal-oxide-semiconductor drive module, to form metal-oxide-semiconductor rectification mould according to the dead zone protection time of described FPGA module acquisition
The drive signal of block；
Metal-oxide-semiconductor rectification module, to realize synchronous rectification according to described drive signal, and by the signal after synchronous rectification
Output is extremely loaded.
Further, described zero-crossing comparator includes two-way zero-crossing comparator unit, the two-way zero-crossing comparator unit
It is connected respectively with the first end of described coil and the second end, so as to export the alternating current output signal of zero-crossing comparator first and mistake
The alternating current output signal of zero comparator second, each of which, which passes by zero comparator unit, includes first resistor R1, second resistance R2、
3rd resistor R3, the first electric capacity C1, the second electric capacity C2, the first diode D1And comparator, described first resistor R1First
End, the first described electric capacity C1First end be connected with the signal obtained from the respective end of coil, described first electricity
Hinder R1The second end, the first described electric capacity C1The second end, described second resistance R2First end and the described the 1st
Pole pipe D1First end be connected, the first described diode D1The second end ground connection, described second resistance R2The second end,
Described 3rd resistor R3First end, the second described electric capacity C2First end and described comparator positive input
It is connected, described 3rd resistor R3The second termination power Vdd, described the second electric capacity C2The second end and described comparison
The output end of device is connected, and the reverse input end of described comparator meets a voltage Vref, and voltage Vref size is the ratio
The DC component of the signal inputted compared with device positive input, the output end of described comparator is connected with described FPGA module
Connect.
Further, described metal-oxide-semiconductor rectification module includes the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor and the 4th
Metal-oxide-semiconductor, the first end of the source electrode of described the first metal-oxide-semiconductor, the drain electrode of the second described metal-oxide-semiconductor and described coil is exported
The first AC signal be connected, the grid of the first described metal-oxide-semiconductor is connected with first voltage AH, the second described metal-oxide-semiconductor
Grid be connected with second voltage AL, the draining of described the first metal-oxide-semiconductor, the drain electrode of the 3rd described metal-oxide-semiconductor and described
The first end of load be connected；The source electrode of the 3rd described metal-oxide-semiconductor, the drain electrode of the 4th described metal-oxide-semiconductor and described line
The second AC signal for being exported of the second end of circle is connected, the source electrode of described the second metal-oxide-semiconductor, described the 4th metal-oxide-semiconductor
Source electrode, the second end of described load are grounded, and the grid that the 3rd described MOS is closed is connected with tertiary voltage BH, described
The grid of 4th metal-oxide-semiconductor is connected with the 4th voltage BL.
Further, described zero-crossing comparator includes current over-zero detection module and voltage zero-cross detection module；Or
Zero-crossing comparator described in person only includes voltage zero-cross detection module.
Present invention additionally comprises a kind of wireless charging system, it is mainly characterized by, and described system includes transmitting terminal and connect
Receiving end；
Described transmitting terminal includes pwm signal generation module, metal-oxide-semiconductor switch module and primary coil；Described PWM letters
Number generation module is connected with described metal-oxide-semiconductor switch module, and described metal-oxide-semiconductor switch module is connected with described primary coil
Connect；
Described receiving terminal includes secondary coil, the first resonant capacitance Cd, the second resonant capacitance Cs, circuit of synchronous rectification；Institute
The the first resonant capacitance C stateddIt is connected across the two ends of described secondary coil, the first end of described secondary coil passes through described
Second resonant capacitance CsIt is connected with described metal-oxide-semiconductor rectification module, the first end of described secondary coil is also by described
Second resonant capacitance (Cs) be connected with described zero-crossing comparator, the second end of described secondary coil and described zero passage ratio
It is connected compared with device.
The invention further relates to a kind of method of synchronous rectification, it is mainly characterized by, and described method comprises the following steps：
(1) zero-crossing comparator described in is handled the signal obtained from coil, to obtain zero-crossing comparator first
Alternating current output signal and the alternating current output signal of zero-crossing comparator second；
(2) FPGA module described in is according to the signal acquisition dead zone protection time obtained from coil；
(3) it is whole that the dead zone protection time that the metal-oxide-semiconductor drive module described in is obtained according to described FPGA module forms metal-oxide-semiconductor
The drive signal of flow module；
(4) the metal-oxide-semiconductor rectification module described in realizes synchronous rectification according to described drive signal, and by after synchronous rectification
Signal output is extremely loaded.
Further, described step (2) specifically includes following steps：
(2.1) the described alternating current output signal of zero-crossing comparator first of FPGA module detection and described zero passage described in
The alternating current output signal of comparator second whether there is burr；
(2.2) if detecting the described alternating current output signal of zero-crossing comparator first or described zero-crossing comparator second
There is burr in alternating current output signal, then described FPGA module is dead according to updating the frequency of the signal obtained from coil
Start security counters after area's guard time, and entrance safe mode；Then proceed to step (2.4)；
(2.3) if detecting the described alternating current output signal of zero-crossing comparator first and described zero-crossing comparator the
Burr is not present in two alternating current output signals, then continues step (2.7)；
(2.4) FPGA module described in judges whether described security counters count completion；
(2.5) completed if described security counters are counted, the described Zero-cross comparator of described FPGA module detection
The alternating current output signal of device first and the described alternating current output signal of zero-crossing comparator second whether there is burr；
(2.6) if detecting the described alternating current output signal of zero-crossing comparator first or described zero-crossing comparator second
There is burr in alternating current output signal, then continue step (2.2)；
(2.7) if detecting the described alternating current output signal of zero-crossing comparator first and described zero-crossing comparator the
Burr is not present in two alternating current output signals, then described FPGA module obtains the frequency of the signal obtained from coil；Then after
Continuous step (2.9)；
(2.8) do not completed if described security counters are counted, continue step (2.4)；
(2.9) FPGA module described in is according to the described alternating current output signal of zero-crossing comparator first and described zero passage
The frequency of the alternating current output signal of comparator second updates the described dead zone protection time.
Further, the described dead zone protection time includes Start lag times and Stop lead times；Described
FPGA module updates the described dead zone protection time according to the frequency of the signal obtained from coil, is specially：
When the frequency and described zero-crossing comparator second of the described alternating current output signal of zero-crossing comparator first are exchanged
When the frequency of output signal is between 110~130KHz, described Start lag times are T_lag1, during described Stop lead
Between be T_lead1；
When the frequency and described zero-crossing comparator second of the described alternating current output signal of zero-crossing comparator first are exchanged
When the frequency of output signal is between 130~150KHz, described Start lag times are T_lag2, during described Stop lead
Between be T_lead2；
When the frequency and described zero-crossing comparator second of the described alternating current output signal of zero-crossing comparator first are exchanged
When the frequency of output signal is between 150~170KHz, described Start lag times are T_lag3, during described Stop lead
Between be T_lead3；
When the frequency and described zero-crossing comparator second of the described alternating current output signal of zero-crossing comparator first are exchanged
When the frequency of output signal is between 170~190KHz, described Start lag times are T_lag4, during described Stop lead
Between be T_lead4；
When the frequency and described zero-crossing comparator second of the described alternating current output signal of zero-crossing comparator first are exchanged
When the frequency of output signal is between 190~205KHz, described Start lag times are T_lag5, during described Stop lead
Between be T_lead5；
When the described alternating current output signal of zero-crossing comparator first or the described alternating current output signal of zero-crossing comparator second
When there is burr, the described Start lag times are T_lag6, and the described Stop lead times are T_lead6.
Circuit of synchronous rectification, wireless charging system and the synchronous rectification method in the invention are employed, is ensureing synchronous
On the basis of rectification efficiency, the rigors of the real-time control sequential of synchronous rectification are reduced, setting for synchronous rectification control has been saved
Cost is counted, while improving the security reliability of system, can adaptively follow the AC signal of different frequency to set corresponding
Dead time, further improves and has carried out the efficiency of synchronous rectification.
Brief description of the drawings
Fig. 1 is the structural representation of the wireless charging system of the present invention.
Fig. 2 is the circuit diagram of the zero-crossing comparator of the present invention.
Fig. 3 a are the circuit diagram of the metal-oxide-semiconductor rectification module of the present invention.
The timing diagram that Fig. 3 b control for the metal-oxide-semiconductor of the present invention.
Fig. 4 is the oscillogram of the dead zone protection time of the present invention.
Fig. 5 is the control flow chart of the FPGA module of the present invention.
Embodiment
In order to more clearly describe the technology contents of the present invention, carried out with reference to specific embodiment further
Description.
The purpose of the present invention is that instead of that synchronous rectification is self-driven, by gathering the AC signal before rectification, feeding hardware electricity
Road carries out sequential processing, eliminates the burr produced during collection AC signal, it is to avoid it is same that metal-oxide-semiconductor drives two reversed-phase output signals to occur
The situation of phase, improves security reliability and the flexibility of synchronous rectification control.
Refer to shown in Fig. 1, circuit of synchronous rectification of the invention includes：
Zero-crossing comparator, the signal obtained from coil to be handled, is exchanged with obtaining zero-crossing comparator first
Output signal and the alternating current output signal of zero-crossing comparator second；
FPGA module, to according to the signal acquisition dead zone protection time obtained from coil；
Metal-oxide-semiconductor drive module, to form metal-oxide-semiconductor rectification mould according to the dead zone protection time of described FPGA module acquisition
The drive signal of block；
Metal-oxide-semiconductor rectification module, to realize synchronous rectification according to described drive signal, and by the signal after synchronous rectification
Output is extremely loaded.
The control signal of synchronous rectifier is produced as shown in Figure 1, it is necessary to by three modules, zero-crossing comparator, FPGA moulds
Block and metal-oxide-semiconductor drive module.These three modules all existence times postpone, and there is also be switched on and off for metal-oxide-semiconductor rectification module
Delay.In addition reduction synchronous rectification control work clock is considered, to improve system operating efficiency, FPGA module is handled defeated
The MOS drive signals a cycle more late than the signal that zero-crossing comparator is sampled gone out.
In a preferred embodiment, the response speed of zero-crossing comparator directly affects the exchange letter of AC signal first
Number Rx_A/ the second AC signal Rx_B rising edges and the trailing edge sampling degree of accuracy, are referred to shown in Fig. 2, described Zero-cross comparator
Device includes first resistor R1, second resistance R2, 3rd resistor R3, the first electric capacity C1, the second electric capacity C2, the first diode D1And ratio
Compared with device, described first resistor R1First end, the first described electric capacity C1Signal phase of the first end with being obtained from coil
Connection, described first resistor R1The second end, the first described electric capacity C1The second end, described second resistance R2First
End and the first described diode D1First end be connected, the first described diode D1The second end ground connection.Described
Two resistance R2The second end, described 3rd resistor R3First end, the second described electric capacity C2First end and described ratio
Positive input compared with device is connected, described 3rd resistor R3The second termination power Vdd.The second described electric capacity C2
Two ends are connected with the output end of described comparator.The reverse input end of described comparator meets a voltage Vref, the voltage
Vref size is the DC component for the signal that the comparator positive input is inputted, the output end of described comparator with it is described
FPGA module be connected.
In actual applications, it utilizes the first diode D1High-speed switch characteristic, come reduce output delay.First resistor
R1There are two effects：
A) current limliting, prevents the excessive breakdown diode of electric current；
B) with second resistance R2, 3rd resistor R3Potential-divider network is constituted, DC component is provided for comparator positive input.
AC signal the first AC signal the second AC signals of Rx_A/ Rx_B is square wave, so its rising edge and trailing edge
The first electric capacity C rich in high fdrequency component, now low-capacitance1Capacitive reactance is very low for high frequency, the first AC signal Rx_A/ second
AC signal Rx_B passes through the first diode D1Fast charging and discharging is carried out to the electric capacity.So that the first AC signal Rx_A/
The time delay that two AC signal Rx_B reach comparator positive input shortens, and increases the dynamic response speed of Zero-cross comparator circuit
Degree, improves the sampling degree of accuracy at AC signal edge.
Second electric capacity C2Play a part of positive feedback, comparator is had certain hysteresis effect, improve zero-crossing comparator
Antijamming capability.Because the circuit is Zero-cross comparator, therefore VrefTo be equal to the DC component of the positive input signal of comparator.
It ensure that sampled to the first AC signal of AC signal Rx_A, the second AC signal Rx_B degree of accuracy and anti-interference energy
Power, can reduce the complexity designed the sampled signal signal process part；In a preferred embodiment, please
Refering to shown in Fig. 3 a, described metal-oxide-semiconductor rectification module includes the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor and the 4th MOS
Pipe, the source electrode of described the first metal-oxide-semiconductor, the drain electrode of the second described metal-oxide-semiconductor and the first described AC signal Rx_A are connected
Connect, the grid of the first described metal-oxide-semiconductor is connected with first voltage AH, grid and the second voltage AL of described the second metal-oxide-semiconductor
It is connected, the first end of the draining of described the first metal-oxide-semiconductor, the drain electrode of the 3rd described metal-oxide-semiconductor and described load is connected
Connect；The source electrode of the 3rd described metal-oxide-semiconductor, the drain electrode of the 4th described metal-oxide-semiconductor and the second described AC signal Rx_B are connected
Connect, the source electrode of described the second metal-oxide-semiconductor, the source electrode of the 4th described metal-oxide-semiconductor, the second end of described load are grounded, described
The 3rd MOS close grid be connected with tertiary voltage BH, the grid of the 4th described metal-oxide-semiconductor is connected with the 4th voltage BL.
It can be seen that first voltage AH and the 4th voltage BL is same phase in Fig. 3 b, second voltage AL and tertiary voltage BH are
Same phase, difference is that amplitude is different, in order to ensure work that synchronous rectifier can be orderly, need to ensure the voltages of first voltage AH/ the 4th
BL and second voltage AL/ tertiary voltages BH are anti-phase, and forbid occurring while being high situation.
It is delayed in practical application because metal-oxide-semiconductor drive module is present, and metal-oxide-semiconductor is turned on and off there is also delay, therefore
Need to set between the voltage BL and second voltage AL/ tertiary voltages BH of first voltage AH/ the 4th while being low guard time, i.e.,
Dead zone protection time, such as Fig. 4, wherein zero-crossing comparator the first alternating current output signal Cmp_RxA/ zero-crossing comparators second exchange defeated
It is zero-crossing comparator output to go out signal Cmp_RxB, produces the electricity of the voltage BL of metal-oxide-semiconductor drive signal first voltage AH/ the 4th and the 3rd
Press BH/ second voltages AL.Wherein Trunk Width are zero-crossing comparator the first alternating current output signal Cmp_RxA/ zero-crossing comparators
Second alternating current output signal Cmp_RxB pulsewidth, Start lag represent the voltage BL of first voltage AH/ the 4th and tertiary voltage BH/
Second voltage AL rising edge lags behind the time of first AC signal Cmp_RxA/ the second AC signal Cmp_RxB rising edges,
Stop lead represent the voltage BL of first voltage AH/ the 4th and tertiary voltage BH/ second voltage AL trailing edges in advance in Zero-cross comparator
The time of device the first alternating current output signal Cmp_RxA/ zero-crossing comparator the second alternating current output signal Cmp_RxB trailing edges.
Because wireless charging system agreement (Qi) as defined in WPC provides exchange (AC) signal frequency model of wireless charging system
Enclose for 110KHz~205KHz.In order to improve the efficiency of synchronous rectification, therefore different Start are set for different frequency range AC signals
Lag and Stop lead times, such as table 1 below.
The different Start lag of the AC signals different frequency range of table 1 correspondence and Stop lead times
| AC signal frequency range [KHz] | Start lag[ns] | Stop lead[ns] |
| 110~130 | T_lag1 | T_lead1 |
| 130~150 | T_lag2 | T_lead2 |
| 150~170 | T_lag3 | T_lead3 |
| 170~190 | T_lag4 | T_lead4 |
| 190~205 | T_lag5 | T_lead5 |
| Burr | T_lag6 | T_lead6 |
According to digital signal processing module to AC signal zero crossing comparator the first alternating current output signal Cmp_RxA/ zero passages
The second alternating current output signal of comparator Cmp_RxB carries out computation of Period, judges current AC signal is in which frequency range, Ran Houpei
Put corresponding Start lag and Stop lead times.
In a preferred embodiment, current over-zero detection module can be increased, according to current zero-crossing point, with reference to electricity
Zero point is pressed through, the corresponding dead zone protection time is set；Described zero-crossing comparator includes current over-zero detection module and voltage
Zero passage detection module；Or described zero-crossing comparator only includes voltage zero-cross detection module.
The present invention is on the premise of system effectiveness is ensured, accurate Sample AC PWM waveform, while improving zero cross detection circuit
Antijamming capability.The design difficulty of Digital Signal Processing (signal of processing zero passage detection sampling) can so be reduced.Numeral
Signal processor purpose of design is the sampled signal pulsewidth for adjusting zero cross detection circuit output, and filters out the hair occurred in the signal
Thorn.Most at last handle after control signal feeding synchronous rectification driving circuit, improve circuit of synchronous rectification rectification efficiency and can
By property.
Referring to shown in Fig. 1, present invention additionally comprises a kind of wireless charging system, described system include transmitting terminal with
And receiving terminal；
Described transmitting terminal includes pwm signal generation module, metal-oxide-semiconductor switch module and primary coil；Described PWM letters
Number generation module is connected with described metal-oxide-semiconductor switch module, and described metal-oxide-semiconductor switch module is connected with described primary coil
Connect；
Described receiving terminal includes secondary coil, the first resonant capacitance Cd, the second resonant capacitance Cs, circuit of synchronous rectification；Institute
The the first resonant capacitance C stateddIt is connected across the two ends of described secondary coil, the first end of described secondary coil passes through described
Second resonant capacitance CsIt is connected with described metal-oxide-semiconductor rectification module, the first end of described secondary coil is also by described
Second resonant capacitance (Cs) be connected with described zero-crossing comparator, the second end of described secondary coil and described zero passage ratio
It is connected compared with device.
In actual applications, the wireless charging standard released according to wireless charging alliance (WPC), Fig. 1 is wireless charging system
Theory diagram, main point two parts electric energy transmitting terminal Tx and electric energy receiving terminal Rx, electric energy transmission between the two is using electricity
Magnetic induction technology, the technology is realized by two inductance coils：Primary coil Primary Coil and secondary coil Secondary
Coil.Secondary coil senses that AC energy is converted to DC voltage RECT, powering load by circuit of synchronous rectification.Wherein
Synchronous rectification part includes zero-crossing comparator, FPGA module, metal-oxide-semiconductor drive module and metal-oxide-semiconductor rectification module.
The invention further relates to a kind of method of synchronous rectification, described method comprises the following steps：
(1) zero-crossing comparator described in is handled the signal obtained from coil, to obtain zero-crossing comparator first
Alternating current output signal and the alternating current output signal of zero-crossing comparator second；
(2) FPGA module described in is according to the signal acquisition dead zone protection time obtained from coil；
(3) it is whole that the dead zone protection time that the metal-oxide-semiconductor drive module described in is obtained according to described FPGA module forms metal-oxide-semiconductor
The drive signal of flow module；
(4) the metal-oxide-semiconductor rectification module described in realizes synchronous rectification according to described drive signal, and by after synchronous rectification
Signal output is extremely loaded.
In a preferred embodiment, because zero-crossing comparator reference voltage is not preferable；Simultaneously duty factor compared with
When light, receiving terminal Rx AC signals waveform is not preferable square-wave signal, and these factors can influence the ratio of zero-crossing comparator
Compared with performance, there is zero-crossing comparator output zero-crossing comparator the first alternating current output signal Cmp_RxA and zero-crossing comparator second is handed over
There is burr or is high situation simultaneously in stream output signal Cmp_RxB.Now digital signal processing module does both of these case
Safe handling, while when being high, considering in security reliability, the two directly being dragged down into processing.
Wherein, refer to shown in Fig. 5, when FPGA module detect the first alternating current output signal of zero-crossing comparator Cmp_RxA,
When the second alternating current output signal of zero-crossing comparator Cmp_RxB is jagged, when first by current Start lag and Stop lead
Between be arranged to T_lag6 and T_lead6, counted while starting safe mode, gate time may be configured as T_Safe [ns].Count
At the end of time, continue to detect whether jagged, jagged then restarting safe mode counting, Start lag and Stop
The lead times keep；Impulse- free robustness then judges the first alternating current output signal of zero-crossing comparator Cmp_RxA, the zero passage ratio of current AC signals
Compared with device the second alternating current output signal Cmp_RxB frequencies, and corresponding Start lag and Stop lead times are set.
Described step (2) specifically includes following steps：
(2.1) the described alternating current output signal of zero-crossing comparator first of FPGA module detection and described zero passage described in
The alternating current output signal of comparator second whether there is burr；
(2.2) if detecting the described alternating current output signal of zero-crossing comparator first or described zero-crossing comparator second
There is burr in alternating current output signal, then described FPGA module is dead according to updating the frequency of the signal obtained from coil
Start security counters after area's guard time, and entrance safe mode；Then proceed to step (2.4)；
(2.3) if detecting the described alternating current output signal of zero-crossing comparator first and described zero-crossing comparator the
Burr is not present in two alternating current output signals, then continues step (2.7)；
(2.4) FPGA module described in judges whether described security counters count completion；
(2.5) completed if described security counters are counted, the described Zero-cross comparator of described FPGA module detection
The alternating current output signal of device first and the described alternating current output signal of zero-crossing comparator second whether there is burr；
(2.6) if detecting the described alternating current output signal of zero-crossing comparator first or described zero-crossing comparator second
There is burr in alternating current output signal, then continue step (2.2)；
(2.7) if detecting the described alternating current output signal of zero-crossing comparator first and described zero-crossing comparator the
Burr is not present in two alternating current output signals, then described FPGA module obtains the frequency of the signal obtained from coil；Then after
Continuous step (2.9)；
(2.8) do not completed if described security counters are counted, continue step (2.4)；
(2.9) FPGA module described in is according to the described alternating current output signal of zero-crossing comparator first and described zero passage
The frequency of the alternating current output signal of comparator second updates the described dead zone protection time.
Further, the described dead zone protection time includes Start lag times and Stop lead times；Described
FPGA module updates the described dead zone protection time according to the frequency of the signal obtained from coil, is specially：
When the frequency and described zero-crossing comparator second of the described alternating current output signal of zero-crossing comparator first are exchanged
When the frequency of output signal is between 110~130KHz, described Start lag times are T_lag1, during described Stop lead
Between be T_lead1；
When the frequency and described zero-crossing comparator second of the described alternating current output signal of zero-crossing comparator first are exchanged
When the frequency of output signal is between 130~150KHz, described Start lag times are T_lag2, during described Stop lead
Between be T_lead2；
When the frequency and described zero-crossing comparator second of the described alternating current output signal of zero-crossing comparator first are exchanged
When the frequency of output signal is between 150~170KHz, described Start lag times are T_lag3, during described Stop lead
Between be T_lead3；
When the frequency and described zero-crossing comparator second of the described alternating current output signal of zero-crossing comparator first are exchanged
When the frequency of output signal is between 170~190KHz, described Start lag times are T_lag4, during described Stop lead
Between be T_lead4；
When the frequency and described zero-crossing comparator second of the described alternating current output signal of zero-crossing comparator first are exchanged
When the frequency of output signal is between 190~205KHz, described Start lag times are T_lag5, during described Stop lead
Between be T_lead5；
When the described alternating current output signal of zero-crossing comparator first or the described alternating current output signal of zero-crossing comparator second
When there is burr, the described Start lag times are T_lag6, and the described Stop lead times are T_lead6.
Circuit of synchronous rectification, wireless charging system and the synchronous rectification method in the invention are employed, is ensureing synchronous
On the basis of rectification efficiency, the rigors of the real-time control sequential of synchronous rectification are reduced, setting for synchronous rectification control has been saved
Cost is counted, while improving the security reliability of system, can adaptively follow the AC signal of different frequency to set corresponding
Dead time, further improves and has carried out the efficiency of synchronous rectification.
In this description, the present invention is described with reference to its specific embodiment.But it is clear that can still make
Various modifications and alterations are without departing from the spirit and scope of the present invention.Therefore, specification and drawings are considered as illustrative
And it is nonrestrictive.
Claims (7)
1. a kind of circuit of synchronous rectification, it is characterised in that described circuit of synchronous rectification includes：
Zero-crossing comparator, the signal obtained from coil to be handled, to obtain the exchange output of zero-crossing comparator first
Signal and the alternating current output signal of zero-crossing comparator second；
FPGA module, to according to the signal acquisition dead zone protection time obtained from coil；
Metal-oxide-semiconductor drive module, to form metal-oxide-semiconductor rectification module according to the dead zone protection time of described FPGA module acquisition
Drive signal；
Metal-oxide-semiconductor rectification module, to realize synchronous rectification according to described drive signal, and by the signal output after synchronous rectification
To load；
Described FPGA module specifically includes following step according to the signal acquisition dead zone protection time obtained from coil
Suddenly：
(2.1) alternating current output signal of zero-crossing comparator first and described Zero-cross comparator described in FPGA module detection described in
The output signal of device second whether there is burr；
(2.2) if the alternating current output signal of zero-crossing comparator first or described zero-crossing comparator second described in detecting are exchanged
There is burr in output signal, then described FPGA module updates described dead band according to the frequency of the signal obtained from coil and protected
Start security counters after shield time, and entrance safe mode；Then proceed to step (2.4)；
(2.3) if the alternating current output signal of zero-crossing comparator first and described zero-crossing comparator second described in detecting are handed over
Flow output signal and burr is not present, then continue step (2.7)；
(2.4) FPGA module described in judges whether described security counters count completion；
(2.5) completed if described security counters are counted, the described zero-crossing comparator of described FPGA module detection the
One alternating current output signal and the described alternating current output signal of zero-crossing comparator second whether there is burr；
(2.6) if the alternating current output signal of zero-crossing comparator first or described zero-crossing comparator second described in detecting are exchanged
There is burr in output signal, then continue step (2.2)；
(2.7) if the alternating current output signal of zero-crossing comparator first and described zero-crossing comparator second described in detecting are handed over
Flow output signal and burr is not present, then described FPGA module obtains the frequency of the signal obtained from coil；Then proceed to step
Suddenly (2.9)；
(2.8) do not completed if described security counters are counted, continue step (2.4)；
(2.9) FPGA module described in is according to the described alternating current output signal of zero-crossing comparator first and described Zero-cross comparator
The frequency of the alternating current output signal of device second updates the described dead zone protection time.
2. circuit of synchronous rectification according to claim 1, it is characterised in that described zero-crossing comparator includes two-way zero passage
Comparator unit, the two-way zero-crossing comparator unit is connected with the first end of described coil and the second end respectively, so that defeated
Go out the alternating current output signal of zero-crossing comparator first and the alternating current output signal of zero-crossing comparator second, each of which passes by zero comparator
Unit includes first resistor (R1), second resistance (R2), 3rd resistor (R3), the first electric capacity (C1), the second electric capacity (C2), first
Diode (D1) and comparator, described first resistor (R1) first end, the first described electric capacity (C1) first end with
The signal obtained from the respective end of coil is connected, described first resistor (R1) the second end, the first described electric capacity (C1)
The second end, described second resistance (R2) first end and the first described diode (D1) first end be connected, it is described
The first diode (D1) the second end ground connection, described second resistance (R2) the second end, described 3rd resistor (R3)
One end, the second described electric capacity (C2) first end and the positive input of described comparator be connected, the described the 3rd
Resistance (R3) the second termination power (Vdd), the second described electric capacity (C2) the second end and the output end phase of described comparator
Connection, the reverse input end of described comparator meets a voltage Vref, and voltage Vref size is comparator forward direction input
The DC component of the signal of input is held, the output end of described comparator is connected with described FPGA module.
3. circuit of synchronous rectification according to claim 1, it is characterised in that described metal-oxide-semiconductor rectification module includes first
Metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor and the 4th metal-oxide-semiconductor, source electrode, the second described metal-oxide-semiconductor of described the first metal-oxide-semiconductor
Drain electrode and the first AC signal for being exported of first end of described coil be connected, the grid of described the first metal-oxide-semiconductor
It is connected with first voltage (AH), the grid of the second described metal-oxide-semiconductor is connected with second voltage (AL), the first described MOS
The first end of the draining of pipe, the drain electrode of the 3rd described metal-oxide-semiconductor and described load is connected；The 3rd described metal-oxide-semiconductor
The second AC signal that second end of source electrode, the drain electrode of the 4th described metal-oxide-semiconductor and described coil is exported is connected, institute
The source electrode for the second metal-oxide-semiconductor stated, the source electrode of the 4th described metal-oxide-semiconductor, the second end of described load are grounded, and the described the 3rd
The grid that MOS is closed is connected with tertiary voltage (BH), and the grid of the 4th described metal-oxide-semiconductor is connected with the 4th voltage (BL).
4. circuit of synchronous rectification according to claim 1, it is characterised in that described zero-crossing comparator includes current over-zero
Detection module and voltage zero-cross detection module；Or described zero-crossing comparator only includes voltage zero-cross detection module.
5. a kind of wireless charging system of the circuit of synchronous rectification comprising described in any one of Claims 1-4, it is characterised in that
Described system includes transmitting terminal and receiving terminal；
Described transmitting terminal includes pwm signal generation module, metal-oxide-semiconductor switch module and primary coil；Described pwm signal production
Raw module is connected with described metal-oxide-semiconductor switch module, and described metal-oxide-semiconductor switch module is connected with described primary coil；
Described receiving terminal includes secondary coil, the first resonant capacitance (Cd), the second resonant capacitance (Cs), circuit of synchronous rectification；Institute
The the first resonant capacitance (C statedd) it is connected across the two ends of described secondary coil, the first end of described secondary coil passes through described
The second resonant capacitance (Cs) be connected with described metal-oxide-semiconductor rectification module, the first end of described secondary coil also passes through institute
The the second resonant capacitance (C stateds) be connected with described zero-crossing comparator, the second end of described secondary coil and described mistake
Zero comparator is connected.
6. a kind of method that circuit of synchronous rectification based on described in any one of Claims 1-4 realizes synchronous rectification, its feature exists
In described method comprises the following steps：
(1) zero-crossing comparator described in is handled the signal obtained from coil, is exchanged with obtaining zero-crossing comparator first
Output signal and the alternating current output signal of zero-crossing comparator second；
(2) FPGA module described in is according to the signal acquisition dead zone protection time obtained from coil；
(3) the dead zone protection time that the metal-oxide-semiconductor drive module described in is obtained according to described FPGA module forms metal-oxide-semiconductor rectification mould
The drive signal of block；
(4) metal-oxide-semiconductor rectification module described in realizes synchronous rectification according to described drive signal, and by the signal after synchronous rectification
Output is extremely loaded；
Described step (2) specifically includes following steps：
(2.1) alternating current output signal of zero-crossing comparator first and described Zero-cross comparator described in FPGA module detection described in
The alternating current output signal of device second whether there is burr；
(2.2) if the alternating current output signal of zero-crossing comparator first or described zero-crossing comparator second described in detecting are exchanged
There is burr in output signal, then described FPGA module updates described dead band according to the frequency of the signal obtained from coil and protected
Start security counters after shield time, and entrance safe mode；Then proceed to step (2.4)；
(2.3) if the alternating current output signal of zero-crossing comparator first and described zero-crossing comparator second described in detecting are handed over
Flow output signal and burr is not present, then continue step (2.7)；
(2.4) FPGA module described in judges whether described security counters count completion；
(2.5) completed if described security counters are counted, the described zero-crossing comparator of described FPGA module detection the
One alternating current output signal and the described alternating current output signal of zero-crossing comparator second whether there is burr；
(2.6) if the alternating current output signal of zero-crossing comparator first or described zero-crossing comparator second described in detecting are exchanged
There is burr in output signal, then continue step (2.2)；
(2.7) if the alternating current output signal of zero-crossing comparator first and described zero-crossing comparator second described in detecting are handed over
Flow output signal and burr is not present, then described FPGA module obtains the frequency of the signal obtained from coil；Then proceed to step
Suddenly (2.9)；
(2.8) do not completed if described security counters are counted, continue step (2.4)；
(2.9) FPGA module described in is according to the described alternating current output signal of zero-crossing comparator first and described Zero-cross comparator
The frequency of the alternating current output signal of device second updates the described dead zone protection time.
7. the method for synchronous rectification according to claim 6, it is characterised in that the described dead zone protection time includes
Start lag times and Stop lead times；Described FPGA module updates institute according to the frequency of the signal obtained from coil
The dead zone protection time stated, it is specially：
When the frequency and described zero-crossing comparator second of the described alternating current output signal of zero-crossing comparator first exchange output
When the frequency of signal is between 110~130KHz, described Start lag times are T_lag1, and the described Stop lead times are
T_lead1；
When the frequency and described zero-crossing comparator second of the described alternating current output signal of zero-crossing comparator first exchange output
When the frequency of signal is between 130~150KHz, described Start lag times are T_lag2, and the described Stop lead times are
T_lead2；
When the frequency and described zero-crossing comparator second of the described alternating current output signal of zero-crossing comparator first exchange output
When the frequency of signal is between 150~170KHz, described Start lag times are T_lag3, and the described Stop lead times are
T_lead3；
When the frequency and described zero-crossing comparator second of the described alternating current output signal of zero-crossing comparator first exchange output
When the frequency of signal is between 170~190KHz, described Start lag times are T_lag4, and the described Stop lead times are
T_lead4；
When the frequency and described zero-crossing comparator second of the described alternating current output signal of zero-crossing comparator first exchange output
When the frequency of signal is between 190~205KHz, described Start lag times are T_lag5, and the described Stop lead times are
T_lead5；
When the described alternating current output signal of zero-crossing comparator first or the described alternating current output signal of zero-crossing comparator second occur
During burr, the described Start lag times are T_lag6, and the described Stop lead times are T_lead6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510907800.6A CN105471286B (en) | 2015-12-10 | 2015-12-10 | Circuit of synchronous rectification, wireless charging system and synchronous rectification method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510907800.6A CN105471286B (en) | 2015-12-10 | 2015-12-10 | Circuit of synchronous rectification, wireless charging system and synchronous rectification method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105471286A CN105471286A (en) | 2016-04-06 |
| CN105471286B true CN105471286B (en) | 2017-09-29 |
Family
ID=55608691
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510907800.6A Active CN105471286B (en) | 2015-12-10 | 2015-12-10 | Circuit of synchronous rectification, wireless charging system and synchronous rectification method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105471286B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106487235B (en) * | 2016-11-30 | 2017-11-10 | 无锡华润矽科微电子有限公司 | Synchronous rectification time schedule controller, wireless charging full-bridge synchronous rectification circuit and system |
| KR102621927B1 (en) * | 2016-12-20 | 2024-01-08 | 주식회사 엘엑스세미콘 | Rectifier cicrcuit |
| CN107395036B (en) * | 2017-09-06 | 2019-08-13 | 苏州加士革电子科技有限公司 | A kind of single-stage AC-DC voltage-stablizer for wireless charging |
| CN108206640B (en) * | 2017-12-28 | 2020-02-18 | 重庆平伟实业股份有限公司 | Synchronous rectification module, rectification method and manufacturing method thereof |
| CN110040015B (en) * | 2019-05-05 | 2020-11-03 | 中惠创智无线供电技术有限公司 | Control circuit and method of electric vehicle wireless charging system based on LCCL |
| CN112825440A (en) * | 2019-11-20 | 2021-05-21 | 青岛海尔智能技术研发有限公司 | Apparatus and method for wireless power supply |
| CN114688953A (en) * | 2020-12-30 | 2022-07-01 | 华润微集成电路(无锡)有限公司 | Circuit structure for realizing non-inductive BLDC rotor position detection based on MCU detection commutation signal |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101588137A (en) * | 2008-05-23 | 2009-11-25 | 尼克森微电子股份有限公司 | Synchronous rectification controlling device and forward synchronous converter |
| JP4666096B2 (en) * | 2008-09-04 | 2011-04-06 | 株式会社デンソー | DC-DC converter |
| CN102195483B (en) * | 2010-03-04 | 2014-06-04 | 矽创电子股份有限公司 | Dead zone adjusting circuit with coarse adjustment function and fine adjustment function and method |
| CN102377357B (en) * | 2010-08-09 | 2014-06-18 | 尼克森微电子股份有限公司 | Secondary synchronous rectification controller and power switching circuit thereof |
| US20120068548A1 (en) * | 2010-09-16 | 2012-03-22 | Advantest Corporation | Wireless power supply apparatus |
| JP5494838B2 (en) * | 2011-01-26 | 2014-05-21 | 株式会社村田製作所 | Power transmission system |
| CN102790542B (en) * | 2012-07-30 | 2014-08-20 | 华为技术有限公司 | Synchronous rectification control circuit, converter and synchronous rectification control method |
| CN103023335B (en) * | 2012-12-27 | 2015-01-14 | 万仁春 | LLC (logical link control) converter synchronous rectification method and device |
-
2015
- 2015-12-10 CN CN201510907800.6A patent/CN105471286B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN105471286A (en) | 2016-04-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105471286B (en) | Circuit of synchronous rectification, wireless charging system and synchronous rectification method | |
| CN203645381U (en) | Vehicle charger system of electric vehicle | |
| US20170214278A1 (en) | Wireless power feeding system | |
| CN104795903B (en) | Magnetic coupling dual-mode wireless power transmission device and control method thereof | |
| CN103580000B (en) | Switching Power Supply output over-voltage protection method and circuit and the Switching Power Supply with this circuit | |
| CN104734300B (en) | A kind of electric motor car wireless charging circuit and its control method | |
| CN105099238B (en) | Control the method and control circuit of the synchronous rectifier of power converter | |
| CN102684460B (en) | Frequency soft clamp system for quasi-resonant switching power supply and method | |
| CN204290733U (en) | Based on the ultra-wide output voltage range charger of LLC topology | |
| CN104467443A (en) | Super-wide output voltage range charger based on LLC topology and control method | |
| CN104113098A (en) | Wireless charging topological structure and frequency sweep algorithm | |
| CN204216790U (en) | A kind of scanning power supply able to programme | |
| CN105262154A (en) | Wireless charging system for underwater robot and control method of wireless charging system | |
| US20180083491A1 (en) | Wireless power transfer system | |
| CN101997418A (en) | LLC (liquid level control) type serial-parallel resonant converter | |
| CN102185482A (en) | Switch power controller and valley bottom switching method thereof | |
| CN105305578B (en) | A kind of high-efficiency high power wireless electric vehicle charging device | |
| CN103560599A (en) | Current sampling circuit and wireless charging emitting circuit | |
| CN202759634U (en) | LED drive circuit without auxiliary winding | |
| CN105186706A (en) | Automatic sweep-frequency wireless resonant power transmission device and operation method | |
| CN104242658A (en) | Valley-switching digital control circuit of switch power source | |
| CN107332453B (en) | A kind of stage photovoltaic single off-network inverter and its control method | |
| CN206164359U (en) | ACDC converting circuit and control module thereof | |
| Huwig et al. | Digitally controlled synchronous bridge-rectifier for wireless power receivers | |
| CN205039601U (en) | Battery charger |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 214135 -6, Linghu Avenue, Wuxi Taihu international science and Technology Park, Wuxi, Jiangsu, China, 180 Patentee after: China Resources micro integrated circuit (Wuxi) Co., Ltd Address before: No.180-22, Linghu Avenue, Taihu International Science and Technology Park, Wuxi, Jiangsu 214135 Patentee before: WUXI CHINA RESOURCES SEMICO Co.,Ltd. |
|
| CP03 | Change of name, title or address |