CN101588137A - Synchronous rectification controlling device and forward synchronous converter - Google Patents
Synchronous rectification controlling device and forward synchronous converter Download PDFInfo
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- CN101588137A CN101588137A CNA2008100983430A CN200810098343A CN101588137A CN 101588137 A CN101588137 A CN 101588137A CN A2008100983430 A CNA2008100983430 A CN A2008100983430A CN 200810098343 A CN200810098343 A CN 200810098343A CN 101588137 A CN101588137 A CN 101588137A
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Abstract
The invention discloses a synchronous rectification controlling device and a forward synchronous converter. The synchronous rectification controlling device is suitable for the forward synchronous converter. The forward synchronous converter comprises a converting unit, a first rectification switch and a second rectification switch, wherein the converting unit is provided with a primary side and a secondary side, and the first rectification switch and the second rectification switch are coupled with the secondary side of the converting unit. The synchronous rectification controlling device comprises a state judging circuit and a synchronous rectification controller. The state judging circuit is coupled with the secondary side of the converting unit, is used for judging whether the forward synchronous converter works in an critical state of an intermittent current mode and a continuous current mode or works in an intermittent current mode according to the rising slope of the voltage at the secondary side, and is used for outputting a reset signal. The synchronous rectification controller is coupled with the secondary side of the forward synchronous converter and the state judging circuit, and is used for switching off the second rectification switch for a preset time according to the reset signal so as to achieve the purpose of protecting backward current.
Description
Technical field
The invention relates to a kind of synchronous rectificating device and forward synchronous converter, especially refer to a kind of secondary side rise of output voltage slope, with the synchronous rectificating device of judging continuous current pattern and discontinuous current pattern boundary and the forward synchronous converter that uses aforementioned synchronous rectificating device according to transducer.
Background technology
Fig. 1 is the positive activation type transducer schematic diagram of prior art.The positive activation type transducer is provided with a transformer T1, and input power supply VIN, PDM keyer PWM, input filter capacitor C1, initial resistance R1, initial capacitance C2, current sense resistor R2, the rectifier diode D1 and the transistor switch Q1 that is controlled by PDM keyer PWM that couples front stage circuits and provide is provided its primary side.The secondary side of transformer T1 is provided with two output rectifier diode D2, D3, energy storage inductor L, an output filter capacitor C3 and one by resistance R 3, voltage detector 10 that R4 constituted.
In the above-mentioned positive activation type transducer, at the beginning of circuit was starting, power end VIN began by initial resistance R1 initial capacitance C2 charging, and when the current potential of initial capacitor C 2 is charged to when being enough to initial PDM keyer PWM, PDM keyer PWM comes into operation.The duty ratio of the control signal that PDM keyer PWM is produced the detection signal adjustment of input current according to the detection signal of 10 pairs of output voltage VO of voltage detector and current sense resistor R2 is with the conducting of adjusting transistor switch Q1 and the time scale of ending.When output voltage VO was lower than a predeterminated voltage value, the ON time ratio of transistor switch Q1 improved, and when being higher than a predeterminated voltage value, the ON time ratio of transistor switch Q1 reduces, and exported a stable output voltage VO to reach by this.
When transistor switch Q1 was conducting, input power supply VIN provided energy by transformer T1, by rectifier diode D1 to initial capacitance C2 energy storage, and by rectifier diode D2 to energy storage inductor L and output filter capacitor C3 energy storage.When transistor switch Q1 for by the time, initial capacitance C2 releases energy and continues running for PDM keyer PWM, and energy storage inductor L releases energy by rectifier diode D3 to output filter capacitor C3.
Yet,, cause energy loss because all there are forward bias in rectifier diode D2, D3 when electric current is flowed through.Therefore, prior art also has with transistor switch replacement rectifier diode D2, D3 to reduce the practice of energy loss.
Please refer to Fig. 2, be the schematic diagram of the forward synchronous converter of prior art.Utilize transistor switch Q2, Q3 to replace rectifier diode D2, D3 shown in Figure 1.One synchronous commutation controller 12 is according to secondary side voltage VD and dead band setting signal S1, the S2 of transformer T1, and then the conducting of oxide-semiconductor control transistors switch Q2, Q3 and the time that ends.
Fig. 3 is that the forward synchronous converter of prior art operates in the signal sequence schematic diagram under the continuous current pattern.Please also refer to Fig. 2 and Fig. 3, the output end voltage at transformer T1 secondary side two ends is respectively V1, V2, when synchronous rectifying controller 12 detects the terminal voltage V1 rising of transformer T1 secondary side, produce one first synchronizing signal SG1 oxide-semiconductor control transistors switch Q2 conducting, this moment transformer T1 electric current by the terminal voltage V1 of secondary side energy storage inductor L, output filter capacitor C3, transistor switch Q2 the terminal voltage V2 that flows through to transformer T1 secondary side.Synchronous rectifying controller 12 allows transistor switch Q2 shift to an earlier date a Dead Time DT1 than an ON time Ton and ends according to dead band setting signal S1.After transistor switch Q2 ends and passes through Dead Time DT1, synchronous rectifying controller 12 produces one second synchronizing signal SG2 oxide-semiconductor control transistors switch Q3 conducting, at this moment, the energy on the energy storage inductor L is by the path output of output filter capacitor C3 and transistor switch Q3.Synchronous rectifying controller 12 is according to dead band setting signal S2, allow transistor switch Q3 than one deadline Toff in advance a Dead Time DT2 end.The setting of Dead Time DT1, DT2 is conducting for fear of transistor switch Q2, Q3 the time.In Dead Time DT1, DT2, can flow through the earlier body diode (Body Diode, indicate) of transistor switch Q2, Q3 of the secondary side current of transformer T1.
Yet among Fig. 3, a scheduled time ends transistor switch Q2, Q3 and reaches the mode of setting Dead Time DT1, DT2 in advance, causes the situation of electric current adverse current under the interrupted current pattern easily.Please refer to Fig. 4, for the forward synchronous converter of prior art operates in signal sequence schematic diagram under the interrupted current pattern.Owing to operate in the interrupted current pattern, at the PDM keyer PWM oxide-semiconductor control transistors switch Q1 of the primary side of transformer T1 before the next cycle conducting, energy storage inductor L has discharged stored energy, therefore output filter capacitor C3 begins oppositely to export energy to energy storage inductor L, shown in the 4th figure, the regional A less than 0 volt appears in voltage V2.When the situation of adverse current takes place, not only can cause the instability of output voltage VO, also can the unnecessary energy of loss.
Summary of the invention
In view of this, synchronous commutation control device of the present invention is applicable in the forward synchronous converter, in order to the output voltage signal that detects forward synchronous converter to judge the operating state of forward synchronous converter.And when forward synchronous converter entered interrupted current pattern (DCM), synchronous commutation control device of the present invention was stopped the switching of synchronous rectification transistor switch, to avoid the problem of electric current adverse current.
Synchronous commutation control device of the present invention includes a status determination circuit and a synchronous commutation controller.Wherein, status determination circuit is coupled to the secondary side of forward synchronous converter, is the rate of rise according to the secondary side voltage of forward synchronous converter, to judge the operating state of forward synchronous converter.When this forward synchronous converter is operated in the boundary state of interrupted current pattern and continuous current pattern or when being operated in the interrupted current pattern, the rate of rise of secondary side voltage will be lower than a slope value, and this moment, this status determination circuit was exported a reset signal.Synchronous rectifying controller is coupled to the secondary side and the status determination circuit of forward synchronous converter, be secondary side voltage, one first dead band setting signal, one second dead band setting signal according to forward synchronous converter, with one first rectifier switch of control forward synchronous converter and the switching of one second rectifier switch, simultaneously, synchronous rectifying controller, takes place with the problem of avoiding the electric current adverse current with second rectifier switch, one scheduled time length by forward synchronous converter according to reset signal.
In addition, forward synchronous converter of the present invention includes a converting unit, one first switch, a PDM keyer, a synchronous rectifier switch unit and an aforesaid synchronous commutation control device.Converting unit has primary side and secondary side, and its primary side couples an input power supply, and the power conversions that converting unit will be imported power supply becomes an output voltage in its secondary side output.First switch couples the primary side of converting unit.PDM keyer is according to a detection signal of output voltage, in order to control the switching of first switch.The synchronous rectification switch unit has one first rectifier switch and one second rectifier switch, and the synchronous rectification switch unit is coupled to the secondary side of converting unit, in order to this output voltage of rectification.Aforesaid synchronous commutation control device is coupled to the secondary side of converting unit, rise of output voltage slope according to converting unit, to judge the operating state of forward synchronous converter, when forward synchronous converter is operated in the boundary state of interrupted current pattern and continuous current pattern or when being operated in the interrupted current pattern, the rate of rise of secondary side voltage will be lower than a slope value, force this moment to take place with the problem of avoiding the electric current adverse current by second rectifier switch, one scheduled time length.
To sum up, synchronous rectificating device provided by the invention, be applicable in the forward synchronous converter, wherein, synchronous rectificating device is according to the secondary side rise of output voltage slope of forward synchronous converter, be operated in interrupted current pattern and continuous current pattern boundary or be operated in the interrupted current pattern to judge forward synchronous converter, and then point at this moment, force by second rectifier switch, one scheduled time length, take place with the problem of avoiding the electric current adverse current, and then improve the loss that the electric current adverse current causes output voltage instability and energy.
Above general introduction and ensuing detailed description are all exemplary in nature, are in order to further specify claim protection range of the present invention.And about other purpose of the present invention and advantage, will be set forth in follow-up explanation and diagram.
Description of drawings
Fig. 1 is the schematic diagram of the positive activation type transducer of prior art;
Fig. 2 is the schematic diagram of the forward synchronous converter of prior art;
Fig. 3 is that the forward synchronous converter of prior art operates in the signal sequence schematic diagram under the continuous current pattern;
Fig. 4 is that the forward synchronous converter of prior art operates in the signal sequence schematic diagram under the interrupted current pattern;
Fig. 5 is a forward synchronous converter configuration diagram of the present invention
Fig. 6 is a status determination circuit schematic diagram of the present invention; And
Fig. 7 is a status determination circuit work schedule schematic diagram of the present invention.
[primary clustering symbol description]
Prior art:
Transformer T1
Input power supply VIN
PDM keyer PWM
Input filter capacitor C1
Initial resistance R1
Initial capacitance C2
Current sense resistor R2
Rectifier diode D1
Transistor switch Q1
Rectifier diode D2, D3
Energy storage inductor L
Output filter capacitor C3
Resistance R 3, R4
Transistor switch Q2, Q3
Synchronous rectifying controller 12
Dead band setting signal S1, S2
Terminal voltage V1, the V2 of transformer T1 secondary side
Transformer T1 secondary side voltage VD
The first synchronizing signal SG1
The second synchronizing signal SG2
Output voltage VO
The present invention:
Positive activation type transducer 2
Converting unit Tr
The first switch Q1
Synchronous commutation control device 23
Synchronous rectification switch unit 24
Input power supply Vin
Output voltage V D
Feedback voltage signal VFB
Current detection signal VIC
The first rectifier switch Q2
The second rectifier switch Q3
Synchronous rectifying controller 232
The first synchronizing signal SG1
The second synchronizing signal SG2
Energy storage inductor L
Output filter capacitor C3
The first dead band setting signal S1
The second dead band setting signal S2
ON time Ton
Deadline Toff
Dead Time DT1, DT2
Reset signal Sreset
The first reference voltage VREF1
The second reference voltage VREF2
First judges signal SV1
Second judges signal SV2
Postpone to judge signal SV3
Embodiment
With reference to figure 5, be forward synchronous converter configuration diagram of the present invention.Positive activation type transducer 2 mainly is provided with a converting unit Tr, one first switch Q1, a PDM keyer 20, one synchronous rectifier switch unit 24 and a synchronous rectifier control device 23.
Wherein, converting unit Tr has primary side and secondary side, and this primary side couples an input power supply Vin, and the power conversions that will import power supply Vin becomes an output voltage V D to export in the secondary side of converting unit Tr.The first switch Q1 couples the primary side of converting unit Tr.PDM keyer 20 is according to a feedback voltage signal VFB and the current detection signal VIC that flows through the first switch Q1 of forward synchronous converter, to control the change action of the first switch Q1.Synchronous rectification switch unit 24 has one first rectifier switch Q2 and one second rectifier switch Q3, and the first rectifier switch Q2 and the second rectifier switch Q3 are transistor switch.Wherein, the first rectifier switch Q2 coupled in series is in the secondary side of converting unit Tr, as an electric current forward path in the forward synchronous converter 2.And the second rectifier switch Q3 coupled in parallel is in the secondary side of converting unit Tr, as an inductive current release way in the forward synchronous converter 2.
Synchronous commutation control device 23 includes a status determination circuit 230 and a synchronous commutation controller 232.When synchronous rectifying controller 232 detects the secondary side output voltage V D rising of converting unit Tr, produce one first synchronizing signal SG1 and control the first rectifier switch Q2 conducting, this moment converting unit Tr electric current by the output voltage V D end of secondary side energy storage inductor L, output filter capacitor C3, the first rectifier switch Q2 the secondary side other end of flowing through to converting unit Tr.Synchronous rectifying controller 232 and according to the first dead band setting signal S1, allow the first rectifier switch Q2 than an ON time Ton in advance a Dead Time DT1 end.
Simultaneously, after the first rectifier switch Q2 ends and passes through Dead Time DT1, synchronous rectifying controller 232 is to produce one second synchronizing signal SG2 to control the second rectifier switch Q3 conducting, and at this moment, the energy on the energy storage inductor L is by the path output of the output filter capacitor C3 and the second rectifier switch Q3.Synchronous rectifying controller 232 and according to the second dead band setting signal S2, allow the second rectifier switch Q3 than one deadline Toff in advance a Dead Time DT2 end.The setting of Dead Time DT1, DT2 is conducting for fear of the first rectifier switch Q2 and the second rectifier switch Q3 time.In Dead Time DT1, DT2, can flow through the earlier body diode (indicate) of the first rectifier switch Q2 and the second rectifier switch Q3 of the secondary side current of converting unit Tr.
In addition, status determination circuit 230 is coupled to the secondary side of converting unit Tr, is the rate of rise according to the output voltage V D of converting unit Tr, to judge the operating state of forward synchronous converter 2.When forward synchronous converter 2 is operated in the boundary state of interrupted current pattern and continuous current pattern and when being operated in the interrupted current pattern, these status determination circuit 230 outputs one reset signal Sreset.Simultaneously, synchronous rectifying controller 232 is coupled to the secondary side of converting unit Tr, status determination circuit 230 and synchronous rectification switch unit 24, receive reset signal Sreset, and according to reset signal Sreset in order to the second rectifier switch Q3 in the cutoff synchronization rectifier switch unit 24 at least one more than the cycle, the adverse current situation takes place when avoiding forward synchronous converter 2 when the boundary of interrupted current pattern and continuous current pattern or in the interrupted current pattern to reach, wherein this cycle is the operation cycle of positive activation type transducer 2, for example: the operation cycle of PDM keyer 20.
Please refer to Fig. 6, be status determination circuit schematic diagram of the present invention.Status determination circuit 230 of the present invention includes one first voltage detector 2302, one second voltage detector 2304, a delay circuit 2306 and a D buffer 2308.Wherein, the output voltage V D and the one first reference voltage VREF1 of first voltage detector, 2302 comparison operation converting unit Tr secondary sides, and export one first according to comparative result and judge signal SV1.Simultaneously, the output voltage V D and the one second reference voltage VREF2 of second voltage detector, 2304 comparison operation converting unit Tr secondary sides, and export one second according to comparative result and judge signal SV2, wherein the magnitude of voltage of the second reference voltage VREF2 is greater than the first reference voltage VREF1.According to aforementioned, first voltage detector 2302 and second voltage detector 2304 are formed an analog/digital converter.
With reference to figure 6, delay circuit 2306 is coupled to first voltage detector 2302 again, is used to postpone computing first and judges signal SV1, postpones to judge signal SV3 to export one.In addition, the data input pin of D buffer 2308 (D) couples second voltage detector 2304 and judges signal SV2 to receive second, and the operating frequency input (CK) of D buffer 2308 couples delay circuit 2306 with receive delay judgement signal SV3.Simultaneously, D buffer 2308 is according to postpone judging that signal SV3 judges that with second signal SV2 is stored in the D buffer 2308, and the output Q ' that is presented on D buffer 2308 becomes reset signal Sreset.According to aforementioned, delay circuit 2306 is formed a digital processing unit with D buffer 2308.
Cooperate Fig. 6, with reference to figure 7, Fig. 7 is a status determination circuit work schedule schematic diagram of the present invention.First voltage detector, 2302 elder generations are detected the rising edge (risingedge) of the output voltage V D of converting unit Tr secondary side, and the detected output voltage V D of comparison operation and the first reference voltage VREF1 judge signal SV1 according to comparative result output first again.Second voltage detector 2304 also detects the rising edge (rising edge) of the output voltage V D of converting unit Tr secondary side, and the detected output voltage V D of comparison operation and the second reference voltage VREF2 judge signal SV2 according to comparative result output second again.In addition, postpone to judge that signal SV3 judges that by first signal SV1 postpones a time of delay through delay circuit 2306 and produced behind the Td.
Cooperate Fig. 6 again, with reference to figure 7, when time t1-t2, forward synchronous converter 2 operates in interrupted current pattern (DCM), at this moment, the rate of rise of the output voltage V D of the secondary side of converting unit Tr is smaller, so, first judges signal SV1, postpone to judge that signal SV3 and second judges that signal SV2 successively changes into high level (High) from low level (Low) in regular turn, and postpone to judge that the leading edge of signal SV3 triggers (Leading edge trigger) control D buffer 2308, in order to second of low level (Low) is judged that signal SV2 is stored in the D buffer 2308, and presenting high level (High) at the output Q ' of D buffer 2308, this high level (High) is characterized by reset signal Sreset.
Cooperate Fig. 6 again, with reference to figure 7, when time t2-t3, forward synchronous converter 2 operates in the boundary state of interrupted current pattern (DCM) and continuous current pattern (CCM), at this moment, the rate of rise of the output voltage V D of the secondary side of converting unit Tr is big a little, so, first judges signal SV1, postpone to judge that signal SV3 and second judges that signal SV2 successively changes into high level (High) from low level (Low) in regular turn, and (Leading edge trigger) control D buffer 2308 is triggered in the forward position that postpones judgement signal SV3, in order to second of low level (Low) is judged that signal SV2 is stored in the D buffer 2308, and at the output Q of D buffer 2308, present high level (High), this high level (High) is characterized by reset signal Sreset.
Cooperate Fig. 6 again, with reference to figure 7, when time t3-t4, forward synchronous converter 2 operates in continuous current pattern (CCM), at this moment, the slope of the output voltage V D of the secondary side of converting unit Tr is very big, so, first judges that signal SV1, second judges that signal SV2 almost changes into high level (High) from low level (Low) simultaneously, postpones to judge that signal SV3 then changes into high level (High) from low level (Low) subsequently.Therefore, postpone to judge forward position triggering (Leading edge trigger) the meeting control D buffer 2308 of signal SV3, be stored in the D buffer 2308 with the second judgement signal SV2, and present low level (Low) at the output Q ' of D buffer 2308 with high level (High).
With reference to figure 5, synchronous rectifying controller 232 is when receiving reset signal Sreset, make the second rectifier switch Q3 in the synchronous rectification switch unit 24 by a length (at least one is more than the cycle) predetermined the time, this section period second, rectifier switch Q3 no longer carried out conducting with the second synchronizing signal SG2, so can avoid the problem of electric current adverse current to take place.
In sum, synchronous rectificating device provided by the invention, be applicable in the forward synchronous converter, wherein, synchronous rectificating device is according to the secondary side rise of output voltage slope of forward synchronous converter, be operated in interrupted current pattern and continuous current pattern boundary or be operated in the interrupted current pattern to judge forward synchronous converter, and then point at this moment, force second rectifier switch in forward synchronous converter, take place with the problem of avoiding the electric current adverse current, and then improve the loss that the electric current adverse current causes output voltage instability and energy.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (12)
1. synchronous commutation control device, it is characterized in that, be coupled to a forward synchronous converter, this forward synchronous converter comprises one first rectifier switch and one second rectifier switch that has the converting unit of primary side and secondary side and couple the secondary side of this converting unit, and this synchronous commutation control device comprises:
One status determination circuit is coupled to the secondary side of this forward synchronous converter, according to the rate of rise of the secondary side voltage of this converting unit, judges the state of this forward synchronous converter, and exports a reset signal; And
One synchronous commutation controller is coupled to this status determination circuit, and this synchronous rectifying controller is exported one first synchronizing signal and one second synchronizing signal to control this first rectifier switch and this second rectifier switch respectively;
Wherein, when this synchronous rectifying controller receives this reset signal, make this second rectifier switch by a scheduled time length.
2. synchronous commutation control device as claimed in claim 1, it is characterized in that, this synchronous rectifying controller is secondary side voltage, one first dead band setting signal, the one second dead band setting signal according to this converting unit, with one first rectifier switch of controlling this forward synchronous converter and the switching of one second rectifier switch.
3. synchronous commutation control device as claimed in claim 1 is characterized in that, this status determination circuit comprises:
One analog/digital converter is according to the secondary side voltage of this converting unit, to export a plurality of judgement signals; And
One digital processing unit couples this analog/digital converter, these a plurality of judgement signals of this digital processor processes, and export this reset signal.
4. synchronous commutation control device as claimed in claim 3 is characterized in that, this analog/digital converter comprises:
One first voltage detector, the secondary side voltage of this converting unit of comparison operation and one first reference voltage, and export one first and judge signal; And
One second voltage detector, the secondary side voltage of this converting unit of comparison operation and one second reference voltage, and export one second and judge signal, wherein this second reference voltage is greater than this first reference voltage.
5. synchronous commutation control device as claimed in claim 4 is characterized in that, this digital processing unit comprises:
One delay circuit is coupled to this first voltage detector, is used to postpone this first judgement signal, and exports a delay and judge signal; And
One D buffer, have a data input pin, an operating frequency input and an output, wherein, this data input pin couples this second voltage detector to receive this second judgement signal, this operating frequency input couples this delay circuit and judges signal to receive this delay, this D buffer postpones to judge signal according to this second judgement signal and this, exports this reset signal by this output.
6. synchronous commutation control device as claimed in claim 1 is characterized in that, this scheduled time length is longer than an operation cycle of this forward synchronous converter.
7. a forward synchronous converter is characterized in that, comprising:
One converting unit has primary side and secondary side, and wherein, this primary side couples an input power supply, and the power conversions that will import power supply becomes an output voltage to export in this secondary side;
One first switch couples the primary side of this converting unit;
One PDM keyer is controlled the switching of this first switch according to a detection signal of this output voltage;
One synchronous rectifier switch unit has one first rectifier switch and one second rectifier switch, and this synchronous rectification switch unit is coupled to the secondary side of this converting unit, in order to this output voltage of rectification;
One status determination circuit is coupled to the secondary side of this converting unit, is used for the rise of output voltage slope according to this converting unit, judging the state of this forward synchronous converter, and exports a reset signal; And
One synchronous commutation controller is coupled to this status determination circuit and this synchronous rectification switch unit, is used for making this second rectifier switch by a scheduled time length according to this reset signal.
8. forward synchronous converter as claimed in claim 7, it is characterized in that, this synchronous rectifying controller further is coupled to the secondary side of this converting unit, according to secondary side voltage, one first dead band setting signal, the one second dead band setting signal of this converting unit, to control the switching of this first rectifier switch and this second rectifier switch.
9. forward synchronous converter as claimed in claim 7 is characterized in that, this status determination circuit comprises:
One analog/digital converter is according to the output voltage of this converting unit, to export a plurality of judgement signals; And
One digital processing unit couples this analog/digital converter, these a plurality of judgement signals of this digital processor processes, and export this reset signal.
10. forward synchronous converter as claimed in claim 9 is characterized in that, this analog/digital converter comprises:
One first voltage detector, the output voltage of this converting unit of comparison operation and one first reference voltage, and export one first and judge signal; And
One second voltage detector, the output voltage of this converting unit of comparison operation and one second reference voltage, and export one second and judge signal, wherein this second reference voltage is greater than this first reference voltage.
11. forward synchronous converter as claimed in claim 10 is characterized in that, this digital processing unit comprises:
One delay circuit is coupled to this first voltage detector, is used to postpone this first judgement signal, and exports a delay and judge signal; And
One D buffer, have a data input pin, an operating frequency input and an output, wherein, this data input pin couples this second voltage detector to receive this second judgement signal, this operating frequency input couples this delay circuit and judges signal to receive this delay, this D buffer postpones to judge signal according to this second judgement signal and this, exports this reset signal by this output.
12. forward synchronous converter as claimed in claim 7 is characterized in that, this scheduled time length is longer than an operation cycle of this forward synchronous converter.
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| CNA2008100983430A CN101588137A (en) | 2008-05-23 | 2008-05-23 | Synchronous rectification controlling device and forward synchronous converter |
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| CNA2008100983430A CN101588137A (en) | 2008-05-23 | 2008-05-23 | Synchronous rectification controlling device and forward synchronous converter |
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| CN105471286A (en) * | 2015-12-10 | 2016-04-06 | 无锡华润矽科微电子有限公司 | Synchronous rectification circuit, wireless charging system and synchronous rectification method |
| CN106941321A (en) * | 2017-03-22 | 2017-07-11 | 深圳市稳先微电子有限公司 | A kind of control circuit of synchronous rectifier |
| CN106941321B (en) * | 2017-03-22 | 2019-02-01 | 深圳市稳先微电子有限公司 | A kind of control circuit of synchronous rectifier |
| CN110445403A (en) * | 2019-08-12 | 2019-11-12 | 上海南芯半导体科技有限公司 | A kind of SR avoiding improper opening control method |
| CN110445403B (en) * | 2019-08-12 | 2021-04-20 | 上海南芯半导体科技有限公司 | SR false-open prevention control method |
| CN112448585A (en) * | 2019-08-29 | 2021-03-05 | 伟诠电子股份有限公司 | Secondary synchronous rectification power converter and related control method |
| CN112448585B (en) * | 2019-08-29 | 2022-03-01 | 伟诠电子股份有限公司 | Secondary synchronous rectification power converter and related control method |
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