CN105470239B

CN105470239B - Test structure for testing metal connectivity of wafer laminated structure

Info

Publication number: CN105470239B
Application number: CN201410453193.6A
Authority: CN
Inventors: 郑超; 陈福成; 王伟
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2014-09-05
Filing date: 2014-09-05
Publication date: 2020-06-09
Anticipated expiration: 2034-09-05
Also published as: CN105470239A

Abstract

The invention relates to a test structure for testing metal connectivity of a wafer stack structure. The wafer lamination structure comprises a bottom wafer 201 and a top wafer 202 which is positioned above and integrated with the bottom wafer; the test structure includes a plurality of first vertical interconnects penetrating the top wafer 202, a plurality of first lateral interconnects on a side of an upper surface of the top wafer 202, and a plurality of second lateral interconnects on a side of an upper surface of the bottom wafer, wherein the first lateral interconnects and the second lateral interconnects are alternately arranged in a lateral direction, the first lateral interconnects electrically connect adjacent two of the first vertical interconnects at a top portion, and the second lateral interconnects electrically connect adjacent two of the first vertical interconnects at a bottom portion. The invention has the advantages that: the detection structure can quantify the connection stability of the whole loop interface.

Description

Test structure for testing metal connectivity of wafer laminated structure

Technical Field

The invention relates to the field of semiconductors, in particular to a test structure for testing metal connectivity of a wafer laminated structure and a detection structure for testing electromigration and reliability of a connection interface in the wafer laminated structure.

Background

In the field of electronic consumption, multi-function devices are more and more popular with consumers, and compared with devices with simple functions, the manufacturing process of multi-function devices is more complicated, for example, a plurality of chips with different functions need to be integrated on a circuit board, so that a 3D Integrated Circuit (IC) technology is developed, where the 3D Integrated Circuit (IC) is defined as a system-level integrated structure, a plurality of chips are stacked in a vertical plane direction, so as to save space, a plurality of pins can be led out from an edge portion of each chip as needed, and the chips required to be connected with each other are interconnected through metal wires by using the pins as needed, but the above-mentioned method still has many disadvantages, for example, the number of stacked chips is large, and the connection relationship between the chips is complicated, a plurality of metal wires need to be used, and the final wiring manner is disordered, but also leads to an increase in volume.

Therefore, in the 3D Integrated Circuit (IC) technology, a Through Silicon Via (TSV) is mostly used, the TSV is a vertical interconnection penetrating Through a Silicon wafer or a chip, and a method for manufacturing the TSV can be to drill a hole (Via) in the Silicon wafer by etching or laser, and then fill the hole with a conductive material such as copper, polysilicon, tungsten, and the like, so as to achieve interconnection between different Silicon wafers.

In MEMS products, a wafer bonding (wafer bonding) process is often used, and the technology of through-silicon vias TSV is also usually introduced in the process, thereby bringing a new challenge to the wafer stack (stack wafer), i.e., the connectivity problem between the interfaces, and the connection failure between the wafer stacks (stack wafer) will directly cause the reduction of the device yield.

In addition, under the long-time working state, the semiconductor device sometimes suddenly fails, and Electromigration (EM) phenomenon occurs at the connection position of the redistribution layer (RDL) and the through silicon vias TSV through detection, so that the circuit connection fails.

At present, a semiconductor device of a 3D wafer stack (stack wafer) faces the reliability problem of multiple interfaces (interfaces), and most of the existing detection methods find out the failed interfaces through defect point analysis (Hot Spot), slicing and the like after the device fails, but the method consumes a lot of time.

The existing independent test structure (Testkey) can only test the EM phenomenon of each interface in a single mode and cannot reflect the integral condition of combination; or only a part of the structure can be monitored (monitor), and the whole connecting system cannot be tested.

There is therefore a need for further improvements to the test structures described so far in order to eliminate the above-mentioned problems.

Disclosure of Invention

In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In order to overcome the problems existing in the prior art, the invention provides a test structure for testing the metal connectivity of a wafer stack structure,

the wafer lamination structure comprises a bottom wafer 201 and a top wafer 202 which is positioned above and integrated with the bottom wafer;

the test structure includes a plurality of first vertical interconnects penetrating the top wafer 202, a plurality of first lateral interconnects on a side of an upper surface of the top wafer 202, and a plurality of second lateral interconnects on a side of an upper surface of the bottom wafer, wherein the first lateral interconnects and the second lateral interconnects are alternately arranged in a lateral direction, the first lateral interconnects electrically connect adjacent two of the first vertical interconnects at a top portion, and the second lateral interconnects electrically connect adjacent two of the first vertical interconnects at a bottom portion.

Optionally, the first vertical interconnect comprises a through silicon via 205.

Optionally, the first lateral interconnect includes a rerouting layer 206.

Optionally, the second lateral interconnect comprises a metal pad 203 located below the first vertical interconnect.

Optionally, a metal layer is further disposed between the first vertical interconnection and the metal pad, and the metal layers under the adjacent first vertical interconnections are spaced apart.

Optionally, openings are further formed in the bottom wafer and the top wafer to expose second lateral interconnects at both ends of the test structure as detection ports.

The invention also provides a detection structure for testing electromigration and reliability of a connection interface in a wafer laminated structure, which is characterized in that the wafer laminated structure comprises a bottom wafer 201 and a top wafer 202 which is positioned above the bottom wafer and is integrated with the bottom wafer;

the detection structure comprises at least two detection units, and the detection units are arranged at intervals;

each detection unit comprises two first vertical interconnects arranged at intervals, a first transverse interconnect which is positioned on one side of the upper surface of the top wafer and is electrically connected with the first vertical interconnects, and a third transverse interconnect which is positioned on one side of the upper surface of the bottom wafer and is arranged at intervals below the first vertical interconnects.

Optionally, the first lateral interconnect includes a rerouting layer 206.

Optionally, the third lateral interconnect comprises a metal layer.

Optionally, a metal pad is further disposed below the metal layers at two ends of the detection structure.

The invention provides a test structure for online monitoring (inline monitor) for solving the problems in the prior art, which can cover the whole connection interface of the current trend and test the stability of metal connection.

The invention has the advantages that:

(1) the detection structure can quantify the connection stability of the whole loop interface.

(2) Through the WAT test, the condition of the whole loop can be accurately quantified.

(3) The repeatability and reliability of the process can be tested by this structure.

Drawings

The following drawings of the invention are included to provide a further understanding of the invention. There are shown in the drawings, embodiments and descriptions thereof, which are used to explain the principles and apparatus of the invention. In the drawings, there is shown in the drawings,

FIG. 1a is a schematic diagram of a wafer stack connection in the prior art;

FIG. 1b is a schematic diagram illustrating a defect in a wafer stack connection in the prior art;

FIGS. 2a-2b are schematic diagrams of a wafer stack open circuit detection structure and a layout structure thereof according to an embodiment of the invention;

fig. 2c-2d are schematic diagrams of a detection structure for wafer stack connection stability and layout structure thereof according to an embodiment of the present invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

In a MEMS product, a wafer bonding (wafer bonding) process is often used, in which a TSV technology is also usually introduced, as shown in fig. 1a, the MEMS product includes a bottom wafer 101 and a top wafer 104, wherein the bottom wafer and the top wafer are connected through a through-silicon via 105, a metal layer 103 and a metal pad 102 are further formed in the bottom wafer below the through-silicon via 105, and a redistribution layer 106 is further formed above the through-silicon via 105, and since the device has a large number of bonding interfaces, the connectivity problem between the interfaces becomes a problem to be considered.

The device shown in fig. 1a faces reliability problems of multiple connection interfaces (interfaces), such as between the redistribution layer 106 and the through-silicon via 105, between the through-silicon via 105 and the metal layer 103, a void occurring in the through-silicon via 105 itself, a void occurring between the metal layer 103 and the metal pad 102, a fusion bridge between the metal layers 103, and the like, and any Interface occurring problem may cause performance reduction or failure of the device, as shown in fig. 1b, the left drawing and the right drawing are SEM schematic diagrams of the Interface between the redistribution layer 106 and the through-silicon via 105, and the failure of the device caused by the void occurring in the through-silicon via 105 itself, respectively.

In the existing detection method, a failed interface is found out through defect point analysis (Hot Spot), Detape, FA slicing and the like after the device fails, but the method consumes a large amount of time. At present, an independent test structure (Testkey) can only test the EM phenomenon of each interface in a single mode and cannot reflect the integral condition of combination. Or only a part of the structure can be monitored (monitor), and the whole connecting system cannot be tested.

Example 1

In order to solve the problems in the prior art, the present invention provides a test structure for testing metal connectivity of a wafer stack structure, including:

The detection structure can cover the whole connection interface of the current trend, and can integrally test the metal connectivity of the whole system.

The detection structure in an embodiment of the present invention is further described with reference to fig. 2c-2d, where fig. 2c is a schematic structural diagram of the detection structure, and fig. 2d is a schematic layout structural diagram of the detection structure.

As shown in fig. 2c, various active devices, such as CMOS devices and other active devices, may also be formed in the bottom wafer 201, and the active devices are not limited to a certain type and are not described herein again.

Various MEMS devices, such as acceleration sensors, inertial sensors, pressure sensors, etc., may be included in the top wafer 202, but are not limited to the above examples, and other devices may be further included in the top wafer.

The bottom wafer 201 and the top wafer 202 are bonded into a whole, wherein the bonding manner of the bottom wafer 201 and the top wafer 202 may be various, for example, by thermal bonding or other methods, and details thereof are not repeated herein.

Wherein the first vertical interconnect comprises a through silicon via 205 and the first lateral interconnect comprises a redistribution layer 206.

The second lateral interconnect comprises a metal pad 203 located below the first vertical interconnect. Metal layers are further arranged between the first vertical interconnection pieces and the metal pads, and the metal layers below the adjacent first vertical interconnection pieces are arranged at intervals.

As shown in fig. 2c, at least two through-silicon vias 205 may be included in each of the detection structures, and the two through-silicon vias 205 may be disposed in the top wafer 202 in parallel and penetrate through the top wafer 202.

Specifically, the top of the top wafer 202 exposes the top of the through-silicon-via 205, and the bottom of the through-silicon-via passes through the top wafer and connects to the metal layer 204 in the bottom wafer 201.

Optionally, the through-silicon via 205 includes a conductive layer, a barrier layer and a liner layer from inside to outside, wherein the conductive layer may be made of a metal material commonly used in the art, such as one of Pt, Au, Cu, Ti and W.

The distance between the two through silicon vias 205 is not limited to a certain range of values, and may be set as required.

The tops of the through-silicon vias are connected by a redistribution layer 206, wherein the redistribution layer 206 is located on one side of the upper surface of the top wafer 202 and can directly contact with the top wafer to realize electrical connection between the two through-silicon vias 205, and a connection interface is formed between the redistribution layer 206 and each through-silicon via 205.

The material and the forming method of the redistribution layer 206 may be selected from methods commonly used in the art, and are not described herein again.

Further, the metal layer 204 is disposed below each of the through silicon vias 205, and is directly connected to the metal layer 204, so as to form a connection interface between the metal layer 204 and the through silicon vias 205.

The metal layers 204 are located in the bottom wafer 201, and the metal layers 204 are not in contact with each other but are spaced apart from each other.

Alternatively, the metal layer 204 may be a metal layer commonly used in the art, such as copper, but this is not limited to this example.

The metal pads 203 are disposed below the metal layers 204 and are used for connecting the metal layers 204 disposed at intervals to form a metal layer-metal pad connection interface and simultaneously realize electrical connection below adjacent through silicon vias.

The metal pad 205 may be made of a metal material commonly used in the art, for example, metal Al, but this is not limited to this example.

Openings are also formed in the bottom wafer and the top wafer to expose metal pads 205 at both ends of the test structure as detection ports.

In the detection structure, the tops of the adjacent silicon through holes are connected through a redistribution layer, the lower parts of the silicon through holes are connected through metal bonding pads, the redistribution layer and the metal bonding pads are arranged in a staggered mode in the transverse direction, and the detection structure is integrally connected to form a serpentine bent structure so as to cover the whole connection interface of the current trend.

Specifically, as shown in fig. 2c, the top of the first through-silicon-via 20 is connected to the top of the second through-silicon-via 21 through a redistribution layer, the top of the second through-silicon-via 21 is connected to the top of the third through-silicon-via 22 through a metal layer and a metal pad connected to the metal layer, and so on, so that the redistribution layer and the metal pad are alternately arranged in the transverse direction to form a serpentine structure.

The detection structure can connect all connection interfaces contained in the wafer lamination layer to form an interface covering the whole current system, the connection interfaces comprise an interface between a metal pad and a metal layer, an interface between the metal layer and a silicon through hole and an interface between the silicon through hole and a redistribution layer, in addition, whether holes exist in the silicon through hole can be detected, so that the comprehensive detection of the electrical connection stability in the wafer lamination layer is realized, the current flow direction is shown as a right graph in fig. 2d, and a left graph is a layout structure schematic diagram of the detection structure.

Alternatively, in the present invention, a plurality of metal layer-through silicon via repeating units may be included between the metal pad layers, that is, the through silicon vias and the metal layers are alternately disposed to form a plurality of layers, and then the wiring layer and the metal pad are connected.

The invention provides a test structure for online monitoring (inline monitor) for solving the problems in the prior art, which can cover the whole connection interface of the current trend and test the metal connectivity.

The invention has the advantages that:

(1) this test structure can quantify the connection stability of the entire loop interface.

Example 2

The invention also provides a detection structure for testing electromigration and reliability of a connection interface in a wafer lamination structure, which comprises:

wherein each of the inspection units includes two first vertical interconnects spaced apart from each other, a first lateral interconnect electrically connected to the first vertical interconnects on the side of the upper surface of the top wafer 202, and a third lateral interconnect spaced apart from the first vertical interconnects on the side of the upper surface of the bottom wafer.

The short circuit detection structure provided by the invention is designed into a special test structure aiming at wafer lamination (stack wafer), and can cover the whole connection interface of the current trend and test the Electromigration (EM) and stability (Reliability) of a connecting line.

As shown in fig. 2a, various active devices, such as CMOS devices and other active devices, may also be formed in the bottom wafer 201, and the active devices are not limited to a certain type and are not described herein again.

Wherein the first vertical interconnect comprises a through silicon via 205.

The first lateral interconnect includes a rerouting layer 206.

The third lateral interconnect includes a metal layer.

And metal pads are also arranged below the metal layers at the two ends of the detection structure.

In each detection unit, the tops of the through silicon vias are connected through a redistribution layer 206, wherein the redistribution layer 206 is located on the top wafer 202 and connected to the tops of the through silicon vias 205 to achieve electrical connection between the two through silicon vias 205, and a connection interface is formed between the redistribution layer 206 and each through silicon via 205.

In the detection structure, metal pads are not arranged below each metal layer, no via is formed between the two detection units, no metal pad is arranged below the adjacent metal layer in the two detection units, but metal pads are formed at two ends of the detection structure, as shown in fig. 2a, and the layout structure is shown in fig. 2 b.

When the temperature rises or the through silicon vias expand due to other reasons, adjacent detection units may contact each other to cause short circuit, as shown in fig. 2a, bridging occurs between the through silicon vias, and the detection structure may be used to test Electromigration (EM) and stability (Reliability) of the connection lines, so as to ensure good stability of the wafer stack.

The metal layer and the silicon through hole are made of metal copper;

the metal bonding pad is an aluminum bonding pad.

The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A detection structure for testing electromigration and reliability of a connection interface in a wafer lamination structure, wherein the wafer lamination structure comprises a bottom wafer and a top wafer which is positioned above the bottom wafer and is integrated with the bottom wafer;

each detection unit comprises two first vertical interconnection pieces arranged at intervals, a first transverse interconnection piece located on one side of the upper surface of the top wafer and electrically connected with the first vertical interconnection pieces, and a third transverse interconnection piece located on one side of the upper surface of the bottom wafer and arranged at intervals below the first vertical interconnection pieces, wherein the third transverse interconnection pieces between every two adjacent detection units are not in contact, and when the first vertical interconnection pieces expand, the first vertical interconnection pieces between every two adjacent detection units are in contact with each other to generate bridging, so that the detection structure is conducted to test.

2. The detection structure of claim 1, wherein the first vertical interconnect comprises a through silicon via.

3. The detection structure of claim 1, wherein the first lateral interconnect comprises a redistribution layer.

4. The sensing structure of claim 1, wherein the third lateral interconnect comprises a metal layer.

5. The test structure of claim 4, further comprising a metal pad disposed under the metal layer at each end of the test structure, wherein the metal pad is not disposed under the metal layer in the test cell between the ends.