CN105468540B - L2 Cache and its consistency implementation method and data processing system - Google Patents
L2 Cache and its consistency implementation method and data processing system Download PDFInfo
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- CN105468540B CN105468540B CN201410448635.8A CN201410448635A CN105468540B CN 105468540 B CN105468540 B CN 105468540B CN 201410448635 A CN201410448635 A CN 201410448635A CN 105468540 B CN105468540 B CN 105468540B
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Abstract
The invention discloses a kind of L2 Cache and its consistency implementation method and data processing system, the L2 Cache includes Slave interface, controller, Master Interface and RAM；Slave interface, for receiving consistency access indication signal and access, when receiving consistency access indication signal, determining access is that consistency accesses, and accesses indication signal according to consistency and access and classify to access, forms instruction information according to classification results；Controller, according to instruction information inquiry operation data in RAM, executes consistency operation according to instruction information after inquiring operation data for receiving instruction information；Master Interface, for when non-inquiry operation data, accessing indication signal and consistency access in RAM to peripheral hardware output-consistence according to instruction information and operation data being output to external memory according to instruction information after inquiring operation data.
Description
Technical field
The present invention relates to the caching technology of data processing field more particularly to a kind of L2 Cache and its consistency realization sides
Method and data processing system.
Background technique
In the multi-core processor of shared storage, cache memory Cache can be by the number in shared memory space
According to local is buffered in, multicore is accelerated to obtain the process of data.Since the storage view that each processor is seen is to pass through local
What Cache was obtained, therefore for the data of the same storage location, different processors may get different numbers
According to value.
At present in multiple nucleus system, it will be integrated in the caching on same circuit board or on mainboard with central processor CPU, claim
For level-one L1 Cache, and it is known as second level L2 Cache with the independent caching of CPU.In the prior art, in the control of processor
Cache consistency between lower realization and L1 Cache；However in order to improve the performances such as system processing speed, a cluster Cluster
Interior multiple CPU usually can also share a L2 Cache；However the existing L2 Cache separately positioned with CPU is not support
Consistency access, this will lead to L1 Cache and L2 Cache can not achieve Cache consistency；L2 Cache can not achieve
Cache consistency.
Obviously Cache consistency cannot be safeguarded well, it will cause processing error rate caused by data inconsistency high
And the problems such as treatment effeciency is low.
Summary of the invention
In view of this, can receive consistency access an embodiment of the present invention is intended to provide one kind realizes Cache consistency
L2 Cache and data processing system；The embodiment of the present invention also provides the L2 Cache consistency implementation method simultaneously.
In order to achieve the above objectives, the technical scheme of the present invention is realized as follows:
First aspect of the embodiment of the present invention provides a kind of second level independence Cache L2 Cache, the L2 Cache packet
Include Slave interface, controller, Master Interface and RAM；
The Slave interface is accessed for receiving consistency access indication signal and access when receiving the consistency
Determine that the access is that consistency accesses, and accesses indication signal and the access to the visit according to consistency when indication signal
It asks and classifies, form instruction information according to classification results；
The controller, for receiving the instruction information, according to the instruction information in the RAM inquiry operation number
According to according to instruction information execution consistency operation after inquiring the operation data；
The Master Interface, when for not inquiring the operation data in the RAM, according to the instruction information to
Peripheral hardware exports the consistency access indication signal and consistency access, and according to institute after inquiring the operation data
It states instruction information and the operation data is output to external memory.
Preferably,
The consistency access indication signal includes consistency access type indication signal；
The Slave interface accesses class according to the consistency for receiving the consistency access type indication signal
Type indication signal determines that the access is that consistency accesses.
Preferably,
The consistency access indication signal further includes consistency access overall signal；
The Slave interface includes the first read address channel, the first reading data channel and the first write address channel；
The Slave interface accesses global letter according to the consistency for receiving consistency access overall signal
Number driving forms Slave interface control signal, drives according to the Slave interface control signal each in the Slave interface
The access of consistency described in the channel reception；
First read address channel, for receiving the consistency access type indication signal；
Described first reads data channel, reads response signal for sending according to the query result to request source；
First write address channel, for receiving the external memory more new signal of consistency access.
Preferably,
Consistency access overall signal includes inquiry of the operation data of the consistency access in other Cache
State and the request source of consistency access.
Preferably,
The Master Interface includes the second read address channel, the second reading data channel and the second write address channel；
Second read address channel when for not inquiring the operation data in the RAM, exports the consistency
Access indication signal；
Described second reads data channel, for receiving reading response signal and listening to response signal；
Second write address channel writes the operation data in external memory and invalid Cache for exporting
The indication signal of the operation data.
Preferably,
The L2 Cache further include:
First buffering area, for store access type, in other Cache inquiry state, in the L2 Cache
Inquiry state and consistency access request source, for being mentioned to inquire the operation data and realization Cache consistency
For according to information.
Preferably,
Institute first states buffer area, is also used to store invalid failure information, according to the invalid failure notification message to described
Request source.
Preferably,
The RAM includes Data RAM and Tag RAM；The Data RAM is used for storage operation number evidence；The Data
RAM includes several described cache storage units；The Tag RAM is for the storage address of storage operation number evidence and described
The status information of cache storage unit；
The controller is specifically used for according to the instruction information,
It reads Tag RAM and updates the Tag RAM according to the result queries of Tag RAM,
Or
It reads Tag RAM and is returned according to Data RAM described in the result queries of Tag RAM and by the operation data of inquiry
To processor and the Tag RAM is updated,
Or
It reads Tag RAM and is returned according to Data RAM described in the result queries of Tag RAM and by the operation data of inquiry
To processor,
Or
It reads Tag RAM and is returned according to Data RAM described in the result queries of Tag RAM and by the operation data of inquiry
External memory is write to processor and by the operation data,
Or
Tag RAM is read,
Or
It reads Tag RAM and is write according to Data RAM described in the result queries of Tag RAM and by the operation data of inquiry
External memory and the update Tag RAM；
Wherein, updating the Tag RAM includes at least one for updating operation address and the status information.
Preferably,
The controller, also particularly useful for according to the instruction information,
It, will be described when the state that the Data RAM inquires the operation data and the operation data is dirty
Operation data is output to external memory by the master interface.
Preferably,
The controller includes:
Tag Access fifo queue, for after inquiring the operation data, whether storage will to update the Tag
The information of RAM and the instruction of the access Data RAM；
Tag Write fifo queue, for after inquiring the operation data and determination need to update the Tag
When RAM, storage needs to update the operation information of the Tag RAM；
Data read fifo queue, for after inquiring the operation data, storage to need to update the Tag RAM
And read the operation information of Data RAM；
Control unit, for according to the Tag Access fifo queue, Tag Write fifo queue and Data
Read fifo queue executes the consistency operation.
Preferably,
The controller includes control unit；
Described control unit, for the collision detection that accesses, when detecting conflict access, using blocking mechanism to visit
Ask that conflict is handled.
Second aspect of the embodiment of the present invention provides a kind of data processing system, and the system comprises at least one clusters；
The cluster is listened described in 1 to 9 any one of controller and the claims including frame at least two processors, cluster
L2 Cache；Wherein, each described processor is integrally disposed a L1 Cache；
Frame listens controller in the cluster, is connected respectively with the L1 Cache and the L2 Cache, consistent for listening to
Property access, assist realization Cache mono- between wantonly one or two of L1 Cache and the L1 Cache and the L2 Cache
Cause property.
Preferably,
The system also includes frames between cluster to listen controller；
Frame listens controller between the cluster, be connected with the L2 Cache for listen to consistency access, assist realize cluster it
Between Cache consistency.
Preferably,
Institute L1 Cache is accessed specifically for inquiring the consistency in the L1 Cache when reception consistency access
Corresponding operation data；When the L1 Cache inquires the operation data, the consistency access is responded, while in institute
State caching frame in cluster listen the L1 Cache is realized under the assistance of controller where cluster Cache consistency, and between the cluster
Caching frame listens the consistency that the Cache between cluster is realized under the assistance of controller；
Caching frame listens controller in the cluster, for not inquiring the operation data in the L1 Cache described in this cluster
When, Xiang Suoshu L2 Cache sends the consistency access；
The L2 Cache accesses corresponding operation data for not inquiring consistency in the L1 Cache described in this cluster
When, the consistency access of the consistency access and the transmission of other clusters is received, inquires in the L2 Cache and whether stores
Operation data is stated, when the L2 Cache, which does not inquire the consistency, accesses corresponding operation data, by between the cluster
The operation data is inquired in other clusters other than cluster where caching frame listens controller to the L2 Cache, it is described inquiring
The consistency access is responded after operation data, and the Cache between cluster is realized under caching frame listens controller to assist between the cluster
Consistency.
The third aspect of the embodiment of the present invention provides a kind of L2 Cache consistency implementation method, which comprises
Consistency access indication signal and access are received, determines institute when receiving the consistency access indication signal
Stating access is that consistency accesses；
Classify according to consistency access indication signal and the access to the access, refers to according to classification results formation
Show information；
According to the instruction information inquiry operation data, held after inquiring the operation data according to the instruction information
Row consistency operation；When not inquiring the operation data, the consistency access is exported to peripheral hardware according to the instruction information
Indication signal and consistency access；
When the operation data is output to external memory by access needs, then the operation data is being inquired
Afterwards, the operation data is output to external memory according to the instruction information.
Preferably,
The consistency access indication signal includes consistency access type indication signal；
The reception consistency access indication signal and access, determine when receiving the consistency access indication signal
The access is that consistency accesses, comprising:
The consistency access type indication signal is received, determines the access according to the consistency type indication signal
For consistency access.
Preferably,
The L2 Cache includes Slave interface；The Slave interface includes the first read address channel, the first reading data
Channel and the first write address channel；
The consistency access indication signal further includes consistency access overall signal；
The reception consistency access indication signal and access, determine when receiving the consistency access indication signal
The access is that consistency accesses, comprising:
Consistency access overall signal is received, drives to form Slave and connect according to consistency access overall signal
Mouth control signal, drives in the Slave interface one described in each channel reception according to the Slave interface control signal
The access of cause property；
Pass through consistency access type indication signal described in the first read address channel reception；
The reception consistency access indication signal and access, determine when receiving the consistency access indication signal
It is described access be consistency access, further include it is following at least one:
Pass through consistency access type indication signal described in the first read address channel reception；
Data channel, which is read, by described first sends reading response signal to request source according to the query result；
The external memory more new signal accessed by the first write address channel reception consistency.
Preferably,
Consistency access overall signal includes inquiry of the operation data of the consistency access in other Cache
State and the request source of consistency access.
Preferably,
The L2 Cache includes Master Interface；The Master Interface includes the second read address channel, the second reading
According to channel and the second write address channel；
It is described when not inquiring the operation data, export consistency access to peripheral hardware according to the instruction information and refer to
Show signal and consistency access, comprising:
When not inquiring the operation data in the RAM by second read address channel, the consistency is exported
Access indication signal；
The method also includes:
Response signal is read by the second reading data channel reception and listens to response signal；
The operation data is write into institute in external memory and invalid Cache by the output of second write address channel
State the indication signal of operation data.
Preferably,
After receiving the consistency access indication signal, the method also includes:
Store access type, the inquiry state in other Cache, the inquiry state in L2 Cache and it is described unanimously
Property access request source, for inquire the operation data and realize that Cache consistency provides foundation information.
Preferably,
The method also includes:
When not inquiring the operation data in L2 Cache, invalid failure information is formed and stores, according to the nothing
Failure notification message is imitated to the request source.
Preferably,
The Slave interface includes controller；The RAM includes Data RAM and Tag RAM；The Data RAM
For storage operation number evidence；The Tag RAM is used to store the storage address of the operation data and the shape of cache storage unit
State information；
It is described according to the instruction information inquiry operation data, after inquiring the operation data according to the instruction believe
Breath execute consistency operation include it is following at least one:
By the controller, the result queries according to the instruction information, reading Tag RAM and according to Tag RAM are more
The new status information；
It reads Tag RAM and is returned according to Data RAM described in the result queries of Tag RAM and by the operation data of inquiry
To processor and update the status information；
It reads Tag RAM and is returned according to Data RAM described in the result queries of Tag RAM and by the operation data of inquiry
To processor；
It reads Tag RAM and is returned according to Data RAM described in the result queries of Tag RAM and by the operation data of inquiry
External memory is write to processor and by the operation data；
Read Tag RAM；And
It reads Tag RAM and is write according to Data RAM described in the result queries of Tag RAM and by the operation data of inquiry
External memory and the update status information.
Preferably,
It is described when the access needs operation data is output to external memory when, then inquiring the operation
After data, the operation data is output to external memory according to the instruction information, comprising:
According to the instruction information, the state of the operation data and the operation data is inquired in the Data RAM
When for dirty, the operation data is output to external memory by the master interface.
Preferably,
The method also includes:
It is accessed collision detection by control unit, when detecting conflict access, access is rushed using blocking mechanism
Row of advancing by leaps and bounds is handled.L2 Cache and its consistency implementation method described in the embodiment of the present invention and data processing system, pass through one
The reception of cause property access indication signal can be realized the consistency with other Cache according to consistency access indication signal；
It is able to carry out consistency access operation independently of the L2 Cache of CPU, can be realized L1 Cache and L2 in data processing system
The Cache consistency between consistency and cluster and cluster between Cache, expands the range of Cache consistency, reduces
Data processing mistake probability caused by cannot achieve in data handling procedure because of L2 Cache.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of L2 Cache described in the embodiment of the present invention；
Fig. 2 is one of the structural schematic diagram of data processing system described in the embodiment of the present invention；
Fig. 3 is the second structural representation of data processing system described in the embodiment of the present invention；
Fig. 4 is the flow diagram of L2 Cache consistency implementation method described in this law embodiment.
Specific embodiment
Technical solution of the present invention is further described in detail with reference to the accompanying drawings and specific embodiments of the specification.
Embodiment one:
As indicated with 1, a kind of secondary cache L2 Cache of the present embodiment, the L2 Cache include Slave interface
110, controller 120, Master Interface 130 and RAM 140；The RAM 140 is usually divided into Tag RAM and Data again
RAM。
The Slave interface 110, for receiving consistency access indication signal and access, when receiving the consistency
Determine that the access is that consistency accesses when accessing indication signal, according to consistency access indication signal and the access to described
Access is classified, and forms instruction information according to classification results；
The controller 120 is inquired in the RAM140 for receiving the instruction information according to the instruction information
Operation data executes consistency operation according to the instruction information after inquiring the operation data；
The Master Interface 130, when for not inquiring the operation data in the RAM 140, according to the finger
Show that information exports the consistency access indication signal and consistency access to peripheral hardware and inquiring the operation data
The operation data is output to external memory according to the instruction information afterwards.
L2 Cache described in the present embodiment is for the L1Cache being integrated on same mainboard with CPU
Independent Cache.
Slave interface described in the present embodiment 110 can also connect when receiving access relative to existing L2Cache
The consistency access indication signal is received, and indication signal is accessed according to the consistency, access is judged；By the visit
It asks and is divided into consistency access and nonuniformity access；It is usually consistent to being received while access when the Slave interface
Property access indication signal, then it is assumed that receive it is described access be consistency access.The consistency access is to need to keep Cache
Between storing data consistency access operation, data consistency between this Cache is referred to as Cache consistency.If
It is that consistency access will then generate the instruction information for corresponding to consistency access, so that the L2 Cache is according to the finger
Show that information executes the consistency operation of response, specifically such as invalid data operates.
It is described to classify according to consistency access indication signal and the access to the access, including by access type
It is divided into consistency access and nonuniformity access, operation when response accesses may include executing read operation, write operation to RAM or looking into
Operation is ask, in order to which simplified control device is to data processing, the Slave interface will also carry out again according to the specific required operation executed
Subseries, being capable of quickly access described in the more described instruction information response convenient for controller.
Preferably, the consistency access indication signal includes consistency access type indication signal；The Slave interface
110, for receiving the consistency access type indication signal, according to described in consistency access type indication signal determination
Access is that consistency accesses.
Specifically define that consistency access is accessed relative to nonuniformity in the present embodiment, Slave interface is receiving one
When the access of cause property, the consistency access type indication signal will be also received, to can confirm that current accessed for consistency visit
It asks.
Preferably,
The consistency access indication signal further includes consistency access overall signal；
The Slave interface includes the first read address channel, the first reading data channel and the first write address channel；
The Slave interface accesses global letter according to the consistency for receiving consistency access overall signal
Number driving forms Slave interface control signal, drives according to the Slave interface control signal each in the Slave interface
The access of consistency described in the channel reception；
First read address channel, for receiving the consistency access type indication signal；
Described first reads data channel, reads response signal for sending according to the query result to request source；
First write address channel, for receiving the external memory more new signal of consistency access.
Slave interface described in the present embodiment preferably comprises the interface in 5 channels；During concrete implementation, institute
Stating Slave interface will also include further includes the first reading data channel and the first write response channel other than above-mentioned 3 channels.
When the access is consistency access, the Slave interface can receive access, specific such as read access or write visit
It asks；It is for how to receive access and accessed as which channel reception access with Slave interface described in the prior art
It is consistent；In order to indicate the access as consistency access, the Slave interface will also receive the consistency access type instruction
Signal；In order to determine the information such as state of the consistency access in other Cache, the consistency access will also be described in reception
Consistency accesses overall signal；The salve interface will be taken in the synthesis access and consistency access overall signal
The information of band determines the operation that L2 Cache is needed to be implemented, and then forms instruction information.The controller will be according to the instruction
Information controls Slave interface, Master Interface and RAM and executes corresponding consistency operation.It is specific described according to the inquiry
As a result it is sent to request source and reads response signal, be increased a kind of consistency access Read response in L2 Cache.
Preferably, consistency access overall signal includes the operation data of the consistency access in other Cache
In inquiry state and the consistency access request source.
Other described Cache can be L1 Cache or other L2 Cache.The specific request source can be and L1
Cache integrally disposed CPU, AXI main equipment, AXI are from equipment such as equipment.
When storing the inquiry state in other described Cache, can inquire in this L2 Cache less than corresponding data
When, it goes other Cache to obtain data, copies to and execute corresponding operation in this L2 Cache, while being read operation according to operation
Or write operation controls other Cache and executes consistency operation, specifically such as when this L2 Cache carries out write operation, the control
Device will be according to consistency access overall signal output control information so that the data of its invalid storage inside of other Cache.
It is corresponding in order to make L2 Cache support consistency access, not only Slave interface is changed in the present embodiment
Into, while also Master Interface is improved, it is specific as follows: the Master Interface 130 include the second read address channel,
Second reads data channel and the second write address channel；
Second read address channel when for not inquiring the operation data in the RAM, exports described consistent
Property access indication signal；The consistency access indication signal specifically includes the consistency access type indication signal；
Described second reads data channel, for receiving reading response signal and listening to response signal；The reading response signal is logical
The signal exported when often returning to operation data for the downstream processing structure of L2 Cache；The downstream processing structure is specifically as external
Memory memory.
Second write address channel writes the operation data in external memory and invalid Cache for exporting
The indication signal of the operation data.The external memory can be various types of registers etc..Institute in the present embodiment
The interface that Master Interface 130 is preferably also 5 channels is stated, further includes the second write data channel and the second write response channel；It is described
Second write data channel, for exporting and receiving the relevant signal of data write operation；Second write response channel, for receiving
With output write response signal.
Preferably, the L2 Cache further include:
First buffering area, for store access type, in other Cache inquiry state, in the L2 Cache
Inquiry state and consistency access request source, for being mentioned to inquire the operation data and realization Cache consistency
For according to information.
The first buffering area can be the buffer being specially arranged；The access type includes that the type of access is to hold
Row access or nonuniformity access；Other described Cache include L1 Cache and other L2 Cache etc..Store the L2
Inquiry state in Cache facilitates other Cache when executing consistency access, keeps with the Cache's of the L2 Cache
Consistency.
The first buffering area accesses overall signal and listens in signal and obtains specifically for storage from the consistency
The above- mentioned information taken, to assist the L2 Cache to realize the consistency with other Cache.
Institute first states buffer area, is also used to store invalid failure information, according to the invalid failure notification message to described
Request source.
Preferably, the RAM includes Data RAM and Tag RAM；The Data RAM is for storage operation number according to institute
Tag RAM is stated for storing the storage address of the operation data and the status information of cache storage unit；The Data RAM
Including cache storage unit described in several；The cache storage unit is specifically as follows cache row etc., is to carry out cache
The minimum unit of read-write operation.
The controller 120 is specifically used for according to the instruction information,
It reads Tag RAM and updates the Tag RAM according to the result queries of Tag RAM,
Or
It reads Tag RAM and is returned according to Data RAM described in the result queries of Tag RAM and by the operation data of inquiry
To processor and the Tag RAM is updated,
Or
It reads Tag RAM and is returned according to Data RAM described in the result queries of Tag RAM and by the operation data of inquiry
To processor,
Or
It reads Tag RAM and is returned according to Data RAM described in the result queries of Tag RAM and by the operation data of inquiry
External memory is write to processor and by the operation data,
Or
Tag RAM is read,
Or
It reads Tag RAM and is write according to Data RAM described in the result queries of Tag RAM and by the operation data of inquiry
External memory and the update Tag RAM；
Wherein, updating the Tag RAM includes at least one for updating operation address and the status information.
The control logic of controller in existing L2 Cache is relatively easy, occurs over just and writes to Tag RAM update
When replacement caused by operation or read-write distribution, and the update of the Tag RAM is also occurred to execute one in the present embodiment
When other operations of cause property access, as operation data is inquired.Specifically such as；Writing in consistency access is being executed in other Cache
When operation, it may be necessary to the copy of the operation data in invalid this L2 Cache, it may be necessary to invalid corresponding Cache unit,
Then can the controller may execute and read Tag RAM and the result queries according to Tag RAM and update the Tag RAM's
Control logic.
Specific controller 120 responds current accessed using which kind of control logic, the operation being directed toward according to the access with
And the access carries out the information such as type and the inquiry state in other Cache to determine.
The controller can realize the increase of control logic by new control chip or logic control circuit etc..
Preferably, the controller 120, also particularly useful for according to the instruction information,
It, will be described when the state that the Data RAM inquires the operation data and the operation data is dirty
Operation data is output to external memory by the master interface.
The state of operation data is dirty, indicates that the operation data in current time Cache has had updated, but
It is the state that the operation data in external memory does not update also.
Preferably, the controller 120 includes:
Tag Access fifo queue, for after inquiring the operation data, whether storage will to update the Tag
The information of RAM and the instruction of the access Data RAM；
Tag Write fifo queue, for after inquiring the operation data and determination need to update the Tag
When RAM, storage needs to update the operation information of the Tag RAM；
Data read fifo queue, for after inquiring the operation data, storage to need to update the Tag RAM
And read the operation information of Data RAM；
Control unit, for according to the Tag Access fifo queue, Tag Write fifo queue and Data
Read fifo queue executes the consistency operation.
Fifo queue described in the present embodiment is fifo queue；Controller 120 described in the present embodiment is relative to existing
Some L2 cache have newly-increased 4 queues to assist to realize newly-increased control logic.
Preferably, the controller 120 includes control unit；
Described control unit, for the collision detection that accesses, when detecting conflict access, using blocking mechanism to visit
Ask that conflict is handled.
The specific structure of described control unit can be processing chip, be connected respectively at above-mentioned fifo, the Slave connects
Mouth, Master Interface and RAM are connected.
When the L2 cache need to realize consistency access when, it is understood that there may be different CPU same Cache is stored
Unit is written and read, this will lead to conflict, and described control unit is needed to access collision detection at this time, and using obstruction
Mechanism carries out Coordination Treatment to access conflict；The access conflict can be institute involved in the access of existing Cache consistency
Some access conflicts；The blocking mechanism can also equally use existing blocking mechanism.
In summary, it present embodiments provides a kind of L2 Cache and realizes that consistency is accessed using 5 channels, specifically
Existing L2 Cache include support AXI protocol do not support consistency access L2 Cache；This support AXI protocol
The Slave interface of L2 Cache is usually 5 channels, and L2 Cache described in the present embodiment can be in support AXI association
Improved L2 Cache on the L2 Cache of view, by the multiplexing in each channel in Slave interface and Master Interface, in the control
In device processed increase control logic (institute increased control logic can specifically using increase newly logic circuit or new control chip come reality
It is existing) so that the L2 Cache is supported consistency access.When the L2 Cache be applied to data processing system in, can be used for
L1 Cache and/or L2 Cache realize Cache consistency；And it was verified that L2 Cache described in the present embodiment with it is existing
In L1 Cache and listen to the equipment such as controller and have good compatibility.
Embodiment two:
As shown in Fig. 2, the system comprises at least one clusters the present embodiment provides a kind of data processing system；
The cluster includes at least two processors, frame listens controller and the L2 as described in embodiment one in cluster
Cache；Wherein, each described processor is integrally disposed a L1 Cache；
Frame listens controller L1 Cache Snoop Controller in the cluster, respectively with the L1 Cache and described
L2 Cache is connected, and for listening to consistency access, assists wantonly one or two of the L1 Cache and L1 Cache and institute
State realization Cache consistency between L2 Cache.
Usually when CPU initiate one access, first the CPU integrate the L1 Cache in inquire whether have it is corresponding
Operation data, when not inquiring corresponding operation data, by listening to controller in the cluster into other L1 Cache
Inquiry, when inquiring the operation data in other Cache, listens to the institute under the assistance of controller by inquiry in the cluster
It states operation data and returns to corresponding L1Cache and CPU；By listening to controller to L2 Cache in cluster if not inquiring
In inquired；The consistency operation is responded by L2 Cache.
L2 Cache described in the present embodiment supports consistency access, realizes so as to realize with the L1 Cache
Cache consistency, the problem of can be improved data access efficiency and reduce data processing inconsistency.
As shown in figure 3, the system also includes frames between cluster to listen controller；Frame listens controller between the cluster, with the L2
Cache is connected for listening to consistency access, assists to realize the Cache consistency between cluster.
When L1 Cache and L2 Cache of the corresponding operation data in a cluster is not inquired in consistency access
When corresponding data, controller is listened to go to inquire corresponding operation data, same institute to other clusters by frame between the cluster
State the consistency operation that L2 Cache and the L1 Cache listen controller to receive the transmission of other clusters also by frame between the cluster
The operation such as data query operation.
It include multiple cluster Cluster in system shown in Fig. 3；Cluster 0 and Cluster N are shown in diagram；Its
In, the N is the integer not less than 1.Each described cluster include in L1 Cache, L2 Cache and cluster caching frame listen control
Device.
Institute L1 Cache is accessed specifically for inquiring the consistency in the L1 Cache when reception consistency access
Corresponding operation data；When the L1 Cache inquires the operation data, the consistency access is responded, while in institute
State caching frame in cluster listen the L1 Cache is realized under the assistance of controller where cluster Cache consistency, and between the cluster
Caching frame listens the consistency that the Cache between cluster is realized under the assistance of controller；
Caching frame listens controller in the cluster, for not inquiring the operation data in the L1 Cache described in this cluster
When, Xiang Suoshu L2 Cache sends the consistency access；
The L2 Cache accesses corresponding operation data for not inquiring consistency in the L1 Cache described in this cluster
When, the consistency access of the consistency access and the transmission of other clusters is received, inquires in the second-level cache and whether stores
Operation data is stated, when the L2 Cache, which does not inquire the consistency, accesses corresponding operation data, by between the cluster
The operation data is inquired in other clusters other than cluster where caching frame listens controller to the L2 Cache, it is described inquiring
The consistency access is responded after operation data, and the Cache between cluster is realized under caching frame listens controller to assist between the cluster
Consistency.
After receiving consistency access (such as CPU issue consistency access), will be inquired first into L1 Cache described in
Consistency accesses corresponding operation data；Usually portion operation data will include multiple copies；In the corresponding L1 Cache of CPU
The copy of the operation data may be stored with, it is also possible to not have.When CPU inquired in its corresponding L1 Cache it is corresponding
After operation data, accessed directly in response to the consistency；If not finding in the L1Cache, L2 is needed
It goes to search in Cache；If in the L2 Cache in this cluster not if inquire into other clusters.
Specifically such as, when operation data B is stored in Cluster 0, there are two copies, are to be located at the corresponding L1 of CPU 0 respectively
In the L2 Cache of in Cache and its place cluster, when executing consistency access, inquire in the corresponding L1 Cache of CPU 0
It is stored with the operation data B, write operation is carried out to the operation data B, while caching frame listens controller in the cluster
Under assistance, L2 Cache is made to deactivate the operation data of its storage.It is specific how to be led in vain using the controller of Cache
It crosses and the status information of the storage address in Tag RAM is updated to invalid state by effective status.Thus realize in cluster
Cache consistency.The Cache consistency is that the information content for the same operation data that different Cache is stored is consistent.
When operation data B respectively stores a copy in Cluster 0 and Cluster N, specifically it is stored in
In Cluster 0 in the corresponding L1 Cache of CPU 0 and in the corresponding L1Cache of the corresponding CPU N of Cluster N.It inquires
It is stored with the operation data B in the corresponding L1 Cache of CPU 0 in Cluster 0, the operation data B is carried out writing behaviour
Make, while under the assistance that caching frame listens between controller and the cluster caching to listen to controller in the cluster, making in Cluster N
The corresponding L1Cache of CPU N deactivates the operation data of its storage.The specific controller that how can use Cache in vain
Invalid, the similar operation in the specific address as described in erasing by carrying out the storage address in Tag RAM.Thus realize cluster
Between Cache consistency.
For another example, copy there are two storing in Cluster 0 as operation data B is to be located at the corresponding L1 of CPU 0 respectively
In Cache in L1 Cache corresponding with CPU N, wherein the integer that the N is not small 1；When executing consistency access, look into
It askes in the corresponding L1 Cache of CPU 0 and is stored with the operation data B, to operation data B progress write operation, while
Caching frame is listened under the assistance of controller in the cluster, and the corresponding L1 Cache of the CPU N is made to deactivate the operand of its storage
According to.It is specific how to use the controller of Cache invalid by carrying out the storage address in Tag RAM in vain, specifically
The similar operation in the address as described in wiping.Thus realize the Cache consistency in cluster.
The same second-level cache finds operation data B at its own, when responding the write request, similarly will
It is cached between the cluster under the assistance for listening to controller, keeps the operation data B in other clusters invalid.
The copy for how triggering its invalid internal operation data of Cache in the present embodiment, may refer to the prior art
It just no longer illustrates one by one herein.
The write access includes being deleted operation data, adding new content in the operation data and to institute
State the operation that the content in operation data is replaced modification.
This implements the system described out when carrying out consistency access response, carries out query processing by level-one Cache first,
And responded according to query result, then there is second-level cache to be inquired and responded, cluster is kept in the prior art not modifying
On the basis of interior Cache consistency, the Cache consistency between cluster is realized, it is strong with the compatibility of the prior art.
When consistency access is read access, the level-one Cache, specifically for inquiring the operation data
Read operation is executed to the operation data afterwards；
When consistency access is write access, the second-level cache, specifically for inquiring the operation data
Read operation is carried out to the operation data later.
Since consistency access is read access, consistency will not be accessed corresponding operation data modify, add with
And the movement such as deletion, new operation data will not be generated, the movement without invalid operation data.
It in the present embodiment can be by can be realized L2 Cache of consistency access, caching listens to controller between cluster
It introduces, realizes the consistency of Cache between cluster and cluster in system, avoid the inconsistent caused data of data between cluster and cluster
Handle the probability of mistake.
Embodiment three:
As shown in figure 4, the present embodiment provides a kind of L2 Cache consistency implementation methods, which comprises
Step S110: receiving consistency access indication signal and access, accesses indication signal when receiving the consistency
When determine it is described access be consistency access；
Step S120: classify according to consistency access indication signal and the access to the access, according to classification
As a result instruction information is formed；
Step S130: according to the instruction information inquiry operation data, after inquiring the operation data according to described in
Indicate that information executes consistency operation；When not inquiring the operation data, according to the instruction information to described in peripheral hardware output
Consistency accesses indication signal and consistency access；
Step S140: when the operation data is output to external memory by access needs, then inquiring
After stating operation data, the operation data is output to external memory according to the instruction information.
Method described in the present embodiment is applied in L2 Cache described in embodiment one, specifically provides L2 Cache
The implementation method for such as responding consistency access has the advantages that realize easy.
Preferably,
The consistency access indication signal includes consistency access type indication signal；
The step S110 includes: to receive the consistency access type indication signal, is referred to according to the consistency type
Show that signal determines that the access is that consistency accesses.It further defines herein and how to determine that the access is that consistency accesses.
Preferably, the L2 Cache includes Slave interface；The Slave interface includes the first read address channel, first
Read data channel and the first write address channel；
The consistency access indication signal further includes consistency access overall signal；
The step S110 includes:
Consistency access overall signal is received, drives to form Slave and connect according to consistency access overall signal
Mouth control signal, drives in the Slave interface one described in each channel reception according to the Slave interface control signal
The access of cause property；
Pass through consistency access type indication signal described in the first read address channel reception；
The step S110 further include it is following at least one:
Pass through consistency access type indication signal described in the first read address channel reception；
Data channel, which is read, by described first sends reading response signal to request source according to the query result；
The external memory more new signal accessed by the first write address channel reception consistency.
The present embodiment further defines each channel in the slave is how to respond the consistency to access.Institute
The interface that Slave interface is 5 channels is stated, during concrete implementation, the Slave interface further includes the first write response channel
And first write data channel.
Preferably, consistency access overall signal includes the operation data of the consistency access in other Cache
In inquiry state and the consistency access request source.
The step S110 includes received consistency access overall signal, includes according to institute in the step S120
It states consistency access overall signal to classify, forms instruction information.
Preferably, the L2 Cache includes Master Interface；The Master Interface includes the second read address channel, the
Second reading data channel and the second write address channel；
The step S130 is specifically included: not inquiring the operation in the RAM by second read address channel
When data, the consistency access indication signal is exported；
The method also includes:
Response signal is read by the second reading data channel reception and listens to response signal；
The operation data is write into institute in external memory and invalid Cache by the output of second write address channel
State the indication signal of operation data.
The reading response signal is usually the signal from downstream processing structure；The downstream processing structure such as memory
Deng.It is described listen to response signal and listened between cluster described in embodiment two controller etc. is listened in controller or cluster.
Preferably, after receiving the consistency access indication signal in step s 110, the method also includes:
Store access type, the inquiry state in other Cache, the inquiry state in L2 Cache and it is described unanimously
Property access request source, for inquire the operation data and realize that Cache consistency provides foundation information.
The access type, in the inquiry state in other Cache, the inquiry state in L2 Cache and described consistent
Property access request source can access and the consistency access indication signal in obtain.In concrete implementation process
In, the Slave interface parsing access and the consistency access indication signal, and store the information in buffer
In, the consistency access operation is executed according to the information convenient for the controller.
Further, the method also includes:
When not inquiring the operation data in L2 Cache, invalid failure information is formed and stores, according to the nothing
Failure notification message is imitated to the request source.
The present embodiment has further specified how L2 Cache to request source feedback stores invalid failure information, in order to
The request source carries out post-treatment operations.
Preferably, the Slave interface includes controller；The RAM includes Data RAM and Tag RAM；It is described
Data RAM is used for storage operation number evidence；The Data RAM includes several described cache storage units；The Tag RAM
For storing the storage address of the operation data and the status information of the cache storage unit；
The step S130 include it is following at least one:
By the controller, the result queries according to the instruction information, reading Tag RAM and according to Tag RAM are more
The new status information reads Tag RAM and according to Data RAM described in the result queries of Tag RAM and by the operation of inquiry
Data return to processor and update the status information, read Tag RAM and according to Data described in the result queries of Tag RAM
RAM and the operation data of inquiry is returned into processor, reads Tag RAM and according to Data described in the result queries of Tag RAM
RAM and the operation data of inquiry is returned into processor and the operation data is write into external memory, reads Tag RAM,
And it reads Tag RAM and according to Data RAM described in the result queries of Tag RAM and the operation data of inquiry is write into outside deposits
Reservoir and the update status information.
The controller has increased controller newly relative to existing L2 Cache in the present embodiment, it is specific provide how institute
The control logic that L2 Cache realizes consistency access is stated, has the advantages that realize simple.
Preferably,
The step S140 includes:
According to the instruction information, the state of the operation data and the operation data is inquired in the Data RAM
When for dirty, the operation data is output to external memory by the master interface.
Specifically, the controller includes: Tag Access fifo queue, for after inquiring the operation data,
Whether storage wants the instruction of the more new information and the access Data RAM of the Tag RAM；Tag Write fifo queue is used
In after inquiring the operation data and when determination needs to update the Tag RAM, storage needs to update the Tag RAM's
Operation information；Data read fifo queue, for after inquiring the operation data, storage to need to update the Tag
RAM and the operation information for reading Data RAM；Control unit, for according to the Tag Access fifo queue, Tag
Write fifo queue and Data read fifo queue execute the consistency operation.
The control implement body is controlled the L2 Cache using the fifo of above-mentioned first in first out and realizes consistency access.
Further, the method also includes:
It is accessed collision detection by control unit, when detecting conflict access, access is rushed using blocking mechanism
Row of advancing by leaps and bounds is handled.The conflict access includes read operation and the write operation such as to same cache storage unit
The present embodiment the method is the method proposed on the basis of the L2 Cache described in example 1, Neng Goushi
The Cache consistency of existing L2 Cache and other Cache, including in cluster between Cache consistency and cluster Cache consistency.
In several embodiments provided herein, it should be understood that disclosed device and method can pass through it
Its mode is realized.Apparatus embodiments described above are merely indicative, for example, the division of the unit, only
A kind of logical function partition, there may be another division manner in actual implementation, such as: multiple units or components can combine, or
It is desirably integrated into another system, or some features can be ignored or not executed.In addition, shown or discussed each composition portion
Mutual coupling or direct-coupling or communication connection is divided to can be through some interfaces, the INDIRECT COUPLING of equipment or unit
Or communication connection, it can be electrical, mechanical or other forms.
Above-mentioned unit as illustrated by the separation member, which can be or may not be, to be physically separated, aobvious as unit
The component shown can be or may not be physical unit, it can and it is in one place, it may be distributed over multiple network lists
In member；Some or all of units can be selected to achieve the purpose of the solution of this embodiment according to the actual needs.
In addition, each functional unit in various embodiments of the present invention can be fully integrated into a processing module, it can also
To be each unit individually as a unit, can also be integrated in one unit with two or more units；It is above-mentioned
Integrated unit both can take the form of hardware realization, can also realize in the form of hardware adds SFU software functional unit.
Those of ordinary skill in the art will appreciate that: realize that all or part of the steps of above method embodiment can pass through
The relevant hardware of program instruction is completed, and program above-mentioned can be stored in a computer readable storage medium, the program
When being executed, step including the steps of the foregoing method embodiments is executed；And storage medium above-mentioned include: movable storage device, it is read-only
Memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or
The various media that can store program code such as person's CD.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (24)
1. a kind of second level independence Cache L2 Cache, which is characterized in that
The L2 Cache includes Slave interface, controller, Master Interface and RAM；
The Slave interface, for receiving consistency access indication signal and access, the access includes consistency access and non-
Consistency access determines that the access is consistency access when receiving the consistency access indication signal, and according to one
Cause property access indication signal and the access classify to the access, form instruction information according to classification results；
The controller, for receiving the instruction information, according to the instruction information in the RAM inquiry operation data,
It is inquired in the RAM and executes consistency operation according to the instruction information after the operation data；
The Master Interface, when for not inquiring the operation data in the RAM, according to the instruction information to peripheral hardware
The consistency access indication signal and consistency access are exported, and according to the finger after inquiring the operation data
Show that the operation data is output to external memory by information.
2. L2 Cache according to claim 1, which is characterized in that
The consistency access indication signal includes consistency access type indication signal；
The Slave interface refers to for receiving the consistency access type indication signal according to the consistency access type
Show that signal determines that the access is that consistency accesses.
3. L2 Cache according to claim 2, which is characterized in that
The consistency access indication signal further includes consistency access overall signal；
The Slave interface includes the first read address channel, the first reading data channel and the first write address channel；
The Slave interface, for receiving consistency access overall signal, according to consistency access, overall signal is driven
It is dynamic to form Slave interface control signal, it is driven according to the Slave interface control signal each described in the Slave interface
The access of consistency described in channel reception；
First read address channel, for receiving the consistency access type indication signal；
Described first reads data channel, reads response signal for sending according to query result to request source；
First write address channel, for receiving the external memory more new signal of consistency access.
4. L2 Cache according to claim 3, which is characterized in that
Consistency access overall signal includes inquiry state of the operation data of the consistency access in other Cache
And the request source of the consistency access.
5. L2 Cache according to claim 1, which is characterized in that
The Master Interface includes the second read address channel, the second reading data channel and the second write address channel；
Second read address channel when for not inquiring the operation data in the RAM, exports the consistency access
Indication signal；
Described second reads data channel, for receiving reading response signal and listening to response signal；
Second write address channel, for export the operation data is write it is described in external memory and invalid Cache
The indication signal of operation data.
6. L2 Cache according to claim 1, which is characterized in that
The L2 Cache further include:
First buffering area, for storing access type, in the inquiry state in other Cache, the inquiry in the L2Cache
State and the request source of consistency access, for providing foundation to inquire the operation data and realization Cache consistency
Information.
7. L2 Cache according to claim 6, which is characterized in that
The first buffering area is also used to store invalid failure information, according to request source described in the invalid failure notification message.
8. L2 Cache according to claim 1, which is characterized in that
The RAM includes Data RAM and Tag RAM；The Data RAM is used for storage operation number evidence；The Data RAM
Including several cache storage units；The Tag RAM is used for the storage address and cache storage unit of storage operation number evidence
Status information；
The controller is specifically used for according to the instruction information,
It reads Tag RAM and updates the Tag RAM according to the result queries of Tag RAM,
Or
It reads Tag RAM and returns to place according to Data RAM described in the result queries of Tag RAM and by the operation data of inquiry
It manages device and updates the Tag RAM,
Or
It reads Tag RAM and returns to place according to Data RAM described in the result queries of Tag RAM and by the operation data of inquiry
Device is managed,
Or
It reads Tag RAM and returns to place according to Data RAM described in the result queries of Tag RAM and by the operation data of inquiry
The operation data is simultaneously write external memory by reason device,
Or
Tag RAM is read,
Or
It reads Tag RAM and writes outside according to Data RAM described in the result queries of Tag RAM and by the operation data of inquiry
Memory and the update Tag RAM；
Wherein, updating the Tag RAM includes at least one for updating operation address and the status information.
9. L2 Cache according to claim 8, which is characterized in that
The controller, also particularly useful for according to the instruction information,
When the state that the Data RAM inquires the operation data and the operation data is dirty, by the operation
Data are output to external memory by the Master Interface.
10. L2 Cache according to claim 8, which is characterized in that
The controller includes:
Tag Access fifo queue, for after inquiring the operation data, whether storage will to update the Tag RAM
Information and the access Data RAM instruction；
Tag Write fifo queue, for after inquiring the operation data and determine need to update the Tag RAM when,
Storage needs to update the operation information of the Tag RAM；
Data read fifo queue, for after inquiring the operation data, storage to need to update the Tag RAM and reading
Take the operation information of Data RAM；
Control unit, for according to the Tag Access fifo queue, Tag Write fifo queue and Data read
Fifo queue executes the consistency operation.
11. L2 Cache according to claim 1, which is characterized in that
The controller includes control unit；
Described control unit, when detecting conflict access, rushes access using blocking mechanism for the collision detection that accesses
Row of advancing by leaps and bounds is handled.
12. a kind of data processing system, which is characterized in that
The system comprises at least one clusters；
The cluster listens controller and the described in any item L2 of the claims 1 to 9 including frame at least two processors, cluster
Cache；Wherein, each described processor is integrally disposed a L1 Cache；
Frame listens controller in the cluster, is connected respectively with the L1 Cache and the L2 Cache, visits for listening to consistency
It asks, assists to realize Cache consistency between wantonly one or two of L1 Cache and the L1 Cache and the L2Cache.
13. system according to claim 12, which is characterized in that
The system also includes frames between cluster to listen controller；
Frame listens controller between the cluster, is connected with the L2 Cache for listening to consistency access, assists to realize between cluster
Cache consistency.
14. system according to claim 13, which is characterized in that
Institute L1 Cache is corresponded to specifically for inquiring the consistency access in the L1 Cache when reception consistency access
Operation data；When the L1 Cache inquires the operation data, the consistency access is responded, while in the cluster
Interior caching frame is listened the L1 Cache is realized under the assistance of controller where cluster Cache consistency, and cached between the cluster
Frame listens the consistency that the Cache between cluster is realized under the assistance of controller；
Caching frame listens controller in the cluster, when for not inquiring the operation data in the L1 Cache described in this cluster,
The consistency access is sent to the L2 Cache；
When the L2 Cache accesses corresponding operation data for not inquiring consistency in the L1 Cache described in this cluster, connect
The consistency access for receiving the consistency access and the transmission of other clusters, inquires in the L2 Cache whether be stored with the operation
Data pass through caching frame between the cluster when the L2 Cache, which does not inquire the consistency, accesses corresponding operation data
The operation data is inquired in other clusters other than cluster where listening controller to the L2 Cache, is inquiring the operand
According to the rear response consistency access, and the Cache consistency between cluster is realized under caching frame listens controller to assist between the cluster.
15. a kind of L2 Cache consistency implementation method, which is characterized in that the described method includes:
Consistency access indication signal and access are received, the access includes consistency access and nonuniformity access, works as reception
Determine that the access is that consistency accesses when accessing indication signal to the consistency；
Classify according to consistency access indication signal and the access to the access, forms instruction letter according to classification results
Breath；
According to the instruction information inquiry operation data, one is executed according to the instruction information after inquiring the operation data
The operation of cause property；When not inquiring the operation data, the consistency access instruction is exported to peripheral hardware according to the instruction information
Signal and consistency access；
When the operation data is output to external memory by access needs, then after inquiring the operation data,
The operation data is output to external memory according to the instruction information.
16. according to the method for claim 15, which is characterized in that
The consistency access indication signal includes consistency access type indication signal；
The reception consistency access indication signal and access, when receiving the consistency access indication signal described in determination
Access is that consistency accesses, comprising:
The consistency access type indication signal is received, determines the access according to the consistency access type indication signal
For consistency access.
17. according to the method for claim 15, which is characterized in that
The L2 Cache includes Slave interface；The Slave interface includes the first read address channel, the first reading data channel
And the first write address channel；
The consistency access indication signal further includes consistency access overall signal；
The reception consistency access indication signal and access, when receiving the consistency access indication signal described in determination
Access is that consistency accesses, comprising:
Consistency access overall signal is received, overall signal drives to form Slave interface control according to consistency access
Signal processed drives consistency described in each channel reception in the Slave interface according to the Slave interface control signal
Access；
Pass through the first read address channel reception consistency access type indication signal；
The reception consistency access indication signal and access, when receiving the consistency access indication signal described in determination
Access be consistency access, further include it is following at least one:
Pass through consistency access type indication signal described in the first read address channel reception；
Data channel, which is read, by described first sends reading response signal to request source according to query result；
The external memory more new signal accessed by the first write address channel reception consistency.
18. according to the method for claim 17, which is characterized in that
Consistency access overall signal includes inquiry state of the operation data of the consistency access in other Cache
And the request source of the consistency access.
19. according to the method for claim 15, which is characterized in that
The L2 Cache includes Master Interface；The Master Interface is read data including the second read address channel, second and is led to
Road and the second write address channel；
It is described when not inquiring the operation data, export consistency access instruction letter to peripheral hardware according to the instruction information
Number and the consistency access, comprising:
When not inquiring the operation data in RAM by second read address channel, the consistency access instruction is exported
Signal；
The method also includes:
Response signal is read by the second reading data channel reception and listens to response signal；
The operation data is write into the behaviour in external memory and invalid Cache by the output of second write address channel
Make the indication signal of data.
20. according to the method for claim 15, which is characterized in that
After receiving the consistency access indication signal, the method also includes:
It stores access type, visited in the inquiry state in other Cache, the inquiry state in L2 Cache and the consistency
The request source asked, for providing to inquire the operation data and realization Cache consistency according to information.
21. according to the method for claim 20, which is characterized in that
The method also includes:
When not inquiring the operation data in L2 Cache, invalid failure information is formed and stores, according to the invalid mistake
It loses information and notifies the request source.
22. according to the method for claim 15, which is characterized in that
Slave interface includes controller；RAM includes Data RAM and Tag RAM；The Data RAM is used for storage operation number
According to；The Tag RAM is for storing the storage address of the operation data and the status information of cache storage unit；
It is described according to the instruction information inquiry operation data, held after inquiring the operation data according to the instruction information
Row consistency operation include it is following at least one:
By the controller, according to the instruction information, reads Tag RAM and update institute according to the result queries of Tag RAM
State status information；
It reads Tag RAM and returns to place according to Data RAM described in the result queries of Tag RAM and by the operation data of inquiry
It manages device and updates the status information；
It reads Tag RAM and returns to place according to Data RAM described in the result queries of Tag RAM and by the operation data of inquiry
Manage device；
It reads Tag RAM and returns to place according to Data RAM described in the result queries of Tag RAM and by the operation data of inquiry
The operation data is simultaneously write external memory by reason device；
Read Tag RAM；And
It reads Tag RAM and writes outside according to Data RAM described in the result queries of Tag RAM and by the operation data of inquiry
Memory and the update status information.
23. according to the method for claim 22, which is characterized in that
It is described when the access needs operation data is output to external memory when, then inquiring the operation data
Afterwards, the operation data is output to external memory according to the instruction information, comprising:
According to the instruction information, it is in the state that the Data RAM inquires the operation data and the operation data
When dirty, the operation data is output to external memory by Master Interface.
24. according to the method for claim 15, which is characterized in that
The method also includes:
Accessed collision detection by control unit, when detecting conflict access, using blocking mechanism to access conflict into
Row processing.
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| PCT/CN2015/073046 WO2016033949A1 (en) | 2014-09-04 | 2015-02-13 | L2 cache and implementation method of consistency thereof, system and storage medium |
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| CN101354682A (en) * | 2008-09-12 | 2009-01-28 | 中国科学院计算技术研究所 | Apparatus and method for settling access catalog conflict of multi-processor |
| CN101430664A (en) * | 2008-09-12 | 2009-05-13 | 中国科学院计算技术研究所 | Multiprocessor system and Cache consistency message transmission method |
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| CN101354682A (en) * | 2008-09-12 | 2009-01-28 | 中国科学院计算技术研究所 | Apparatus and method for settling access catalog conflict of multi-processor |
| CN101430664A (en) * | 2008-09-12 | 2009-05-13 | 中国科学院计算技术研究所 | Multiprocessor system and Cache consistency message transmission method |
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