CN105468540A - L2 Cache, uniformity implementation method for L2 Cache, and data processing system - Google Patents
L2 Cache, uniformity implementation method for L2 Cache, and data processing system Download PDFInfo
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Abstract
The present invention discloses an L2 Cache, a uniformity implementation method for the L2 Cache, and a data processing system. The L2 Cache comprises a Slave interface, a controller, a Master interface, and a RAM. The Slave interface is used for receiving a uniform access indication signal and accessing; when receiving the uniform access indication signal, determining the accessing is uniform accessing; classifying the accessing according to the uniform access indication signal and the accessing; and forming indication information according to a classification result. The controller is used for receiving the indication information; searching the RAM for operation data according to the indication information; and performing a uniform operation according to the indication information after finding the operation data. The Master interface is used for: when no operation data is found in the RAM, outputting a uniform access indication signal to a peripheral according to the indication information and performing uniform accessing, and after operation data is found, outputting the operation data to an external memory according to the indication information.
Description
Technical field
The present invention relates to the caching technology of data processing field, particularly relate to a kind of L2Cache and consistance implementation method thereof and data handling system.
Background technology
In the polycaryon processor of shared storage, cache memory Cache by the data buffer storage in shared storage space in this locality, can accelerate the process that multinuclear obtains data.The storage view seen due to each processor is obtained by local Cache, and therefore for the data of same memory location, different processors may get different data values.
In current multiple nucleus system, be integrated in buffer memory on same circuit board or on mainboard by with central processor CPU, be called one-level L1Cache, and with CPU independently buffer memory be called secondary L2Cache.In the prior art, the Cache consistance under the control of a processor between realization and L1Cache; But in order to improve the performances such as system processing speed, the multiple CPU in a bunch of Cluster also can share a L2Cache usually; But the existing L2Cache being separated setting with CPU does not support that consistance is accessed, this will cause L1Cache and L2Cache can not realize Cache consistance; L2Cache can not realize Cache consistance.
Obviously Cache consistance can not well be safeguarded, the problems such as the high and treatment effeciency of the process error rate that data inconsistency will be caused to cause is low.
Summary of the invention
In view of this, the embodiment of the present invention expects that providing one can receive consistance access realizes the conforming L2Cache of Cache and data handling system; The embodiment of the present invention also provides described L2Cache consistance implementation method simultaneously.
For achieving the above object, technical scheme of the present invention is achieved in that
Embodiment of the present invention first aspect provides a kind of secondary independence Cache L2Cache, and described L2Cache comprises Slave interface, controller, Master Interface and RAM;
Described Slave interface, for receiving consistance access indicator signal and access, determine that when receiving described consistance access indicator signal described access is consistance access, and according to consistance access indicator signal and described access, described access is classified, form indication information according to classification results;
Described controller, for receiving described indication information, according to described indication information query manipulation data in described RAM, performs consistency operation according to described indication information after inquiring described service data;
Described Master Interface, during for not inquiring about described service data in described RAM, export described consistance access indicator signal and the access of described consistance according to described indication information to peripheral hardware, and according to described indication information, described service data is outputted to external memory storage after inquiring described service data.
Preferably,
Described consistance access indicator signal comprises consistance access type indicator signal;
According to described consistance access type indicator signal, described Slave interface, for receiving described consistance access type indicator signal, determines that described access is consistance access.
Preferably,
Described consistance access indicator signal also comprises described consistance access overall signal;
Described Slave interface comprises first and reads address tunnel, the first read data passage and the first write address passage;
Described Slave interface, for receiving described consistance access overall signal, drive according to described consistance access overall signal and form Slave interface control signal, drive consistance access described in channel reception described in each in described Slave interface according to described Slave interface control signal;
Described first reads address tunnel, for receiving described consistance access type indicator signal;
Described first read data passage, for reading response signal according to described Query Result to request source transmission;
Described first write address passage, for receiving the external memory storage update signal of consistance access.
Preferably,
Described consistance access overall signal comprises the query State of service data in other Cache and the request source of described consistance access of the access of described consistance.
Preferably,
Described Master Interface comprises second and reads address tunnel, the second read data passage and the second write address passage;
Described second reads address tunnel, during for not inquiring about described service data in described RAM, exports described consistance access indicator signal;
Described second read data passage, reads response signal and listens for responsive signal for receiving;
Described second write address passage, writes external memory storage by described service data and the indicator signal of described service data in invalid Cache for exporting.
Preferably,
Described L2Cache also comprises:
First buffer zone, for the request source of memory access type, the query State in other Cache, the query State in described L2Cache and described consistance access, for providing according to information for inquiring about described service data and realizing Cache consistance.
Preferably,
Institute first states buffer zone, also for storing invalid failure information, according to described invalid failure notification message to described request source.
Preferably,
Described RAM comprises DataRAM and TagRAM; Described DataRAM is used for store operands certificate; Described DataRAM comprises cache storage unit described in several; Described TagRAM is used for the memory address of store operands certificate and the status information of described cache storage unit;
Described controller, specifically for according to described indication information,
Read TagRAM and also upgrade described TagRAM according to the result queries of TagRAM,
Or
Read TagRAM and according to TagRAM result queries described in DataRAM and the service data of inquiry is returned to processor and upgrades described TagRAM,
Or
Read TagRAM and according to TagRAM result queries described in DataRAM and the service data of inquiry is returned to processor,
Or
Read TagRAM and according to TagRAM result queries described in DataRAM and the service data of inquiry is returned to processor and described service data is write external memory storage,
Or
Read TagRAM,
Or
Read TagRAM and according to TagRAM result queries described in DataRAM and the service data of inquiry is write external memory storage and upgrades described TagRAM;
Wherein, upgrade described TagRAM comprise renewal rewards theory address and described status information at least one of them.
Preferably,
Described controller, also specifically for according to described indication information,
When described DataRAM inquires described service data and the state of described service data is dirty, described service data is outputted to external memory storage by described master interface.
Preferably,
Described controller comprises:
TagAccessfifo queue, for after inquiring described service data, stores and whether will upgrade the information of described TagRAM and access the instruction of described DataRAM;
TagWritefifo queue, for after inquiring described service data and when determining to need to upgrade described TagRAM, stores and needs the operation information upgrading described TagRAM;
Datareadfifo queue, for after inquiring described service data, stores and needs to upgrade described TagRAM and the operation information of reading DataRAM;
Control module, for performing described consistency operation according to described TagAccessfifo queue, TagWritefifo queue and Datareadfifo queue.
Preferably,
Described controller comprises control module;
Described control module, for the collision detection that conducts interviews, when conflict access being detected, adopts blocking mechanism to process access conflict.
Embodiment of the present invention second aspect provides a kind of data handling system, and described system comprises at least one bunch;
Described bunch comprise at least two processors, bunch in frame listen controller and the L2Cache described in any one of the claims 1 to 9; Wherein, processor described in each is integrated is provided with a L1Cache;
In described bunch, frame listens controller, is connected respectively with described L1Cache and described L2Cache, for intercepting consistance access, assisting L1Cache described in wantonly one or two and realizing Cache consistance between described L1Cache and described L2Cache.
Preferably,
Between described system also comprises bunch, frame listens controller;
Between described bunch, frame listens controller, is connected to access for intercepting consistance with described L2Cache, the Cache consistance between assisting to realize bunch.
Preferably,
Institute L1Cache, specifically for inquiring about service data corresponding to described consistance access when receiving consistance access in described L1Cache; When described L1Cache inquires described service data, respond the access of described consistance, simultaneously in described bunch, caching frame realizes the Cache consistance at described L1Cache place bunch under listening the assistance of controller, and between described bunch caching frame to realize under listening the assistance of controller bunch between the consistance of Cache;
In described bunch, caching frame listens controller, during for not inquiring described service data in L1Cache described in this bunch, sends the access of described consistance to described L2Cache;
When described L2Cache is used for the service data not inquiring consistance access correspondence in this bunch of described L1Cache, receive the consistance access of the access of described consistance and other bunches of transmissions, inquire about in described L2Cache and whether store described service data, when described L2Cache does not inquire the service data of described consistance access correspondence, listened in other bunches beyond controller to described L2Cache place bunch by caching frame between described bunch and inquire about described service data, the access of described consistance is responded after inquiring described service data, and between described bunch caching frame listen controller assist under realize bunch between Cache consistance.
The embodiment of the present invention third aspect provides a kind of L2Cache consistance implementation method, and described method comprises:
Receiving consistance access indicator signal and access, determining that when receiving described consistance access indicator signal described access is consistance access;
According to consistance access indicator signal and described access, described access is classified, form indication information according to classification results;
According to described indication information query manipulation data, after inquiring described service data, perform consistency operation according to described indication information; When not inquiring about described service data, export described consistance access indicator signal and the access of described consistance according to described indication information to peripheral hardware;
When described access needs described service data to output to external memory storage, then, after inquiring described service data, according to described indication information, described service data is outputted to external memory storage.
Preferably,
Described consistance access indicator signal comprises consistance access type indicator signal;
Described reception consistance access indicator signal and access, determining that described access is consistance access when receiving described consistance access indicator signal, comprising:
Receive described consistance access type indicator signal, determine that described access is consistance access according to described consistance type indication signal.
Preferably,
Described L2Cache comprises Slave interface; Described Slave interface comprises first and reads address tunnel, the first read data passage and the first write address passage;
Described consistance access indicator signal also comprises described consistance access overall signal;
Described reception consistance access indicator signal and access, determining that described access is consistance access when receiving described consistance access indicator signal, comprising:
Receive described consistance access overall signal, drive according to described consistance access overall signal and form Slave interface control signal, drive consistance access described in channel reception described in each in described Slave interface according to described Slave interface control signal;
Read address tunnel by described first and receive described consistance access type indicator signal;
When receiving described consistance access indicator signal, described reception consistance access indicator signal and access, determine that described access is consistance access, also comprise following at least one of them:
Read address tunnel by described first and receive described consistance access type indicator signal;
Response signal is read according to described Query Result to request source transmission by described first read data passage;
By the external memory storage update signal of described first write address channel reception consistance access.
Preferably,
Described consistance access overall signal comprises the query State of service data in other Cache and the request source of described consistance access of the access of described consistance.
Preferably,
Described L2Cache comprises Master Interface; Described Master Interface comprises second and reads address tunnel, the second read data passage and the second write address passage;
Described when not inquiring about described service data, export described consistance access indicator signal and the access of described consistance according to described indication information to peripheral hardware, comprising:
By described second read address tunnel in described RAM, do not inquire about described service data time, export described consistance access indicator signal;
Described method also comprises:
Response signal and listens for responsive signal is read by described second read data channel reception;
Exported by described second write address passage and described service data write external memory storage and the indicator signal of described service data in invalid Cache.
Preferably,
After receiving described consistance access indicator signal, described method also comprises:
The request source of memory access type, the query State in other Cache, the query State in L2Cache and described consistance access, for providing according to information for inquiring about described service data and realizing Cache consistance.
Preferably,
Described method also comprises:
When not inquiring described service data in L2Cache, formed and store invalid failure information, according to described invalid failure notification message to described request source.
Preferably,
Described Slave interface comprises controller; Described RAM comprises DataRAM and TagRAM; Described DataRAM is used for store operands certificate; Described TagRAM is for the status information of the memory address and cache storage unit that store described service data;
Described according to described indication information query manipulation data, after inquiring described service data according to described indication information perform consistency operation comprise following at least one of them:
By described controller, according to described indication information, read TagRAM and also upgrade described status information according to the result queries of TagRAM;
Read TagRAM and according to TagRAM result queries described in DataRAM and the service data of inquiry is returned to processor and upgrades described status information;
Read TagRAM and according to TagRAM result queries described in DataRAM and the service data of inquiry is returned to processor;
Read TagRAM and according to TagRAM result queries described in DataRAM and the service data of inquiry is returned to processor and described service data is write external memory storage;
Read TagRAM; And
Read TagRAM and according to TagRAM result queries described in DataRAM and the service data of inquiry is write external memory storage and upgrades described status information.
Preferably,
Described when described access needs described service data to output to external memory storage, then after inquiring described service data, according to described indication information, described service data is outputted to external memory storage, comprising:
According to described indication information, when described DataRAM inquires described service data and the state of described service data is dirty, described service data is outputted to external memory storage by described master interface.
Preferably,
Described method also comprises:
Being conducted interviews collision detection by control module, when conflict access being detected, adopting blocking mechanism to process access conflict.L2Cache described in the embodiment of the present invention and consistance implementation method thereof and data handling system, by the reception of consistance access indicator signal, can realize the consistance with other Cache according to described consistance access indicator signal; L2Cache independent of CPU can perform consistance accessing operation, can realize consistance in data handling system between L1Cache and L2Cache and bunch and bunch between Cache consistance, expand the conforming scope of Cache, reduce in data handling procedure because L2Cache cannot realize the data processing mistake probability that causes.
Accompanying drawing explanation
Fig. 1 is the structural representation of L2Cache described in the embodiment of the present invention;
One of structural representation that Fig. 2 is the data handling system described in the embodiment of the present invention;
The structural representation two that Fig. 3 is the data handling system described in the embodiment of the present invention;
Fig. 4 is the schematic flow sheet of the L2Cache consistance implementation method described in this law embodiment.
Embodiment
Below in conjunction with Figure of description and specific embodiment technical scheme of the present invention done and further elaborate.
Embodiment one:
As indicated with 1, a kind of secondary cache L2Cache of the present embodiment, described L2Cache comprises Slave interface 110, controller 120, Master Interface 130 and RAM140; Described RAM140 is divided into TagRAM and DataRAM again usually.
Described Slave interface 110, for receiving consistance access indicator signal and access, determine that when receiving described consistance access indicator signal described access is consistance access, according to consistance access indicator signal and described access, described access is classified, form indication information according to classification results;
Described controller 120, for receiving described indication information, according to described indication information query manipulation data in described RAM140, performs consistency operation according to described indication information after inquiring described service data;
Described Master Interface 130, during for not inquiring about described service data in described RAM140, exporting described consistance according to described indication information to peripheral hardware and access indicator signal and the access of described consistance and according to described indication information, described service data is outputted to external memory storage after inquiring described service data.
L2Cache described in the present embodiment is the independent Cache for the L1Cache be integrated in CPU on same mainboard.
The interface of Slave described in the present embodiment 110, when reception access, also can receive described consistance access indicator signal relative to existing L2Cache, and judges access according to described consistance access indicator signal; Consistance described access is divided into access and nonuniformity access; Usually while described Slave interface to access, receive consistance access indicator signal, then think that receiving described access is consistance access.Described consistance access is for needing the accessing operation keeping storing data consistency between Cache, and data consistency between this Cache, also can be called Cache consistance.If consistance access then will generate the indication information corresponding to the access of described consistance, so that described L2Cache performs the consistency operation of response according to described indication information, concrete as operations such as invalid datas.
Described foundation consistance access indicator signal and described access are classified to described access, comprise and be divided into consistance to access and nonuniformity access access type, operation during response access can comprise RAM execution read operation, write operation or query manipulation, in order to simplify controller to data processing, described Slave interface also carries out subseries again by according to the concrete required operation performed, and is convenient to controller and can has more described indication information fast and respond described access.
Preferably, described consistance access indicator signal comprises consistance access type indicator signal; According to described consistance access type indicator signal, described Slave interface 110, for receiving described consistance access type indicator signal, determines that described access is consistance access.
Specifically define consistance access in the present embodiment relative to nonuniformity access, Slave interface, when receiving consistance access, also will receive described consistance access type indicator signal, thus can confirm that current accessed is consistance access.
Preferably,
Described consistance access indicator signal also comprises described consistance access overall signal;
Described Slave interface comprises first and reads address tunnel, the first read data passage and the first write address passage;
Described Slave interface, for receiving described consistance access overall signal, drive according to described consistance access overall signal and form Slave interface control signal, drive consistance access described in channel reception described in each in described Slave interface according to described Slave interface control signal;
Described first reads address tunnel, for receiving described consistance access type indicator signal;
Described first read data passage, for reading response signal according to described Query Result to request source transmission;
Described first write address passage, for receiving the external memory storage update signal of consistance access.
Slave interface described in the present embodiment preferably comprises the interface of 5 passages; In concrete implementation procedure, described Slave interface also will comprise beyond above-mentioned 3 passages, also comprise the first read data passage and the first write response passage.
When described access is consistance access, described Slave interface can receive access, concrete as read access or write access etc.; For how to receive access and which channel reception to be accessed to access with the interface of Slave described in prior art be consistent by; In order to indicate this access to be consistance access, described Slave interface also will receive described consistance access type indicator signal; In order to determine the information such as the state of this consistance access in other Cache, described consistance access also will receive described consistance access overall signal; The information that described salve interface will carry in comprehensive described access and described consistance access overall signal, determines that L2Cache needs the operation performed, and then forms indication information.Described controller performs corresponding consistency operation by according to described indication information control Slave interface, Master Interface and RAM.Specifically described reads response signal according to described Query Result to request source transmission, is a kind of consistance access Readresponse increased in L2Cache.
Preferably, described consistance access overall signal comprises the query State of service data in other Cache and the request source of described consistance access of described consistance access.
Other Cache described can be L1Cache or other L2Cache.Concrete described request source can be that CPU, AXI main equipment of the integrated setting with L1Cache, AXI are from equipment such as equipment.
When storing the query State in other Cache described, when can inquire about the data less than correspondence in this L2Cache, other Cache are gone to obtain data, copy in this L2Cache and perform corresponding operation, simultaneously that read operation or write operation control other Cache and perform consistency operation according to operation, concrete as when this L2Cache carries out write operation, described controller exports control information to make the data of other Cache its storage inside invalid by according to described consistance access overall signal.
Corresponding to make L2Cache support consistance access, not only Slave interface is improved in the present embodiment, also Master Interface is improved simultaneously, specific as follows: described Master Interface 130 comprises second and reads address tunnel, the second read data passage and the second write address passage;
Described second reads address tunnel, during for not inquiring about described service data in described RAM, exports described consistance access indicator signal; Described consistance access indicator signal specifically comprises described consistance access type indicator signal;
Described second read data passage, reads response signal and listens for responsive signal for receiving; The described signal reading to export when downstream structure that response signal is generally L2Cache returns service data; Described downstream structure is concrete as external memory storage memory.
Described second write address passage, writes external memory storage by described service data and the indicator signal of described service data in invalid Cache for exporting.Described external memory storage can be various types of registers etc.Described Master Interface 130 is also preferably the interface of 5 passages in the present embodiment, also comprises the second write data channel and the second write response passage; Described second write data channel, for exporting the signal relevant with receiving data write operation; Described second write response passage, for receiving and exporting write response signal.
Preferably, described L2Cache also comprises:
First buffer zone, for the request source of memory access type, the query State in other Cache, the query State in described L2Cache and described consistance access, for providing according to information for inquiring about described service data and realizing Cache consistance.
Described first buffer zone can be the special buffer arranged; The type that described access type comprises access is an execution access or nonuniformity access; Other Cache described comprise L1Cache and other L2Cache etc.Store the query State in described L2Cache, facilitating other Cache when performing consistance access, keeping the consistance with the Cache of described L2Cache.
Described first buffer zone, specifically for storing from described consistance access overall signal and intercepting signal the above-mentioned information done and obtain, realizes the consistance with other Cache to assist described L2Cache.
Institute first states buffer zone, also for storing invalid failure information, according to described invalid failure notification message to described request source.
Preferably, described RAM comprises DataRAM and TagRAM; Described DataRAM is used for store operands according to the status information of described TagRAM for the memory address and cache storage unit that store described service data; Described DataRAM comprises cache storage unit described in several; It is capable etc. that described cache storage unit is specifically as follows cache, is the minimum unit carrying out cache read-write operation.
Described controller 120, specifically for according to described indication information,
Read TagRAM and also upgrade described TagRAM according to the result queries of TagRAM,
Or
Read TagRAM and according to TagRAM result queries described in DataRAM and the service data of inquiry is returned to processor and upgrades described TagRAM,
Or
Read TagRAM and according to TagRAM result queries described in DataRAM and the service data of inquiry is returned to processor,
Or
Read TagRAM and according to TagRAM result queries described in DataRAM and the service data of inquiry is returned to processor and described service data is write external memory storage,
Or
Read TagRAM,
Or
Read TagRAM and according to TagRAM result queries described in DataRAM and the service data of inquiry is write external memory storage and upgrades described TagRAM;
Wherein, upgrade described TagRAM comprise renewal rewards theory address and described status information at least one of them.
The steering logic of the controller in existing L2Cache is relatively simple, time TagRAM renewal is occurred over just to write operation or reads and writes the replacement distributing and cause, and when in the present embodiment other operations performing consistance access also being occurred to the renewal of described TagRAM, as service data inquiry.Concrete as; At other Cache when performing the write operation in consistance access, the copy of the service data in invalid L2Cache may be needed, the Cache unit of invalid correspondence may be needed, then can may perform and read TagRAM and the steering logic upgrading described TagRAM according to the result queries of TagRAM by described controller.
Which kind of steering logic response current accessed concrete controller 120 adopts, and the operation pointed to according to described access and this access are carried out the information such as type and the query State in other Cache and determined.
Described controller can realize the increase of steering logic by newly-increased control chip or logical control circuit etc.
Preferably, described controller 120, also specifically for according to described indication information,
When described DataRAM inquires described service data and the state of described service data is dirty, described service data is outputted to external memory storage by described master interface.
The state of service data is dirty, represents that the described service data in current time Cache have updated, but the state that the described service data in external memory storage does not also upgrade.
Preferably, described controller 120 comprises:
TagAccessfifo queue, for after inquiring described service data, stores and whether will upgrade the information of described TagRAM and access the instruction of described DataRAM;
TagWritefifo queue, for after inquiring described service data and when determining to need to upgrade described TagRAM, stores and needs the operation information upgrading described TagRAM;
Datareadfifo queue, for after inquiring described service data, stores and needs to upgrade described TagRAM and the operation information of reading DataRAM;
Control module, for performing described consistency operation according to described TagAccessfifo queue, TagWritefifo queue and Datareadfifo queue.
Fifo queue described in the present embodiment is fifo queue; Controller 120 described in the present embodiment has newly-increased 4 queues to assist to realize newly-increased steering logic relative to existing L2cache.
Preferably, described controller 120 comprises control module;
Described control module, for the collision detection that conducts interviews, when conflict access being detected, adopts blocking mechanism to process access conflict.
The concrete structure of described control module can be process chip, and, described Slave interface, Master Interface and RAM connected respectively at above-mentioned fifo are connected.
When described L2cache needs to realize consistance access, different CPU may be there is read-write operation is carried out to same Cache storage unit, this will lead to a conflict, and now need described control module to conduct interviews collision detection, and adopt blocking mechanism to carry out Coordination Treatment to access conflict; Described access conflict can be all access conflicts involved in the access of existing Cache consistance; Described blocking mechanism equally also can adopt existing blocking mechanism.
Comprehensively above-mentioned, present embodiments provide a kind of L2Cache and adopt 5 passages to realize consistance access, concrete existing L2Cache comprises the L2Cache not supporting consistance to access supporting AXI agreement; The Slave interface of the L2Cache of this support AXI agreement is generally 5 passages, L2Cache described in the present embodiment can for the L2Cache improved on the L2Cache of described support AXI agreement, multiplexing by passage each in Slave interface and Master Interface, increases steering logic (steering logic increased can specifically adopt newly-increased logical circuit or newly-increased control chip to realize) in the controller and makes described L2Cache support consistance access.When described L2Cache is applied in data handling system, may be used for L1Cache and or L2Cache realize Cache consistance; And facts have proved, the L2Cache described in the present embodiment and existing in L1Cache and intercept the equipment such as controller and have good compatibility.
Embodiment two:
As shown in Figure 2, the present embodiment provides a kind of data handling system, and described system comprises at least one bunch;
Described bunch comprise at least two processors, bunch in frame listen controller and the L2Cache as described in embodiment one; Wherein, processor described in each is integrated is provided with a L1Cache;
In described bunch, frame listens controller L1CacheSnoopController, be connected with described L1Cache and described L2Cache respectively, for intercepting consistance access, assisting L1Cache described in wantonly one or two and realizing Cache consistance between described L1Cache and described L2Cache.
Usually when CPU initiates an access, first in the integrated described L1Cache of this CPU, inquire about whether have corresponding service data, when not inquiring corresponding service data, inquire about in other L1Cache by intercepting controller in described bunch, when inquiring described service data in other Cache, intercept the assistance of controller in described bunch under, the described service data of inquiry is returned to corresponding L1Cache and CPU; If do not inquire, by bunch in intercept in controller to L2Cache and inquire about; Described consistency operation is responded by L2Cache.
L2Cache described in the present embodiment supports consistance access, thus can realize realizing Cache consistance with described L1Cache, can improve the problem of data access efficiency and reduction data processing inconsistency.
As shown in Figure 3, described system also to comprise bunch between frame listen controller; Between described bunch, frame listens controller, is connected to access for intercepting consistance with described L2Cache, the Cache consistance between assisting to realize bunch.
When in consistance access, corresponding L1Cache and L2Cache of service data in one bunch does not inquire corresponding data, listen controller to go to inquire about corresponding service data to other bunches by frame between described bunch, same described L2Cache and described L1Cache also listens controller to receive the operations such as the data query operation of the consistency operation that other bunches send by frame between described bunch.
System shown in Fig. 3 comprises multiple bunches of Cluster; Cluster0 and ClusterN is shown in diagram; Wherein, described N be not less than 1 integer.Bunch to comprise described in each L1Cache, L2Cache and bunch in caching frame listen controller.
Institute L1Cache, specifically for inquiring about service data corresponding to described consistance access when receiving consistance access in described L1Cache; When described L1Cache inquires described service data, respond the access of described consistance, simultaneously in described bunch, caching frame realizes the Cache consistance at described L1Cache place bunch under listening the assistance of controller, and between described bunch caching frame to realize under listening the assistance of controller bunch between the consistance of Cache;
In described bunch, caching frame listens controller, during for not inquiring described service data in L1Cache described in this bunch, sends the access of described consistance to described L2Cache;
When described L2Cache is used for the service data not inquiring consistance access correspondence in this bunch of described L1Cache, receive the consistance access of the access of described consistance and other bunches of transmissions, inquire about in described second-level cache and whether store described service data, when described L2Cache does not inquire the service data of described consistance access correspondence, listened in other bunches beyond controller to described L2Cache place bunch by caching frame between described bunch and inquire about described service data, the access of described consistance is responded after inquiring described service data, and between described bunch caching frame listen controller assist under realize bunch between Cache consistance.
After receiving consistance access (as the consistance access that CPU sends), first will inquire about service data corresponding to described consistance access in L1Cache; Usual a service data can comprise multiple copy; The copy of described service data may be stored in the L1Cache that CPU is corresponding, also may not have.After inquiring corresponding service data in the L1Cache of CPU in its correspondence, directly the described consistance of response is accessed; If do not find in described L1Cache, need to search in L2Cache; If in the L2Cache in this bunch not, inquire about in other bunches.
Concrete as, when service data B stores two copies in Cluster0, the L2Cache being arranged in L1Cache corresponding to CPU0 and place thereof bunch respectively, when performing consistance access, inquire in L1Cache corresponding to CPU0 and store described service data B, write operation is carried out to described service data B, under caching frame listens the assistance of controller in described bunch, makes L2Cache deactivate the service data of its storage simultaneously.It is concrete that how the invalid controller of Cache that can adopt is by being updated to disarmed state by the status information of the memory address in TagRAM by effective status.Cache consistance in so realizing bunch.Described Cache consistance is the information content of the same service data that different Cache stores is consistent.
When service data B in Cluster0 and ClusterN each store a copy time, be specifically stored in the L1Cache that in Cluster0, CPU0 is corresponding and in L1Cache that CPUN that ClusterN is corresponding is corresponding.Inquire in L1Cache corresponding to CPU0 in Cluster0 and store described service data B, write operation is carried out to described service data B, simultaneously in described bunch, caching frame is listened under between controller and described bunch, buffer memory intercepts the assistance of controller, the service data making L1Cache corresponding to CPUN in ClusterN deactivate it to store.Concrete how the invalid controller of Cache that can adopt is invalid by the memory address in TagRAM being carried out, specifically as similar in address as described in wiping etc. operation.Cache consistance between so realizing bunch.
For another example, when service data B stores two copies in Cluster0, be arranged in L1Cache corresponding to L1Cache and CPUN corresponding to CPU0 respectively, wherein, described N is the integer of not little 1; When performing consistance access, inquire in L1Cache corresponding to CPU0 and store described service data B, write operation is carried out to described service data B, under caching frame listens the assistance of controller in described bunch, makes L1Cache corresponding to described CPUN deactivate the service data of its storage simultaneously.Concrete how the invalid controller of Cache that can adopt is invalid by the memory address in TagRAM being carried out, specifically as similar in address as described in wiping etc. operation.Cache consistance in so realizing bunch.
Same described second-level cache finds service data B at himself, when responding described write request, same by under between described bunch, buffer memory intercepts the assistance of controller, makes the service data B in other bunches invalid.
How to trigger the copy of the service data of Cache its inside invalid in the present embodiment, just can illustrate no longer one by one at this see prior art.
Described write access comprises deletes service data, adds new content in described service data and carries out the content in described service data to replace the operation revised.
This implements out described system when carrying out consistance access response, first query processing is carried out by one-level Cache, and respond according to Query Result, second-level cache is had to carry out inquiring about and responding again, do not revise in prior art to keep bunch on the conforming basis of Cache, Cache consistance between achieving bunch is strong with the compatibility of prior art.
When described consistance access is for read access, described one-level Cache, specifically for performing read operation to described service data after inquiring described service data;
When described consistance access is for write access, described second-level cache, specifically for carrying out read operation to described service data after inquiring described service data.
Because consistance access is for read access, the service data corresponding to consistance access can not modifies, add and the action such as deletion, new service data can not be produced, thus without the need to the action of invalid operation data.
In the present embodiment can by can realize consistance access L2Cache, bunch between buffer memory intercept the introducing of controller, to achieve in system bunch and bunch between the consistance of Cache, to avoid bunch and bunch between the probability of the inconsistent data processing mistake caused of data.
Embodiment three:
As shown in Figure 4, the present embodiment provides a kind of L2Cache consistance implementation method, and described method comprises:
Step S110: receive consistance access indicator signal and access, determines that when receiving described consistance access indicator signal described access is consistance access;
Step S120: according to consistance access indicator signal and described access, described access is classified, form indication information according to classification results;
Step S130: according to described indication information query manipulation data, performs consistency operation according to described indication information after inquiring described service data; When not inquiring about described service data, export described consistance access indicator signal and the access of described consistance according to described indication information to peripheral hardware;
Step S140: when described access needs described service data to output to external memory storage, then, after inquiring described service data, according to described indication information, described service data is outputted to external memory storage.
Method described in the present embodiment is applied in the L2Cache described in embodiment one, specifically provides the implementation method of L2Cache as the access of response consistance, has and realize easy advantage.
Preferably,
Described consistance access indicator signal comprises consistance access type indicator signal;
Described step S110 comprises: receive described consistance access type indicator signal, determines that described access is consistance access according to described consistance type indication signal.Further define herein and how to determine that described access is consistance access.
Preferably, described L2Cache comprises Slave interface; Described Slave interface comprises first and reads address tunnel, the first read data passage and the first write address passage;
Described consistance access indicator signal also comprises described consistance access overall signal;
Described step S110 comprises:
Receive described consistance access overall signal, drive according to described consistance access overall signal and form Slave interface control signal, drive consistance access described in channel reception described in each in described Slave interface according to described Slave interface control signal;
Read address tunnel by described first and receive described consistance access type indicator signal;
Described step S110 also comprise following at least one of them:
Read address tunnel by described first and receive described consistance access type indicator signal;
Response signal is read according to described Query Result to request source transmission by described first read data passage;
By the external memory storage update signal of described first write address channel reception consistance access.
It is how to respond the access of described consistance that the present embodiment further defines each passage in described slave.Described Slave interface is the interface of 5 passages, and in concrete implementation procedure, described Slave interface also comprises the first write response passage and the first write data channel.
Preferably, described consistance access overall signal comprises the query State of service data in other Cache and the request source of described consistance access of described consistance access.
Described step S110 comprises the described consistance access overall signal of reception, and described step S120 comprises and classifying according to described consistance access overall signal, forms indication information.
Preferably, described L2Cache comprises Master Interface; Described Master Interface comprises second and reads address tunnel, the second read data passage and the second write address passage;
Described step S130 specifically comprises: by described second read address tunnel in described RAM, do not inquire about described service data time, export described consistance access indicator signal;
Described method also comprises:
Response signal and listens for responsive signal is read by described second read data channel reception;
Exported by described second write address passage and described service data write external memory storage and the indicator signal of described service data in invalid Cache.
Described response signal of reading is generally signal from downstream structure; Described downstream structure is as memory etc.Described listens for responsive signal from described in embodiment two bunch between intercept controller or bunch in intercept controller etc.
Preferably, after receiving described consistance access indicator signal in step s 110, described method also comprises:
The request source of memory access type, the query State in other Cache, the query State in L2Cache and described consistance access, for providing according to information for inquiring about described service data and realizing Cache consistance.
The request source of described access type, the query State in other Cache, the query State in L2Cache and described consistance access can access and obtain in described consistance access indicator signal.In concrete implementation procedure, described Slave interface resolves described access and described consistance access indicator signal, and is stored in buffer by described information, is convenient to described controller consistance accessing operation according to described information and executing.
Further, described method also comprises:
When not inquiring described service data in L2Cache, formed and store invalid failure information, according to described invalid failure notification message to described request source.
How the present embodiment also further provides L2Cache to the invalid failure information of request source feedback store, so that post-treatment operations is carried out in described request source.
Preferably, described Slave interface comprises controller; Described RAM comprises DataRAM and TagRAM; Described DataRAM is used for store operands certificate; Described DataRAM comprises cache storage unit described in several; Described TagRAM is for the status information of the memory address and described cache storage unit that store described service data;
Described step S130 comprise following at least one of them:
By described controller, according to described indication information, read TagRAM and also upgrade described status information according to the result queries of TagRAM, read TagRAM and according to TagRAM result queries described in DataRAM and the service data of inquiry is returned to processor and upgrades described status information, read TagRAM and according to TagRAM result queries described in DataRAM and the service data of inquiry is returned to processor, read TagRAM and according to TagRAM result queries described in DataRAM and the service data of inquiry is returned to processor and described service data is write external memory storage, read TagRAM, and read TagRAM and according to TagRAM result queries described in DataRAM and the service data of inquiry is write external memory storage and upgrades described status information.
Described controller has increased controller newly relative to existing L2Cache in the present embodiment, specifically provides the steering logic how described L2Cache realizes consistance access, has and realize simple advantage.
Preferably,
Described step S140 comprises:
According to described indication information, when described DataRAM inquires described service data and the state of described service data is dirty, described service data is outputted to external memory storage by described master interface.
Particularly, described controller comprises: TagAccessfifo queue, for after inquiring described service data, stores and whether wants the lastest imformation of described TagRAM and access the instruction of described DataRAM; TagWritefifo queue, for after inquiring described service data and when determining to need to upgrade described TagRAM, stores and needs the operation information upgrading described TagRAM; Datareadfifo queue, for after inquiring described service data, stores and needs to upgrade described TagRAM and the operation information of reading DataRAM; Control module, for performing described consistency operation according to described TagAccessfifo queue, TagWritefifo queue and Datareadfifo queue.
Described controller specifically utilizes the fifo of above-mentioned first in first out to realize consistance access to control described L2Cache.
Further, described method also comprises:
Being conducted interviews collision detection by control module, when conflict access being detected, adopting blocking mechanism to process access conflict.Described conflict access comprises as to the read operation of same cache storage unit and write operation
Method described in the present embodiment is the method proposed on the basis of the L2Cache described in embodiment one, can realize the Cache consistance of L2Cache and other Cache, in comprising bunch Cache consistance and bunch between the consistance of Cache.
In several embodiments that the application provides, should be understood that disclosed equipment and method can realize by another way.Apparatus embodiments described above is only schematic, such as, the division of described unit, be only a kind of logic function to divide, actual can have other dividing mode when realizing, and as: multiple unit or assembly can be in conjunction with, maybe can be integrated into another system, or some features can be ignored, or do not perform.In addition, the coupling each other of shown or discussed each ingredient or direct-coupling or communication connection can be by some interfaces, and the indirect coupling of equipment or unit or communication connection can be electrical, machinery or other form.
The above-mentioned unit illustrated as separating component or can may not be and physically separates, and the parts as unit display can be or may not be physical location, namely can be positioned at a place, also can be distributed in multiple network element; Part or all of unit wherein can be selected according to the actual needs to realize the object of the present embodiment scheme.
In addition, each functional unit in various embodiments of the present invention can all be integrated in a processing module, also can be each unit individually as a unit, also can two or more unit in a unit integrated; Above-mentioned integrated unit both can adopt the form of hardware to realize, and the form that hardware also can be adopted to add SFU software functional unit realizes.
One of ordinary skill in the art will appreciate that: all or part of step realizing said method embodiment can have been come by the hardware that programmed instruction is relevant, aforesaid program can be stored in a computer read/write memory medium, this program, when performing, performs the step comprising said method embodiment; And aforesaid storage medium comprises: movable storage device, ROM (read-only memory) (ROM, Read-OnlyMemory), random access memory (RAM, RandomAccessMemory), magnetic disc or CD etc. various can be program code stored medium.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.
Claims (24)
1. a secondary independence Cache L2Cache, is characterized in that,
Described L2Cache comprises Slave interface, controller, Master Interface and RAM;
Described Slave interface, for receiving consistance access indicator signal and access, determine that when receiving described consistance access indicator signal described access is consistance access, and according to consistance access indicator signal and described access, described access is classified, form indication information according to classification results;
Described controller, for receiving described indication information, according to described indication information query manipulation data in described RAM, performs consistency operation according to described indication information after inquiring described service data;
Described Master Interface, during for not inquiring about described service data in described RAM, export described consistance access indicator signal and the access of described consistance according to described indication information to peripheral hardware, and according to described indication information, described service data is outputted to external memory storage after inquiring described service data.
2. L2Cache according to claim 1, is characterized in that,
Described consistance access indicator signal comprises consistance access type indicator signal;
According to described consistance access type indicator signal, described Slave interface, for receiving described consistance access type indicator signal, determines that described access is consistance access.
3. L2Cache according to claim 2, is characterized in that,
Described consistance access indicator signal also comprises described consistance access overall signal;
Described Slave interface comprises first and reads address tunnel, the first read data passage and the first write address passage;
Described Slave interface, for receiving described consistance access overall signal, drive according to described consistance access overall signal and form Slave interface control signal, drive consistance access described in channel reception described in each in described Slave interface according to described Slave interface control signal;
Described first reads address tunnel, for receiving described consistance access type indicator signal;
Described first read data passage, for reading response signal according to described Query Result to request source transmission;
Described first write address passage, for receiving the external memory storage update signal of consistance access.
4. L2Cache according to claim 3, is characterized in that,
Described consistance access overall signal comprises the query State of service data in other Cache and the request source of described consistance access of the access of described consistance.
5. L2Cache according to claim 1, is characterized in that,
Described Master Interface comprises second and reads address tunnel, the second read data passage and the second write address passage;
Described second reads address tunnel, during for not inquiring about described service data in described RAM, exports described consistance access indicator signal;
Described second read data passage, reads response signal and listens for responsive signal for receiving;
Described second write address passage, writes external memory storage by described service data and the indicator signal of described service data in invalid Cache for exporting.
6. L2Cache according to claim 1, is characterized in that,
Described L2Cache also comprises:
First buffer zone, for the request source of memory access type, the query State in other Cache, the query State in described L2Cache and described consistance access, for providing according to information for inquiring about described service data and realizing Cache consistance.
7. L2Cache according to claim 6, is characterized in that,
Institute first states buffer zone, also for storing invalid failure information, according to described invalid failure notification message to described request source.
8. L2Cache according to claim 1, is characterized in that,
Described RAM comprises DataRAM and TagRAM; Described DataRAM is used for store operands certificate; Described DataRAM comprises cache storage unit described in several; Described TagRAM is used for the memory address of store operands certificate and the status information of described cache storage unit;
Described controller, specifically for according to described indication information,
Read TagRAM and also upgrade described TagRAM according to the result queries of TagRAM,
Or
Read TagRAM and according to TagRAM result queries described in DataRAM and the service data of inquiry is returned to processor and upgrades described TagRAM,
Or
Read TagRAM and according to TagRAM result queries described in DataRAM and the service data of inquiry is returned to processor,
Or
Read TagRAM and according to TagRAM result queries described in DataRAM and the service data of inquiry is returned to processor and described service data is write external memory storage,
Or
Read TagRAM,
Or
Read TagRAM and according to TagRAM result queries described in DataRAM and the service data of inquiry is write external memory storage and upgrades described TagRAM;
Wherein, upgrade described TagRAM comprise renewal rewards theory address and described status information at least one of them.
9. L2Cache according to claim 8, is characterized in that,
Described controller, also specifically for according to described indication information,
When described DataRAM inquires described service data and the state of described service data is dirty, described service data is outputted to external memory storage by described master interface.
10. L2Cache according to claim 8, is characterized in that,
Described controller comprises:
TagAccessfifo queue, for after inquiring described service data, stores and whether will upgrade the information of described TagRAM and access the instruction of described DataRAM;
TagWritefifo queue, for after inquiring described service data and when determining to need to upgrade described TagRAM, stores and needs the operation information upgrading described TagRAM;
Datareadfifo queue, for after inquiring described service data, stores and needs to upgrade described TagRAM and the operation information of reading DataRAM;
Control module, for performing described consistency operation according to described TagAccessfifo queue, TagWritefifo queue and Datareadfifo queue.
11. L2Cache according to claim 1, is characterized in that,
Described controller comprises control module;
Described control module, for the collision detection that conducts interviews, when conflict access being detected, adopts blocking mechanism to process access conflict.
12. 1 kinds of data handling systems, is characterized in that,
Described system comprises at least one bunch;
Described bunch comprise at least two processors, bunch in frame listen controller and the L2Cache described in any one of the claims 1 to 9; Wherein, processor described in each is integrated is provided with a L1Cache;
In described bunch, frame listens controller, is connected respectively with described L1Cache and described L2Cache, for intercepting consistance access, assisting L1Cache described in wantonly one or two and realizing Cache consistance between described L1Cache and described L2Cache.
13. systems according to claim 12, is characterized in that,
Between described system also comprises bunch, frame listens controller;
Between described bunch, frame listens controller, is connected to access for intercepting consistance with described L2Cache, the Cache consistance between assisting to realize bunch.
14. systems according to claim 13, is characterized in that,
Institute L1Cache, specifically for inquiring about service data corresponding to described consistance access when receiving consistance access in described L1Cache; When described L1Cache inquires described service data, respond the access of described consistance, simultaneously in described bunch, caching frame realizes the Cache consistance at described L1Cache place bunch under listening the assistance of controller, and between described bunch caching frame to realize under listening the assistance of controller bunch between the consistance of Cache;
In described bunch, caching frame listens controller, during for not inquiring described service data in L1Cache described in this bunch, sends the access of described consistance to described L2Cache;
When described L2Cache is used for the service data not inquiring consistance access correspondence in this bunch of described L1Cache, receive the consistance access of the access of described consistance and other bunches of transmissions, inquire about in described L2Cache and whether store described service data, when described L2Cache does not inquire the service data of described consistance access correspondence, listened in other bunches beyond controller to described L2Cache place bunch by caching frame between described bunch and inquire about described service data, the access of described consistance is responded after inquiring described service data, and between described bunch caching frame listen controller assist under realize bunch between Cache consistance.
15. 1 kinds of L2Cache consistance implementation methods, it is characterized in that, described method comprises:
Receiving consistance access indicator signal and access, determining that when receiving described consistance access indicator signal described access is consistance access;
According to consistance access indicator signal and described access, described access is classified, form indication information according to classification results;
According to described indication information query manipulation data, after inquiring described service data, perform consistency operation according to described indication information; When not inquiring about described service data, export described consistance access indicator signal and the access of described consistance according to described indication information to peripheral hardware;
When described access needs described service data to output to external memory storage, then, after inquiring described service data, according to described indication information, described service data is outputted to external memory storage.
16. methods according to claim 15, is characterized in that,
Described consistance access indicator signal comprises consistance access type indicator signal;
Described reception consistance access indicator signal and access, determining that described access is consistance access when receiving described consistance access indicator signal, comprising:
Receive described consistance access type indicator signal, determine that described access is consistance access according to described consistance type indication signal.
17. methods according to claim 15, is characterized in that,
Described L2Cache comprises Slave interface; Described Slave interface comprises first and reads address tunnel, the first read data passage and the first write address passage;
Described consistance access indicator signal also comprises described consistance access overall signal;
Described reception consistance access indicator signal and access, determining that described access is consistance access when receiving described consistance access indicator signal, comprising:
Receive described consistance access overall signal, drive according to described consistance access overall signal and form Slave interface control signal, drive consistance access described in channel reception described in each in described Slave interface according to described Slave interface control signal;
Read address tunnel by described first and receive described consistance access type indicator signal;
When receiving described consistance access indicator signal, described reception consistance access indicator signal and access, determine that described access is consistance access, also comprise following at least one of them:
Read address tunnel by described first and receive described consistance access type indicator signal;
Response signal is read according to described Query Result to request source transmission by described first read data passage;
By the external memory storage update signal of described first write address channel reception consistance access.
18. methods according to claim 17, is characterized in that,
Described consistance access overall signal comprises the query State of service data in other Cache and the request source of described consistance access of the access of described consistance.
19. methods according to claim 15, is characterized in that,
Described L2Cache comprises Master Interface; Described Master Interface comprises second and reads address tunnel, the second read data passage and the second write address passage;
Described when not inquiring about described service data, export described consistance access indicator signal and the access of described consistance according to described indication information to peripheral hardware, comprising:
By described second read address tunnel in described RAM, do not inquire about described service data time, export described consistance access indicator signal;
Described method also comprises:
Response signal and listens for responsive signal is read by described second read data channel reception;
Exported by described second write address passage and described service data write external memory storage and the indicator signal of described service data in invalid Cache.
20. methods according to claim 15, is characterized in that,
After receiving described consistance access indicator signal, described method also comprises:
The request source of memory access type, the query State in other Cache, the query State in L2Cache and described consistance access, for providing according to information for inquiring about described service data and realizing Cache consistance.
21. methods according to claim 20, is characterized in that,
Described method also comprises:
When not inquiring described service data in L2Cache, formed and store invalid failure information, according to described invalid failure notification message to described request source.
22. methods according to claim 15, is characterized in that,
Described Slave interface comprises controller; Described RAM comprises DataRAM and TagRAM; Described DataRAM is used for store operands certificate; Described TagRAM is for the status information of the memory address and cache storage unit that store described service data;
Described according to described indication information query manipulation data, after inquiring described service data according to described indication information perform consistency operation comprise following at least one of them:
By described controller, according to described indication information, read TagRAM and also upgrade described status information according to the result queries of TagRAM;
Read TagRAM and according to TagRAM result queries described in DataRAM and the service data of inquiry is returned to processor and upgrades described status information;
Read TagRAM and according to TagRAM result queries described in DataRAM and the service data of inquiry is returned to processor;
Read TagRAM and according to TagRAM result queries described in DataRAM and the service data of inquiry is returned to processor and described service data is write external memory storage;
Read TagRAM; And
Read TagRAM and according to TagRAM result queries described in DataRAM and the service data of inquiry is write external memory storage and upgrades described status information.
23. methods according to claim 22, is characterized in that,
Described when described access needs described service data to output to external memory storage, then after inquiring described service data, according to described indication information, described service data is outputted to external memory storage, comprising:
According to described indication information, when described DataRAM inquires described service data and the state of described service data is dirty, described service data is outputted to external memory storage by described master interface.
24. methods according to claim 15, is characterized in that,
Described method also comprises:
Being conducted interviews collision detection by control module, when conflict access being detected, adopting blocking mechanism to process access conflict.
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| CN101430664A (en) * | 2008-09-12 | 2009-05-13 | 中国科学院计算技术研究所 | Multiprocessor system and Cache consistency message transmission method |
| US20140164700A1 (en) * | 2012-12-10 | 2014-06-12 | Facebook, Inc. | System and method of detecting cache inconsistencies |
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| CN101354682A (en) * | 2008-09-12 | 2009-01-28 | 中国科学院计算技术研究所 | Apparatus and method for settling access catalog conflict of multi-processor |
| CN101430664A (en) * | 2008-09-12 | 2009-05-13 | 中国科学院计算技术研究所 | Multiprocessor system and Cache consistency message transmission method |
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