CN105467310A - FPGA-based relay break time test apparatus and test method - Google Patents
FPGA-based relay break time test apparatus and test method Download PDFInfo
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- CN105467310A CN105467310A CN201510960129.1A CN201510960129A CN105467310A CN 105467310 A CN105467310 A CN 105467310A CN 201510960129 A CN201510960129 A CN 201510960129A CN 105467310 A CN105467310 A CN 105467310A
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- function module
- relay
- level signal
- time
- fpga
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/327—Testing of circuit interrupters, switches or circuit-breakers
- G01R31/3277—Testing of circuit interrupters, switches or circuit-breakers of low voltage devices, e.g. domestic or industrial devices, such as motor protections, relays, rotation switches
- G01R31/3278—Testing of circuit interrupters, switches or circuit-breakers of low voltage devices, e.g. domestic or industrial devices, such as motor protections, relays, rotation switches of relays, solenoids or reed switches
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- General Physics & Mathematics (AREA)
- Testing Electric Properties And Detecting Electric Faults (AREA)
Abstract
The invention relates to an FPGA-based relay break time test apparatus and test method. The test apparatus comprises a signal input unit, an a comparison function module, a timing function module and a display function module; and the display execution unit comprises a function selection button and a timing display. The test method comprises the following steps: 1) a low level signal is provided when the relay contact of the signal input unit is open; the reverser converts the low level signal to a high level signal and sends the high level signal to the acquisition function module to time the open time and frequency of the relay; 2) a high level signal is provided when the relay contact is closed, and no acquisition is conducted; 3) the open time and frequency are sent to the comparison function module in real time to get the maximum open time; and 4) when the vibration is complete, the function selection button is pressed and the timing display performs display output.
Description
Technical field
The present invention relates to proving installation and the method for testing of a kind of relay trip time, particularly based on FPGA relay proving installation trip time and method of testing.
Background technology
In the stress screening test of product, the impact of length trip time on machine operation performance of relay is a uncertain factor.In view of FPGA (EP2C5Q208) has the strong advantage of capability of sequential control, present invention achieves a kind of trip time of testing the relay of control moment motor in vibration processes based on FPGA (EP2C5Q208), judge whether the reliability of relay under vibrating conditions meets index request, whether can be applied in the production of product.
Summary of the invention
In order to overcome the shortcoming of prior art, the invention provides a kind of proving installation based on FPGA relay trip time and method of testing.Can record product be in maximum trip time of vibration processes repeat circuit and disconnection times in real time, efficiently and accurately, simple to operate, be easy to realize.
The present invention solves the technical scheme that its technical matters takes:
Based on relay proving installation trip time of FPGA, comprise signal input unit, FPGA (field programmable gate array) test cell and display performance element; Described signal input unit comprises relay and reverser; Described FPGA test cell comprises acquisition function module, comparing function module, clocking capability module and Presentation Function module, and clocking capability module with time benchmark, can change clock frequency 50MHz ~ 200MHz; Described display performance element comprises function selection key and timing display.
A kind of relay method of testing trip time based on FPGA, comprise the following steps: 1), product is in vibration processes, relay contact in signal input unit is low level signal when disconnecting, after sending to reverser oppositely to become high level signal low level signal, the acquisition function module of giving in FPGA test cell gathers, acquisition function module starts trip time and the disconnection times of time switch according to clocking capability module, clock frequency elects 50MHz as, namely the sampling time is 20ns, disconnection times sets to 0 first, until relay contact closure terminates timing, 2), during relay contact closure be high level signal, the acquisition function module of described FPGA test cell is given after being sent to by high level signal reverser oppositely to become low level signal, now acquisition function module does not gather, gather and terminate, now recorded a trip time of relay, 3), the relay trip time collected and disconnection times are given described comparing function module by acquisition function module in real time, carry out cumulative comparison and disconnection times calculating, compare maximum trip time, to relay disconnection next time, Resurvey timing, gathers and so forth and compares, 4) when, having vibrated, press the function selection key in display performance element, function selection key sends order to comparing function module, maximum trip time and disconnection times give after Presentation Function module processes by comparing function module, and the timing display given in described display performance element carries out display translation.
The present invention has following advantages: the monitoring 1) achieving maximum time and the disconnection times disconnected the relay of product in vibration processes, with this, whether the function of product in vibration processes is normally judged whether the Realization of Product function that cuts off self-lock is met to relay and has carried out effectively proving; 2), can record product be in maximum trip time of vibration processes repeat circuit and disconnection times in real time, efficiently and accurately, simple to operate, be easy to realize.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the present invention is further described.
Fig. 1 is principle of the invention block diagram.
Embodiment
As shown in Figure 1, the present invention includes signal input unit 1, FPGA (field programmable gate array) test cell 2 and display performance element 3; Described signal input unit 1 comprises relay and reverser; Described FPGA test cell 2 comprises acquisition function module, comparing function module, clocking capability module and Presentation Function module, and clocking capability module with time benchmark, can change clock frequency 50MHz ~ 200MHz; Described display performance element 3 comprises function selection key and timing display.
The present invention includes the following step: 1), product is in vibration processes, relay contact in signal input unit 1 is low level signal when disconnecting, after sending to reverser oppositely to become high level signal low level signal, the acquisition function module of giving in FPGA test cell 2 gathers, acquisition function module starts trip time and the disconnection times of time switch according to clocking capability module, clock frequency elects 50MHz as, namely the sampling time is 20ns, disconnection times sets to 0 first, until relay contact closure terminates timing; 2), during relay contact closure be high level signal, the acquisition function module of described FPGA test cell 2 is given after being sent to by high level signal reverser oppositely to become low level signal, now acquisition function module does not gather, gather and terminate, now recorded a trip time of relay; 3), the relay trip time collected and disconnection times are given described comparing function module by acquisition function module in real time, carry out cumulative comparison and disconnection times calculating, compare maximum trip time, to relay disconnection next time, Resurvey timing, gathers and so forth and compares; 4) when, having vibrated, press the function selection key in display performance element 3, function selection key sends order to comparing function module, maximum trip time and disconnection times give after Presentation Function module processes by comparing function module, and the timing display given in described display performance element 3 carries out display translation.
Claims (2)
1. based on the proving installation of FPGA relay trip time, it is characterized in that: comprise signal input unit (1), FPGA test cell (2) and display performance element (3); Described signal input unit (1) comprises relay and reverser; Described FPGA test cell (2) comprises acquisition function module, comparing function module, clocking capability module and Presentation Function module, and clocking capability module with time benchmark, can change clock frequency 50MHz ~ 200MHz; Described display performance element (3) comprises function selection key and timing display.
2. the method for testing based on FPGA relay trip time, comprise the following steps: 1), product is in vibration processes, relay contact in signal input unit (1) is low level signal when disconnecting, after sending to reverser oppositely to become high level signal low level signal, the acquisition function module of giving in FPGA test cell (2) gathers, acquisition function module starts trip time and the disconnection times of time switch according to clocking capability module, clock frequency elects 50MHz as, namely the sampling time is 20ns, disconnection times sets to 0 first, until relay contact closure terminates timing, 2), during relay contact closure be high level signal, the acquisition function module of described FPGA test cell (2) is given after being sent to by high level signal reverser oppositely to become low level signal, now acquisition function module does not gather, gather and terminate, now recorded a trip time of relay, 3), the relay trip time collected and disconnection times are given described comparing function module by acquisition function module in real time, carry out cumulative comparison and disconnection times calculating, compare maximum trip time, to relay disconnection next time, Resurvey timing, gathers and so forth and compares, 4) when, having vibrated, press the function selection key in display performance element (3), function selection key sends order to comparing function module, maximum trip time and disconnection times give after Presentation Function module processes by comparing function module, and the timing display given in described display performance element (3) carries out display translation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510960129.1A CN105467310A (en) | 2015-12-21 | 2015-12-21 | FPGA-based relay break time test apparatus and test method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510960129.1A CN105467310A (en) | 2015-12-21 | 2015-12-21 | FPGA-based relay break time test apparatus and test method |
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| CN105467310A true CN105467310A (en) | 2016-04-06 |
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| CN201510960129.1A Pending CN105467310A (en) | 2015-12-21 | 2015-12-21 | FPGA-based relay break time test apparatus and test method |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101625395A (en) * | 2009-08-20 | 2010-01-13 | 哈尔滨工业大学 | Method for measuring relay contact settling time and device thereof |
| CN103576084A (en) * | 2013-11-19 | 2014-02-12 | 湖南工业大学 | Method and device for measuring mechanical switch contact chatter time |
| CN203643574U (en) * | 2013-11-21 | 2014-06-11 | 哈尔滨理工大学 | Tester for time parameters of miniature relay based on CPLD |
| CN203643573U (en) * | 2013-11-19 | 2014-06-11 | 湖南工业大学 | An apparatus for measuring a jitter frequency of a button switch |
| CN105068000A (en) * | 2015-08-25 | 2015-11-18 | 天津市英贝特航天科技有限公司 | Circuit and method for detection of relay actuation time |
-
2015
- 2015-12-21 CN CN201510960129.1A patent/CN105467310A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101625395A (en) * | 2009-08-20 | 2010-01-13 | 哈尔滨工业大学 | Method for measuring relay contact settling time and device thereof |
| CN103576084A (en) * | 2013-11-19 | 2014-02-12 | 湖南工业大学 | Method and device for measuring mechanical switch contact chatter time |
| CN203643573U (en) * | 2013-11-19 | 2014-06-11 | 湖南工业大学 | An apparatus for measuring a jitter frequency of a button switch |
| CN203643574U (en) * | 2013-11-21 | 2014-06-11 | 哈尔滨理工大学 | Tester for time parameters of miniature relay based on CPLD |
| CN105068000A (en) * | 2015-08-25 | 2015-11-18 | 天津市英贝特航天科技有限公司 | Circuit and method for detection of relay actuation time |
Non-Patent Citations (1)
| Title |
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| 徐广瑞: "直流电磁继电器可靠性测试系统的研究", 《中国优秀硕士学位论文全文数据库工程科技II辑》 * |
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Application publication date: 20160406 |
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