CN105450628A - UDP-based TDMA protocol control method and platform - Google Patents
UDP-based TDMA protocol control method and platform Download PDFInfo
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- CN105450628A CN105450628A CN201510650494.2A CN201510650494A CN105450628A CN 105450628 A CN105450628 A CN 105450628A CN 201510650494 A CN201510650494 A CN 201510650494A CN 105450628 A CN105450628 A CN 105450628A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
- H04L69/164—Adaptation or special uses of UDP protocol
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
- H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
- H04L69/321—Interlayer communication protocols or service data unit [SDU] definitions; Interfaces between layers
Abstract
The invention relates to a UDP-based TDMA protocol control method and platform. The method comprises the following steps: S1, implementation of an Ethernet network drive design method; S2, implementation of a port data adapter design method; S3, implementation of a design method for control data caching; S4, implementation of a business data caching design method; and S5, modulation data adapter design method. In addition, the platform includes an integrated business processing module (1), an ATO core board module (2), and a frequency conversion board module (3), wherein the three modules are combined into one. According to the method, the method can be extended; a standard communication protocol interface can be met; and the transportability is high. On the basis of combination of the method and platform, the TDMA protocol function realization way is simplified; the modularization structural design is employed; and the hardware platform can be established based on the simple structure.
Description
Technical field
The present invention relates to a kind of TDMA protocol control method based on UDP and platform, specifically under UDP message host-host protocol, realize the method that controls based on the channel access of TDMA and platform.
Background technology
Along with the develop rapidly of the Internet, the application of Ethernet is also more and more extensive, and speed is also more and more faster.At present, what nearly network most probably all adopted is ethernet technology.Meanwhile, along with continuous maturation and the progress of technology, the range of application of Ethernet is also no longer confined to local area network (LAN), and the access technology based on Ethernet have also been obtained to be applied widely.Interface between physical layer and link layer is the technology of development in Access Network field, its function is the extracting data ATM being responsible for obtaining from physical layer, IP grouping, submits to special ASIC by the high-speed interface between physical layer and link layer or network processing unit processes.Interface between physical layer and link layer is responsible for transmitting data between physical layer and link layer, usual sending direction is defined as the transfer of data of link layer to physical layer, receive direction is defined as the transfer of data of physical layer to link layer, the data packet format transmission that general support is elongated, and require that the transmit leg of data and recipient have independently flow control.The transmit leg of data provides the effective mark sending data, and data receiver provides the effective mark receiving space.
TDMA protocol integrated test system technical research based on UDP has great meaning for Ethernet access technique, along with the continuous lifting of manufacturing process, the integrated level of integrated circuit is also more and more higher, equal area can integrated more element, but this also makes to manufacture time required for a slice chip and cost also improves accordingly.These problems provide good opportunity to develop to FPGA, FPGA realizes the TDMA protocol integrated test system of UDP, and applies it in the related application of Ethernet, are have certain practical significance.
Summary of the invention
The object of this invention is to provide a kind of TDMA protocol control method based on UDP and platform, this platform realizes the control of TDMA agreement, thus make MAC software and physical layer software realize interconnecting.
In order to achieve the above object, the technical solution used in the present invention is:
A kind of TDMA protocol control method based on UDP, include the driving design method of Ethernet, the adaptive method for designing of network interface data adaptation method for designing, control data cache design method, business datum cache design method, modulating data, by step S1, S2, S3, S4 and S5 totally 5 steps complete, wherein:
The driving design method of described step S1 Ethernet, completes the interface of fpga chip and external ethernet PHY, in occupation of very important status in FPGA;
Described step S2 network interface data adaptation method for designing, for the buffer memory that realizes transceiving data between lower MAC and network interface I/O and the adaptation realized in transceiving data bit wide;
Described step S3 control data cache design method, realizes the buffer memory of control data;
Described step S4 business datum cache design method, realizes the buffer memory of business datum;
The adaptive method for designing of described step S5 modem data, for realizing the adaptation of transceiving data mutual between MAC layer and modulator-demodulator on interface shape and sequential, realizes MAC layer to the transmission of MAC end application program in the transmission of the timeslot scheduling control signal of physical layer (modulator-demodulator, radio-frequency module, antenna etc.), realizations to physical layer state optimum configurations and request signal.
Described step S1 includes step S11, S12 and S13, totally 3 steps, wherein:
Described step S11 completes transmitter function, and under gigabit speed, provide GTXCLK signal to PHY, TXD, TXEN, TXER signal therewith signal is synchronous;
Described step S12 completes receiver function, has receive clock signal RXCLK, receives data RXD, reception data effectively indicate RXDV, receives corrupt data instruction RXER;
Described step S13 completes administration configuration, comprises configuration interface clock MDC, configuration interface, carries out read-write operation to PHY chip MII register;
Described step S2 includes step S21 and S22 totally 2 steps, wherein:
Described step S21 completes and sends out data buffer storage and data bit width adaptation, utilizes FIFO to realize the transformation of data bit width from 8bit to 32bit;
Described step S22 completes and receives data buffer storage and bit wide adaptation, utilizes FIFO to realize the transformation of data bit width from 32bit to 8bit;
Described step S3 includes step S31 and S32, wherein:
Described step S31 completes uplink control data buffer memory, and buffer memory is from the control data bag treating upwards MAC submission of physical layer;
Described step S32 completes downlink control data buffer memory, resolves descending control bag, and to sent control data bag buffer memory;
Described step S4 includes step S41 and S42, wherein:
Described step S41 completes uplink business data buffer memory, and buffer memory is from the business data packet treating upwards MAC submission of physical layer;
Described step S42 completes downlink service data buffer memory, the business IP bag data that buffer memory physical layer to be committed sends;
Described step S5 includes step S51 and S52, wherein:
Described step S51 completes the transmission of MAC layer to the timeslot scheduling control signal of physical layer (MODEM, radio-frequency module, antenna etc.);
Described step S52 completes and realizes upper MAC and hold application program to the transmission of physical layer state optimum configurations and request signal.
Based on a TDMA protocol integrated test system platform of UDP, its platform comprises: Multiple Business Management module 1, ATOM core board module 2, frequency conversion template die part 3.Multiple Business Management module 1 is connected by network interface with ATOM core board module 2, constitutes the TDMA protocol integrated test system platform based on UDP with frequency conversion template die part 3.
Described Multiple Business Management module 1 is modular construction, comprises 1 fpga chip, 11,1 intermediate frequency DAC signal processor, 12,1 USB serial ports, 13,1 Ethernet interface, 14,1 FLASH15,1 JTAG mouth 16.
Described ATOM core board module 2, comprises 1 CPU21, and 1 transmitting-receiving frequency control unit 22,1 sends out power control unit 23,1 personal-machine interface board 24,1 FLASH module 25.
Described frequency conversion template die part 3, comprises 1 fpga chip 31,1 and frequently closes indicating member 32,1 ADC conversion module 33.
The present invention is based on the TDMA protocol integrated test system function of UDP, propose a kind of new method realizing protocol transmission in FPGA platform.The method meets MAC layer software to the design of physical layer software and transmission demand, achieves interconnecting between the two, the protocol function implementation of TDMA is simplified more.
The present invention can be used as a kind of new method of the TDMA protocol integrated test system based on UDP, first analyzes protocol infrastructure and requirement that whether hardware platform meets software; Then corresponding hardware resource is analyzed whether meet transmission rate and storage capacity requirement; Finally the corresponding software module of TDMA protocol integrated test system is divided according to function, make it meet the requirement of software simulating.
The invention provides the TDMA protocol integrated test system platform based on UDP, adopt Modular Structure Design, specify interface standard, set up hardware platform with simple and clear structure, stress with function and circuit module correspondence.Specifically by integrated service circuit module, the ATOM core board circuit module of integrated service software, the corresponding hardware platform of upper MAC software.This platform only needs netting twine and PC just can realize media delivery function.Simultaneously the present invention has theory novelty, simplicity of design, method are reliable, practical, and flexible operation is quick, the features such as reasonable integral structure.
Accompanying drawing explanation
Fig. 1 TDMA protocol control method of the present invention flow chart
The driving design method flow diagram of Fig. 2 Ethernet
Fig. 3 network interface data adaptation method for designing flow chart
Fig. 4 network interface data adaptation sends out data buffer storage and the adaptive method for designing flow chart of data bit width
Fig. 5 network interface data adaptation receives data buffer storage and the adaptive method for designing flow chart of data bit width
Fig. 6 control data cache design method flow chart
Fig. 7 business datum cache design method flow chart
The adaptive method for designing flow chart of Fig. 8 modem data
Fig. 9 circuit module electricity of the present invention theory diagram
Symbol description in figure:
1 is Multiple Business Management module, and 2 is ATOM core board module, and 3 is frequency conversion template die part.
11 is fpga chip, and 12 is intermediate frequency DAC signal processor, and 13 is USB serial ports, and 14 is Ethernet interface, and 15 is FLASH, and 16 is JTAG mouth.
21 is CPU, and 22 is transmitting-receiving frequency control unit, and 23 for sending out power control unit, and 24 is man-machine interface board, and 25 is FLASH module.
31 is fpga chip, and 32 for frequently closing indicating member, and 33 is ADC conversion module.
Embodiment
Referring to shown in Fig. 1 to Fig. 9, is the specific embodiment of the invention.
As can be seen from Fig. 1 to Fig. 8:
A kind of TDMA protocol control method based on UDP, include the driving design method of Ethernet, the adaptive method for designing of network interface data adaptation method for designing, control data cache design method, business datum cache design method, modulating data, by step S1, S2, S3, S4 and S5 totally 5 steps complete, wherein:
The driving design method of described step S1 Ethernet, completes the interface of fpga chip and external ethernet PHY, in occupation of very important status in FPGA;
Described step S2 network interface data adaptation method for designing, for the buffer memory that realizes transceiving data between lower MAC and network interface I/O and the adaptation realized in transceiving data bit wide;
Described step S3 control data cache design method, realizes the buffer memory of control data;
Described step S4 business datum cache design method, realizes the buffer memory of business datum;
The adaptive method for designing of described step S5 modem data, for realizing the adaptation of transceiving data mutual between MAC layer and modulator-demodulator on interface shape and sequential, realizes MAC layer to the transmission of MAC end application program in the transmission of the timeslot scheduling control signal of physical layer (modulator-demodulator, radio-frequency module, antenna etc.), realizations to physical layer state optimum configurations and request signal.
Described step S1 includes step S11, S12 and S13, totally 3 steps, wherein:
Described step S11 completes Ethernet transmitter function, and under gigabit speed, provide GTXCLK signal to PHY, TXD, TXEN, TXER signal therewith signal is synchronous;
Described step S12 completes ethernet receiver function, has receive clock signal RXCLK, receives data RXD, reception data effectively indicate RXDV, receives corrupt data instruction RXER;
Described step S13 completes ethernet management configuration, comprises configuration interface clock MDC, configuration interface, carries out read-write operation to PHY chip MII register.
Described step S2 includes step S21 and S22 totally 2 steps, wherein:
Described step S21 completes and sends out data buffer storage and data bit width adaptation.
Described step S21, contains S211, S212, S213 totally 3 steps in steps, wherein:
Described step S211 completes and adds MAC header data;
Described step S212 completes TXIP bag buffer memory, utilizes FIFO to realize the buffer memory wrapped TXIP;
Described step S213 completes the transformation of bit wide, utilizes FIFO to realize the transformation of data bit width from 32bit to 8bit.
Described step S22 completes and receives data buffer storage and bit wide adaptation.
Described step S22, contains S221, S222, S223, S224 totally 4 steps in steps, wherein:
Described step S221 completes and abandons illegal (non-local MAC Address) MAC bag.
Described step S222 abandons MAC header data.
Described step S223 completes RXMAC bag buffer memory, utilizes FIFO to realize the buffer memory wrapped RXMAC.
Described step S224 completes the transformation of bit wide, namely utilizes FIFO to realize the transformation of data bit width from 8bit to 32bit.
Described step S3 includes step S31 and S32, wherein:
Described step S31 completes uplink control data buffer memory, and buffer memory is from the control data bag treating upwards MAC submission of physical layer.
Described step S32 completes downlink control data buffer memory, resolves descending control bag, and to sent control data bag buffer memory.
Described step S4 includes step S41 and S42, wherein:
Described step S41 completes uplink business data buffer memory, and buffer memory is from the business data packet treating upwards MAC submission of physical layer.
Described step S42 completes downlink service data buffer memory, the business IP bag data that buffer memory physical layer to be committed sends.
Described step S5 includes step S51 and S52, wherein:
Described step S51 completes the transmission of MAC layer to the timeslot scheduling control signal of physical layer (MODEM, radio-frequency module, antenna etc.).
Described step S52 completes and realizes upper MAC and hold application program to the transmission of physical layer state optimum configurations and request signal.In the present embodiment, physical layer state optimum configurations comprises the parameters such as modulation system, coded system, symbol numbers, and the signal of inquiry comprises the parameters such as demodulation mode, decoding process, demodulation symbol number.
As can be seen from Figure 9:
Based on a TDMA protocol integrated test system platform of UDP, its platform comprises: Multiple Business Management module 1, ATOM core board module 2, frequency conversion template die part 3.Multiple Business Management module 1 is connected by network interface with ATOM core board module 2, constitutes an entirety with frequency conversion template die part 3, defines the TDMA protocol integrated test system platform based on UDP.Wherein:
Described Multiple Business Management module 1 is modular construction, comprises 1 fpga chip, 11,1 intermediate frequency DAC signal processor, 12,1 USB serial ports, 13,1 Ethernet interface, 14, FLASH15,1 JTAG mouth 16; Intermediate frequency DAC signal processor 12, USB serial ports 13, Ethernet interface 14, FLASH15, JTAG mouth 16 carries out the mutual of control information and data respectively by pin A2, A3, A4, A5, A6 and fpga chip 11.The A7 pin of fpga chip 11 is connected with the B4 pin of the CPU of ATOM plate and carries out exchanging of control information.The B3 of FIFO and the ATOM plate of fpga chip 11 is connected and carries out data interaction.
Described ATOM core board module 2 comprises 1 CPU21, and 1 transmitting-receiving frequency control unit 22,1 sends out power control unit 23,1 personal-machine interface board 24,1 FLASH module 25; Transmitting-receiving frequency control unit 22, sends out power control unit 23 and carries out the mutual of control signal and data-signal by pin B7, B6 and cpu chip 21; Man-machine interface board 24, FLASH module 25 carries out data interaction by B1, B2 and CPU21.
Described frequency conversion template die part 3 comprises 1 fpga chip 31,1 is closed indicating member 32,1 ADC conversion module 33 frequently, frequently closes indicating member 32 and is connected with the C1 pin of the integrated circuit 31 of frequency conversion, be connected with the B5 pin of ATOM core board CPU21, realize exchange and the transmission of information; ADC conversion module 33 is undertaken mutual by C2 pin and fpga chip 11; Frequency conversion template die part 3 receives the intermediate-freuqncy signal from external radio frequency unit, and emission medium-frequency signal is to external radio frequency unit.
What deserves to be explained is that the main components model that the present invention selects is followed successively by: the fpga chip (Xilinxxc6vlx240t) on Multiple Business Management module 1, Ethernet driving chip (88e1111), ADC chip (AD9248BSTZ-65); CPU on ATOM core board 2 adopts Inter atom series 1.6GHZAtomZ530, and chipset adopts InterPoulsbo (US15W) SCHchipset; Fpga chip (Xilinxxc3S250E144QFP) on frequency conversion template die part 3, all the other are technical grade components and parts and fine finishining self-made components.
Above embodiment, is only preferred embodiment of the present invention, in order to technical characteristic of the present invention and exploitativeness to be described, and to be not used to limit and of the present inventionly to apply for a patent right; Simultaneously above description, should understand implemented for knowing those skilled in the art, and therefore, other changes or modify not departing from the equivalence completed under disclosed prerequisite, all should be included within described claim.
Claims (9)
1. the TDMA protocol control method based on UDP, include the driving design method of Ethernet, the adaptive method for designing of network interface data adaptation method for designing, control data cache design method, business datum cache design method, modulating data, by step S1, S2, S3, S4 and S5 totally 5 steps complete, it is characterized in that:
The driving design method of described step S1 Ethernet, completes the interface of FPGA and external ethernet PHY, in occupation of very important status in FPGA;
Described step S2 network interface data adaptation method for designing, for the buffer memory that realizes transceiving data between lower MAC and network interface I/O and the adaptation realized in transceiving data bit wide;
Described step S3 control data cache design method, realizes the buffer memory of control data;
Described step S4 business datum cache design method, realizes the buffer memory of business datum;
The adaptive method for designing of described step S5 modem data, for realizing the adaptation of transceiving data mutual between MAC layer and modulator-demodulator on interface shape and sequential, realizes MAC layer to the transmission of MAC end application program in the transmission of the timeslot scheduling control signal of physical layer (modulator-demodulator, radio-frequency module, antenna etc.), realizations to physical layer state optimum configurations and request signal.
2., as claimed in claim 1 based on the TDMA protocol control method of UDP, it is characterized in that:
Described step S1 includes step S11, S12 and S13, totally 3 steps, wherein:
Described step S11 completes transmitter function, and under gigabit speed, provide GTXCLK signal to PHY, TXD, TXEN, TXER signal therewith signal is synchronous;
Described step S12 completes receiver function, has receive clock signal RXCLK, receives data RXD, reception data effectively indicate RXDV, receives corrupt data instruction RXER;
Described step S13 completes administration configuration, comprises configuration interface clock MDC, configuration interface, carries out read-write operation to PHY chip MII register.
3., as claimed in claim 1 based on the TDMA protocol control method of UDP, it is characterized in that:
Described step S2 includes step S21 and S22 totally 2 steps, wherein:
Described step S21 completes and sends out data buffer storage and data bit width adaptation, it includes again S211, S212, S213 totally 3 steps, FIFO is utilized to realize the transformation of data bit width from 8bit to 32bit, S211 completes and adds MAC header data, S212 completes TXIP bag buffer memory, utilize FIFO to realize the buffer memory wrapped TXIP, S213 completes the transformation of bit wide, utilizes FIFO to realize the transformation of data bit width from 32bit to 8bit;
Described step S22 completes and receives data buffer storage and bit wide adaptation, it includes again S221, S222, S223 totally 3 steps, FIFO is utilized to realize the transformation of data bit width from 32bit to 8bit, S221 completes and abandons illegal (non-local MAC Address) MAC bag, step S222 abandons MAC header data, step S223 completes RXMAC bag buffer memory, FIFO is utilized to realize the buffer memory wrapped RXMAC, step S224 completes the transformation of bit wide, namely utilizes FIFO to realize the transformation of data bit width from 8bit to 32bit.
4., as claimed in claim 1 based on the TDMA protocol control method of UDP, it is characterized in that:
Described step S3 includes step S31 and S32, wherein:
Described step S31 completes uplink control data buffer memory, and buffer memory is from the control data bag treating upwards MAC submission of physical layer;
Described step S32 completes downlink control data buffer memory, resolves descending control bag, and to sent control data bag buffer memory.
5., as claimed in claim 1 based on the TDMA protocol control method of UDP, it is characterized in that:
Described step S4 includes step S41 and S42, wherein:
Described step S41 completes uplink business data buffer memory, and buffer memory is from the business data packet treating upwards MAC submission of physical layer;
Described step S42 completes downlink service data buffer memory, the business IP bag data that buffer memory physical layer to be committed sends.
6., as claimed in claim 1 based on the TDMA protocol control method of UDP, it is characterized in that:
Described step S5 includes step S51 and S52, wherein:
Described step S51 completes the transmission of MAC layer to the timeslot scheduling control signal of physical layer (MODEM, radio-frequency module, antenna etc.);
Described step S52 completes and realizes upper MAC and hold application program to the transmission of physical layer state optimum configurations and request signal.
7. the TDMA protocol integrated test system platform based on UDP, its platform comprises: Multiple Business Management module (1), ATOM core board module (2), frequency conversion template die part (3) totally 3 parts combine formation entirety, it is characterized in that:
Described Multiple Business Management module (1) is modular construction, comprise 1 fpga chip (11), 1 intermediate frequency DAC signal processor (12), 1 USB serial ports (13), 1 Ethernet interface (14), a FLASH (15), 1 JTAG mouth (16); Intermediate frequency DAC signal processor (12), USB serial ports (13), Ethernet interface (14), FLASH (15), JTAG mouth (16) carries out the mutual of control information and data respectively by pin A2, A3, A4, A5, A6 and fpga chip 11; The A7 pin of fpga chip 11 is connected with the B4 pin of the CPU of ATOM plate and carries out exchanging of control information; The B3 of FIFO and the ATOM plate of fpga chip 11 is connected and carries out data interaction.
8. a kind of TDMA protocol integrated test system platform based on UDP as claimed in claim 7, is characterized in that:
Described ATOM core board module (2) comprises 1 CPU (21), 1 transmitting-receiving frequency control unit (22), send out power control unit (23), 1 personal-machine interface board (24), 1 FLASH module (25) for 1; Transmitting-receiving frequency control unit (22), sends out power control unit (23) and carries out the mutual of control signal and data-signal by pin B7, B6 and cpu chip (21); Man-machine interface board (24), FLASH module (25) carry out data interaction by B1, B2 and CPU (21).
9. a kind of TDMA protocol integrated test system platform based on UDP as claimed in claim 7, is characterized in that:
Described frequency conversion template die part 3 comprises 1 frequency conversion integrated circuit (31), 1 frequency closes indicating member (32), 1 ADC conversion module (33), frequently close indicating member (32) to be connected with the C1 pin of the integrated circuit (31) of frequency conversion, be connected with the B5 pin of ATOM core board CPU (21), realize exchange and the transmission of information; ADC conversion module (33) is undertaken mutual by C2 pin and fpga chip (11); Frequency conversion template die part 3 receives the intermediate-freuqncy signal from external radio frequency unit, and emission medium-frequency signal is to external radio frequency unit.
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| CN205051727U (en) * | 2015-10-09 | 2016-02-24 | 武汉中元通信股份有限公司 | TDMA agrees control platform based on UDP |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103001827A (en) * | 2012-11-30 | 2013-03-27 | 无锡众志和达存储技术股份有限公司 | Method for Ethernet package detection based on 10Gb network card and field programmable gate array (FPGA) hardware check |
| CN103036685A (en) * | 2013-01-23 | 2013-04-10 | 南京航空航天大学 | DP83849C-based AFDX interface converter |
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Application publication date: 20160330 |