CN105450009A - Voltage converter fault processing method and voltage converter - Google Patents

Abstract

The present application provides a fault handling method for a voltage converter and the voltage converter. The voltage converter includes a control circuit and N phases. The control circuit controls the N switches in the N phases to output N electrical pulses in the first cycle, the first cycle is composed of N consecutive sub-cycles, and each sub-cycle in the N consecutive sub-cycles The duration is T ₁ /N, and the N start times of the N electric pulses are respectively the N start times of the N consecutive sub-periods. The control circuit determines a first phase failure. Further, the control circuit controls N-1 switches of N-1 phases of the N phases except the first phase, and outputs N-1 electric pulses in the second period. The second cycle is composed of N-1 consecutive sub-cycles, the duration of each sub-cycle in the N-1 consecutive sub-cycles is T ₂ /(N-1), and the N-1 electric The N-1 start times of the pulse are respectively the N-1 start times of the N-1 consecutive sub-periods.

Description

Troubleshooting method of voltage converter and voltage converter

technical field

The invention relates to the field of circuits, in particular to a voltage converter fault handling method and a voltage converter.

Background technique

A voltage converter (English: voltage converter) is a device capable of voltage conversion. A voltage converter can supply power to the load. The voltage converter may include multiple phases (English: phase), and the multiple phases all supply power to the load. When one phase of the voltage converter fails, the entire voltage converter cannot function properly.

Contents of the invention

Embodiments of the present application provide a voltage converter fault handling method and the voltage converter, which can handle the fault when a phase of the voltage converter fails.

The technical scheme provided by the embodiments of the present application is as follows:

In a first aspect, a voltage converter fault handling method is provided, the voltage converter includes a control circuit and N phases, the N phases include N switches, and the N phases are identical to the N switches One-to-one correspondence, N is an integer greater than 2,

The methods include:

The control circuit controls the N switches to output N electric pulses in the first cycle. The N switches correspond to the N electrical pulses one by one, the duration of the first cycle is T ₁ , the first cycle is composed of N consecutive sub-cycles, and the N consecutive sub-cycles The duration of each sub-period is T ₁ /N, and the N starting times of the N electrical pulses are respectively the N starting times of the N consecutive sub-periods.

After the control circuit controls the N switches to output the N electrical pulses in the first cycle, the control circuit determines that the first phase is faulty. The first phase is one of the N phases, the first phase includes a first switch, and the first switch is one of the N switches.

After the control circuit determines that the first phase is faulty, the control circuit controls N-1 switches among the N switches to output N-1 electrical pulses in the second cycle. The N-1 switches are in one-to-one correspondence with the N-1 electrical pulses, the N-1 switches do not include the first switch, the duration of the second cycle is T ₂ , and the first The second cycle consists of N-1 consecutive sub-cycles, the duration of each sub-cycle in the N-1 consecutive sub-cycles is T ₂ /(N-1), and the N of the N-1 electric pulses The -1 start times are respectively the N-1 start times of the N-1 consecutive sub-periods.

Through the above solution, after the control circuit determines that one of the N phases of the voltage converter is faulty, it sets the start time of the switches in the N-1 phases that can work normally among the N phases to output electric pulses, so that all The voltage converter described above can output a stable voltage. Therefore, the above technical solution can handle the fault of the voltage converter, so that the voltage converter can work normally.

Optionally, in an example, the control circuit determining the first phase fault includes: the control circuit determining the value of the average current of the first phase; the control circuit obtaining the N phases of the N phases The values of the average currents, the N phases correspond to the N average currents one by one; when the value of the average current of the first phase is the same as the value of the N average currents of the N phases When the difference between the average values exceeds a first value, the control circuit determines that the first phase is faulty.

By regularly measuring the value of the average current of each phase and determining whether the value of the average current of each phase is within a preset range, the control circuit can automatically determine the value of the first phase without affecting the operation of the system. Fault.

Optionally, in another example, the control circuit determines that the first phase fault includes: the control circuit detects that the voltage converter is abnormal; the control circuit disconnects all the first phase; the control circuit determines that when the first phase is in the off state and N-1 phases are in the on state, the abnormality disappears, and the N-1 phases are the Phases other than the first phase among the N phases; the control circuit determines that the first phase is faulty based on the disappearance of the abnormality.

Optionally, after the control circuit determines that the first phase is faulty, the method further includes: the control circuit disconnects the first phase.

Optionally, in an example, after the control circuit determines that the first phase is faulty, and the control circuit controls N-1 switches among the N switches to output the Before the N-1 electric pulses, the method further includes: the control circuit disconnects the N phases; and the control circuit saves the identification of the first phase. The control circuit controls N-1 switches among the N switches to output the N-1 electric pulses in the second period, specifically including: the control circuit according to the identification of the first phase, determining N-1 switches among the N switches; and the control circuit controls the N-1 switches determined according to the identification of the first phase to output the N-1 switches in the second cycle an electric pulse.

Optionally, in another example, after the control circuit determines that the first phase is faulty, and the control circuit controls N-1 switches among the N switches to output Before the N-1 electric pulses, the method further includes: the control circuit disconnects the N phases; and the control circuit saves the identification of the N-1 phases, and the N-1 phases are Among the N phases, the N-1 phases do not include the first phase. The control circuit controls N-1 switches among the N switches to output the N-1 electrical pulses in the second cycle, specifically including: the control circuit according to the N-1 phases identification, determining N-1 switches among the N switches; and the control circuit controls the N-1 switches determined according to the identification of the N-1 phases to output N-1 in the second cycle an electric pulse.

By storing the identification of the first phase, or storing the identification of the N-1 phases, the control circuit directly starts the N-1 phases when the N switches are turned off and the switches are restarted, enable the voltage converter to work properly.

In a second aspect, a voltage converter is provided, the voltage converter includes a control unit, a detection unit and N phases, the N phases include N switches, and the N phases are identical to the N switches One-to-one correspondence, N is an integer greater than 2.

The control unit is configured to control the N switches to output N electric pulses in a first cycle, the N switches correspond to the N electric pulses one by one, and the duration of the first cycle is T1 , the first cycle is composed of N consecutive sub-cycles, the duration of each sub-cycle in the N consecutive sub-cycles is T ₁ /N, and the N starting times of the N electric pulses are respectively N start times of the N consecutive sub-periods.

The detection unit is configured to determine that the first phase is faulty after the control unit controls the N switches to output the N electrical pulses in the first cycle, and the first phase is the N One of the phases, the first phase includes a first switch, and the first switch is one of the N switches.

The control unit is further configured to control N-1 switches among the N switches to output N-1 electrical pulses in a second cycle after the detection unit determines that the first phase is faulty, the The N-1 switches correspond to the N-1 electrical pulses one by one, the N-1 switches do not include the first switch, the duration of the second cycle is T ₂ , and the second cycle It consists of N-1 consecutive sub-cycles, the duration of each sub-cycle in the N-1 consecutive sub-cycles is T ₂ /(N-1), and the N-1 of the N-1 electric pulses The start times are respectively the N-1 start times of the N-1 consecutive sub-periods.

This solution has the same technical effect as the solution in the first aspect.

Optionally, in an example, the detection unit is specifically configured to: determine the value of the average current of the first phase; obtain the values of N average currents of the N phases, and the N phases and The values of the N average currents correspond one-to-one; when the difference between the average current value of the first phase and the average value of the N average current values of the N phases exceeds the first value , to determine the first phase fault.

Optionally, in another example, the detection unit is specifically configured to: detect that the voltage converter is abnormal; disconnect the first phase according to the detection result; determine when the first phase The abnormality disappears when it is in an off state and N-1 phases are in an on state, and the N-1 phases are phases other than the first phase among the N phases; and Based on the disappearance of the abnormality, it is determined that the first phase is faulty.

Optionally, after the detection unit determines that the first phase is faulty, the control unit is further configured to: disconnect the first phase.

Optionally, in an example, after the detection unit determines that the first phase is faulty, and controls N-1 switches among the N switches to output the N-1 switches in the second cycle. Before the electrical pulses, it is also used to: disconnect the N phases; and save the identification of the first phase. The control unit controls N-1 switches in the N switches to output the N-1 electrical pulses in the second cycle, which specifically includes: determining the N N-1 switches among the switches; and controlling the N-1 switches determined according to the identification of the first phase to output the N-1 electrical pulses in the second cycle.

Optionally, in another example, the control unit controls N-1 switches among the N switches in the second period after the detection unit determines that the first phase is faulty. Before outputting the N-1 electric pulses, it is also used to: disconnect the N phases; and save the identification of the N-1 phases, the N-1 phases are phases of the N phases, The N-1 phases do not include the first phase. The control unit controls N-1 switches among the N switches to output the N-1 electric pulses in the second cycle, which specifically includes: determining the N-1 switches among the N switches; and controlling the N-1 switches determined according to the identification of the N-1 phases to output N-1 electrical pulses in the second cycle.

In a third aspect, a voltage converter is provided, the voltage converter includes a processor, a memory, and N phases, the processor is coupled to the memory, the processor is coupled to the N phases, the The N phases include N switches, the N phases correspond to the N switches one by one, and N is an integer greater than 2.

The memory is used to store computer programs. The processor is configured to perform the following operations by accessing the computer program:

Controlling the N switches to output N electrical pulses in the first period, the N switches correspond to the N electrical pulses one by one, the duration of the first period is T1, and the first period is determined by It consists of N consecutive sub-cycles, the duration of each sub-cycle in the N consecutive sub-cycles is T ₁ /N, and the N starting times of the N electric pulses are respectively the duration of the N consecutive sub-cycles. N start times of the cycle;

After the N switches output the N electrical pulses in the first period, it is determined that the first phase is faulty, the first phase is one of the N phases, and the first phase includes a first switch, the first switch being one of the N switches; and

After determining the first phase fault, controlling N-1 switches among the N switches to output N-1 electrical pulses in the second cycle, the N-1 switches and the N-1 electrical pulses One-to-one pulse correspondence, the N-1 switches do not include the first switch, the duration of the second cycle is T ₂ , the second cycle consists of N-1 consecutive sub-cycles, the The duration of each sub-cycle in N-1 consecutive sub-cycles is T ₂ /(N-1), and the N-1 start times of the N-1 electric pulses are respectively the N-1 consecutive The N-1 start times of the subperiod.

This solution has the same technical effect as the solution in the first aspect.

Optionally, in an example, the processor executes determining the first phase fault, which specifically includes: determining an average current value of the first phase; determining N average current values of the N phases, The N phases correspond to the N average current values one by one; when the average current value of the first phase is different from the average value of the N average current values of the N phases , when a first value is exceeded, the first phase fault is determined.

Optionally, in another example, the processor executes determining the fault of the first phase, which specifically includes: detecting that the voltage converter is abnormal; disconnecting the first phase according to the detection result; determining When the first phase is in the off state and N-1 phases are in the on state, the abnormality disappears, and the N-1 phases are the N phases except the first phase and determining that the first phase is faulty based on disappearance of the abnormality.

Optionally, the processor reads the computer program, and further executes: disconnecting the first phase after determining that the first phase is faulty.

Optionally, in an example, after determining that the first phase is faulty, the processor controls N-1 switches among the N switches to output the N- Before 1 electrical pulse, further perform: disconnecting the N phases; and saving the identity of the first phase. The controlling N-1 switches among the N switches to output the N-1 electrical pulses in the second cycle specifically includes: determining the N switches according to the identification of the first phase and controlling the N-1 switches determined according to the identification of the first phase to output the N-1 electrical pulses in the second cycle.

Optionally, in another example, after the processor determines that the first phase is faulty, and controls N-1 switches among the N switches to output the N- Before 1 electrical pulse, further perform: disconnecting the N phases; and saving the identification of the N-1 phases, the N-1 phases being phases of the N phases, and the N-1 phases phases do not include the first phase. The controlling N-1 switches among the N switches to output the N-1 electrical pulses in the second period specifically includes: determining the N-1 electrical pulses according to the identifications of the N-1 phases N-1 switches among the switches; and the control circuit controls the N-1 switches determined according to the identifiers of the N-1 phases to output N-1 electrical pulses in the second period.

Based on any one of the first aspect, the second aspect or the third aspect, optionally, the duration of each of the N electric pulses is T ₃ , and the N-1 electric pulses The duration of each electric pulse is T ₄ , the T ₃ is equal to the T ₄ , and the T ₁ is equal to the T ₂ .

Based on any one of the first aspect, the second aspect or the third aspect, optionally, the voltage converter is a direct current to direct current converter (English: DCtoDCconverter).

Based on any one of the first aspect, the second aspect or the third aspect, optionally, the voltage converter is a step-down converter (English: buck converter).

Based on any one of the first aspect, the second aspect or the third aspect, optionally, the voltage converter is a voltage regulator module (English: voltage regulator module, VRM for short).

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present application more clearly, the following briefly introduces the drawings related to the embodiments. Obviously, the following figures are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained based on these drawings without any creative effort.

FIG. 1 is a schematic diagram of an application scenario provided by an embodiment of the present application.

FIG. 2 is a flow chart of a method for troubleshooting a voltage converter provided in an embodiment of the present application.

FIG. 3 is a schematic structural diagram of a control circuit provided by an embodiment of the present application.

FIG. 4 is a schematic diagram of a waveform of an electric pulse provided by an embodiment of the present application.

FIG. 5 is a schematic diagram of a waveform of an electric pulse provided by an embodiment of the present application.

Fig. 6 is a schematic structural diagram of a voltage converter provided by an embodiment of the present application.

detailed description

"First", "second" and "third" in this embodiment of the present application are only used to distinguish different objects. Not used to limit the order of the different objects. For example, the embodiments mention a first switch, a second switch and a third switch. The first switch and the second switch are not the same switch. The second switch and the third switch are not the same switch. The first switch and the third switch are not the same switch.

FIG. 1 is a schematic diagram of an application scenario provided by an embodiment of the present application. The system shown in FIG. 1 includes a voltage converter 110 and a load 120 . The voltage converter 110 includes a control circuit 111 and three phases. The first phase 112 includes a first switch 115 and an inductor L1 coupled to the first switch 115 . The second phase 113 includes a second switch 116 and an inductor L2 coupled to the second switch 116 . The third phase 114 includes a third switch 117 and an inductor L3 coupled to the third switch 117 . Point A, point C and point E shown in FIG. 1 are the output terminals of the first switch 115 , the second switch 116 and the third switch 117 respectively. When the voltage converter 110 supplies power to the load 120 normally, the first switch 115 , the second switch 116 and the third switch 117 periodically output electric pulses at their corresponding output terminals. The start times of the electric pulses output by the first switch 115 , the second switch 116 and the third switch 117 are generally evenly distributed in one cycle. Point B, point D and point F are the output terminals of the first phase 112 , the second phase 113 and the third phase 114 respectively. A capacitor C1 is also included between the output terminal of each phase and the load 120 . The electric pulses output by the first switch 115 , the second switch 116 and the third switch 117 reach the load 120 after being processed by the inductor and the capacitor C1 . Therefore, the voltage converter 110 can provide a stable DC voltage to the load 120 .

For example, the voltage converter 110 may be a direct current (English: direct current, DC for short) to direct current converter (English: DCtoDC converter). The DCtoDCconverter can convert the first DC voltage input into the DCtoDCconverter into a second DC voltage, and output the second DC voltage, for example, output the DC voltage of the second magnitude to the load 120 . The voltage value of the first DC voltage is different from the voltage value of the second DC voltage.

For example, the voltage converter 110 may be implemented by using a multi-phase (English: multi-phase) voltage regulation module (English: voltageregulatormodule, VRM for short). The VRM may be a step-down converter (English: buck converter) for supplying power to a central processing unit (English: central processing unit, CPU for short). The VRM can adjust the first DC voltage input to the VRM to the second DC voltage required by the CPU. The voltage value of the first DC voltage is greater than the voltage value of the second DC voltage. For example, the voltage value of the first voltage may be 5V or 12V. The first switch 115 , the second switch 116 and the third switch 117 shown in FIG. 1 can be respectively used to realize the output of multiple phases in the VRM. For example, for the specific implementation of the VRM and the pulse width modulation (English: pulsewidthmodule, PWM) module in the embodiment of the present application, please refer to the VR12/IMVP7 pulse width modulation specification (English: VR12 PWM) issued by Intel Corporation in June 2010. /IMVP7PulseWidthModulationSpecification).

When a phase in the voltage converter 110 , such as the first phase 112 fails, the voltage converter 110 cannot normally supply power to the load 120 . For example, in one cycle, if the voltage converter 110 works normally, the first switch 115 outputs a first electric pulse at a first preset time, the second switch 116 outputs a second electric pulse at a second preset time, and the third switch 115 outputs a second electric pulse at a second preset time. The switch 117 outputs a third electrical pulse at a third preset time. When the first phase 112 fails, the first switch 115 may fail to output the first electrical pulse within the first preset time. That is, a cycle may only have two electrical pulses. And the two electrical pulses are not evenly distributed in one cycle. The output voltage of the voltage converter is an unsteady voltage. Therefore, when a phase of the voltage converter 110 fails, the voltage converter 110 cannot normally supply power to the load 120 .

Fig. 2 is a flowchart of a voltage converter fault detection method provided by an embodiment of the present application. The method shown in FIG. 2 can be used in the circuit structure in FIG. 1 to realize the functions of the control circuit in FIG. 1 . For example, when a certain phase in FIG. 1 fails, the method shown in FIG. 2 may be used to handle the failure. The voltage converter in the method shown in FIG. 2 includes a control circuit and N phases, the N phases include N switches, the N phases correspond to the N switches one by one, and N is greater than 2 an integer of .

The method includes S201, S202 and S203.

S201. The control circuit controls the N switches to output N electrical pulses in a first period.

The N switches correspond to the N electrical pulses one by one, the duration of the first cycle is T ₁ , the first cycle is composed of N consecutive sub-cycles, and the N consecutive sub-cycles The duration of each sub-period is T ₁ /N, and the N starting times of the N electrical pulses are respectively the N starting times of the N consecutive sub-periods.

Specifically, the N electrical pulses are in one-to-one correspondence with the N starting times. Each of the N electrical pulses has a start time. The N starting times of the N electrical pulses are respectively the N starting times of the N consecutive sub-periods.

S202. After the control circuit controls the N switches to output the N electrical pulses in the first period, the control circuit determines that the first phase is faulty.

The first phase is one of the N phases, the first phase includes a first switch, and the first switch is one of the N switches.

S203. After the control circuit determines that the first phase is faulty, the control circuit controls N-1 switches among the N switches to output N-1 electrical pulses in a second period.

The N-1 switches are in one-to-one correspondence with the N-1 electrical pulses, the N-1 switches do not include the first switch, the duration of the second cycle is T ₂ , and the first The second cycle consists of N-1 consecutive sub-cycles, the duration of each sub-cycle in the N-1 consecutive sub-cycles is T ₂ /(N-1), and the N of the N-1 electric pulses The -1 start times are respectively the N-1 start times of the N-1 consecutive sub-periods.

Specifically, the N-1 electrical pulses are in one-to-one correspondence with the N-1 start times. Each of the N electrical pulses has a start time. The N starting times of the N-1 electrical pulses are respectively the N-1 starting times of the N-1 consecutive sub-periods.

The N consecutive sub-periods in this application means that among the N consecutive sub-periods, the end time of one sub-period is equal to the start time of another sub-period in the adjacent sub-periods. For example, N consecutive sub-periods include a first sub-period, a second sub-period and a third sub-period. The first sub-period and the second sub-period are adjacent sub-periods. The second sub-period and the third sub-period are adjacent sub-periods. The first sub-period precedes the second sub-period. The second sub-period precedes the third sub-period. The end time of the first period is equal to the start time of the second sub-period. The end time of the second period is equal to the start time of the third sub-period.

Similarly, the N-1 consecutive sub-periods in this application means that among the N-1 consecutive sub-periods, the end time of one sub-period in the adjacent sub-periods is equal to the start time of another sub-period.

The control circuit 111 in FIG. 1 can be used to implement the control circuit in the method shown in FIG. 2 . The first switch 115 , the second switch 116 and the third switch 117 in FIG. 1 can be used to realize the N switches in the method shown in FIG. 2 . N is an integer greater than 2. N in Fig. 1 is equal to 3. Of course, more switches may also be included in FIG. 1 , so as to realize the scenario where N may be greater than 3 in the method shown in FIG. 2 . The method shown in FIG. 2 will be described below only by taking N equal to 3 shown in FIG. 1 as an example. The first phase 112 , the second phase 113 and the third phase 114 in FIG. 1 can be used to implement the N phases in the method shown in FIG. 2 .

Fig. 3 is a schematic structural diagram of a control circuit provided by the embodiment. The control circuit 300 in FIG. 3 can be used to execute the method described in FIG. 2 . Specifically, the control circuit 300 can be used to implement the control circuit in the method shown in FIG. 2 . The control circuit 300 can be used to implement the control circuit 111 shown in FIG. 1 . As shown in FIG. 3 , the control circuit 300 includes a fault control module 310 , a phase control module 320 , a first PWM module 330 , a second PWM module 340 and a third PWM module 350 . The fault control module 310, the phase control module 320, the first PWM module 330, the second PWM module 340 and the third PWM module 350 communicate through the bus. For example, the bus may be a power management bus (English: powermanagementbus, PMBus for short). Of course, the controller 300 shown in FIG. 3 may include more PWM modules, so as to realize the scenario where N is greater than 3 in the method shown in FIG. 2 . Optionally, the control circuit 300 further includes a current detection module 360 . For example, the above-mentioned modules in the control circuit 300 may be implemented by an application-specific integrated circuit (English: application-specific integrated circuit, ASIC for short).

For example, the first PWM module 330 in the control circuit 300 can be coupled with the first switch 115 shown in FIG. 1 , so as to control the first switch 115 . The second PWM module 340 can be coupled with the second switch 116 shown in FIG. 1 to control the second switch 116 . The third PWM module 350 can be coupled with the third switch 117 shown in FIG. 1 to control the third switch 117 .

In the following, the first PWM module 330 periodically sends a control signal to the first switch 115, thereby controlling the first switch 115 to periodically output electric pulses as an example. For the first switch 115, the second switch 116 And the principle of the third switch 117 outputting electric pulses will be described.

For example, the first switch 115 may be composed of a P-channel metal oxide semiconductor (English: positive channel metal oxide semiconductor, PMOS for short) and an N-channel metal oxide semiconductor (English: negative channel metal oxide semiconductor, NMOS for short) connected in series. The switching tube is realized. The drain of the PMOS is coupled to the input voltage (hereinafter referred to as Vin) input to the voltage converter 110 from the outside of the voltage converter 110, the source of the PMOS is coupled to the drain of the NMOS, and the NMOS The source of is coupled to ground as shown in Figure 1. The first PWM 330 controls the state of the first switch by sending control signals to the gates of the NMOS and the PMOS respectively. For example, when the first PWM 330 sends a first low-level signal to the NMOS and a second low-level signal to the gate of the PMOS, the first switch 115 is in state 1 . That is, the PMOS is turned on, and the NMOS is not turned on. When the first switch 115 is in state 1, the first switch 115 outputs an electric pulse at point A. The voltage value of the electric pulse is equal to the voltage value of _Vin . When the first PWM 330 sends a first high-level signal to the NMOS and a second high-level signal to the gate of the PMOS, the first switch 115 is in state 2 . That is, the NMOS is turned on, and the PMOS is not turned on. When the first switch 115 is in state 2, the first switch 115 does not output an electric pulse at point A. When the first switch 115 is in state 2, the voltage value at point A is equal to the voltage value of the ground wire. For example, the voltage value of the ground wire may be equal to 0V. When the first PWM 330 sends a first mid-level signal to the NMOS and a second mid-level signal to the gate of the PMOS, the first switch 115 is in state 3 . That is, the PMOS is off, the NMOS is off, and the first phase 112 is in a disconnected state. When the first switch 115 is in state 3, the first switch 115 does not output an electric pulse at point A. High-level signals, mid-level signals, and low-level signals are relative concepts. Specifically, the level of the high level signal sent by the PWM module to the same MOS is higher than the level of the middle level signal. The level of the mid-level signal sent by the PWM module to the same MOS is higher than that of the low-level signal. Those skilled in the art can understand that the first high-level signal, the second high-level signal, the first intermediate-level signal, the second intermediate-level signal, the first low-level The voltage values of the level signal and the second low level signal may be selected according to the conduction voltages of the NMOS and the PMOS.

The switch in this application refers to a circuit that outputs an electric pulse in the first cycle or the second cycle under the control of the control circuit. For example, when the above-mentioned first switch 115 is realized by two MOSs, that is, PMOS and NMOS, one PMOS and one NMOS constitute a switch in the first phase. The state of the switch can be one of the following three. In state 1, the output terminal of the switch is coupled to _Vin , and the voltage value output by the switch is equal to the voltage value of Vin, that is, the switch outputs electric pulses at its output terminal; in state 2, the output of the switch Terminal is coupled with the ground wire, the voltage value output by the switch is equal to the voltage value of the ground wire, for example, the voltage value is 0V, and the switch does not output electric pulses at its output terminal; state 3, the switch’s The output terminal is disconnected from the V _in and the ground wire, and the switch does not output electric pulses at its output terminal.

For example, the first PWM module 330 sends a control signal to the first switch 115 , it may be that the first PWM module 330 sends a control signal to the first switch 115 directly. Alternatively, a driving circuit may be included between the first PWM module 330 and the first switch 115 . The first PWM module 330 sends a control signal to the driving circuit. The driving amplifies the control signal, and sends the amplified control signal to the first switch 115 .

For example, when the voltage converter 110 supplies power to the load 120 , the first PWM module 330 periodically sends the high level signal and the low level signal. Correspondingly, the state of the first switch 115 is periodically switched between the state 1 and the state 2 . When the first switch 115 is in state 1, the first switch outputs an electric pulse at the point A.

For example, the second switch 116 periodically outputs electric pulses at point C, and the third switch 117 periodically outputs electric pulses at point E, which may be the same as the first switch 115 output at point A. The same implementation of electrical pulses is achieved.

For example, the first PWM module 330 , the second PWM module 340 and the third PWM module 350 can be implemented by a signal generator.

For example, the first switch 115 in the first phase 112, the second switch 116 in the second phase 113 and the third switch 117 in the third phase 114 output electric pulses in one cycle start times are different. The starting times of the three electrical pulses output by the three switches are evenly distributed within one cycle.

For example, FIG. 4 shows that in the first period described in S201, the electric pulse output by the first switch 115 at point A, the electric pulse output by the second switch 116 at point C, and the electric pulse output by the third switch 117 at point E A possible implementation of the waveform of the output electric pulse. The first period is composed of a first sub-period, a second sub-period and a third sub-period. The duration of the first cycle is T ₁ . Assume that the start time of the first cycle is 0. The end time of the first period is T ₁ . The start time of the first sub-period is 0, and the end time is T ₁ /3. The start time of the second sub-period is T ₁ /3, and the end time is 2T ₁ /3. The start time of the third sub-period is 2T ₁ /3, and the end time is T ₁ . The durations of the electrical pulses output by the first switch 115 , the second switch 116 and the third switch 117 in the first cycle are all T ₃ . Each of the first switch 115 , the second switch 116 and the third switch 117 does not output an electric pulse for a period of time T ₁ -T ₃ in the first period. In the first period, when the switch outputs an electric pulse, the switch is in the state 1 . In the first period, when the switch does not output an electric pulse, the switch is in the state 2, and the amplitude of the output voltage may be 0V. Those skilled in the art can understand that when the switch is switched from the state 1 to the state 2, the switch outputs the rising edge of the electric pulse, and when the switch is switched from the state 2 to the state 1 , the switch outputs the falling edge of the electric pulse. The duration of the rising edge is much shorter than T ₃ , and the duration of the falling edge is much shorter than T ₃ .

For example, the actual voltage that each phase of the voltage converter 110 supplies to the load 120 is the time average of the voltage values of the switch outputs included in the phase. For example, in the first phase 112, in the first period, the duration of the electric pulse whose voltage value is equal to the voltage value of V _in output by the first switch 112 at point A is T ₃ , and the output voltage value is The time period for 0V is T ₁ -T ₃ . The voltage at point A passes through the low-pass filter formed by L1 and C1 shown in FIG. 1 , and the value of the voltage applied to the load 120 is (V _in *T ₃ )/T ₁ . Similarly, in the second phase 113 and the third phase 114, the voltage value applied to the load 120 is also (Vin*T ₃ )/T ₁ .

For example, the first switch 115 , the second switch 116 and the third switch 117 have different start times of outputting electrical pulses in the first cycle shown in FIG. 4 . The above process can be implemented by the phase control module 320 shown in FIG. 3 sending different clock signals to the first PWM module 330 , the second PWM module 340 and the third PWM module 350 respectively. The clock frequency of the clock signal sent by the phase control module 320 to the PWM module is the same, and the phase of the clock signal sent by the phase control module 320 to the PWM module is different. For example, the time corresponding to the rising edge of the clock signal sent by the phase control module 320 to the PWM module is different. The first PWM module 330 , the second PWM module 340 and the third PWM module 350 respectively receive the clock signal of the phase control module 320 . Each PWM module outputs a low-level signal at a time corresponding to the rising edge of the received clock signal, and the switch coupled with the PWM module enters the state 1 . The time corresponding to the rising edge of the clock signal is the start time for the PWM module to output a low level signal. The duration of each PWM module outputting the low-level signal is T ₃ , and the time length of T ₃ is determined by the voltage value required by the load 120 . After a duration _of T3, the control signal output by the PWM module changes from the low-level signal to a high-level signal, and the switch coupled with the PWM module enters the state 2 .

Optionally, in an example, determining that the first phase 112 is faulty by the control circuit in S202 includes: the control circuit determining an average current value of the first phase 112 . The control circuit acquires N average current values of the N phases, and the N phases are in one-to-one correspondence with the N average current values. When the difference between the average current value of the first phase 112 and the average value of the N average current values of the N phases exceeds a first value, the control circuit determines that the first phase 112 failure.

Correspondingly, the control circuit 300 shown in FIG. 3 includes a current detection module 360 . The first phase 112 , the second phase 113 and the third phase 114 in the voltage converter 110 respectively include a current detection device (not shown in FIG. 1 ). The current detection device is used to measure the average current of each of the three phases. The average current refers to the average value of the current within the detection period. In one example, the current detection device measures the average current of L1 shown in FIG. 1 as the average current of the first phase 112, and measures the average current of L2 shown in FIG. 1 as the second phase 113 The average current of L3 shown in FIG. 1 is measured as the average current of the third phase 114 . In another example, the first switch 115 , the second switch 116 and the third switch 117 are respectively implemented by switching transistors composed of the PMOS and the NMOS connected in series. The current detection device 360 measures the average voltage between the source and the drain of the NMOS respectively. The NMOS has a specific resistance value in the state of receiving a high-level signal and in the state of receiving a low-level signal. Therefore, according to the conduction period of the NMOS, such as the T ₁ -T ₃ , and the non-conduction period of the NMOS, such as the T ₁ , the current detection device 360 can calculate the average value of the NMOS resistance. Further, the current detection device 360 calculates the average current of the phase where the NMOS is located according to the average resistance value of the NMOS and the average voltage of the NMOS.

For example, the current detection module 360 determines the average current value of each phase measured by the current detection device, and calculates the average value of the average current values of the three phases. The current detection module 360 compares whether the difference between the average current value of each phase and the average value of the average current values of the three phases is greater than the first value through a comparator. The first value is a preset value. The first value may be the maximum value of fluctuations in the value of the average current allowed when the voltage converter works normally. For example, the first value is 10% of the average value of the N average current values. If the difference between the average current value of the first phase 112 and the average value of the three average current values exceeds the first value, the current detection module 360 determines that the first phase 112 is faulty. Further, the current detection module 360 sends the identification of the first phase 112 to the fault control module 310 and the phase control module 320 .

For example, in another example, the determining by the control circuit in S202 that the first phase 112 is faulty includes: the control circuit detects that the voltage converter is abnormal. The control circuit disconnects the first phase 112 according to the detection result. The control circuit 111 determines that the abnormality disappears when the first phase 112 is in the off state and N-1 phases are in the on state, and the N-1 phases are the N Phases of the phases other than the first phase. The control circuit determines that the first phase 112 is faulty based on the disappearance of the abnormality.

In the present application, a certain phase is in the disconnected state, which means that the switch included in the phase is in the state 3 . The output end of the switch is not connected to _Vin , and the output end of the switch is not connected to the ground. The fact that a certain phase is in the on state means that the state 1 and the state 2 alternate for the state of the switch included in the phase. The switch periodically outputs electric pulses.

For example, the control circuit 300 further includes an abnormality detection module (not shown in FIG. 3 ), configured to detect the voltage at both ends of the load 120 . When the voltage across the load 120 is greater than a second value within a certain time or within a certain duration, the control circuit determines that the voltage converter is abnormal. For example, the fault of the first phase 112 is a short circuit of a component in the first phase 112 . For example, the inductor or the first switch in the first phase 112 is short-circuited. The short circuit of the first phase 112 causes abnormality of the voltage converter 110 that the voltage across the load 120 is greater than the second value. After the control circuit 300 determines that the voltage converter 110 is abnormal, it disconnects the first phase 112 , the second phase 113 and the third phase 114 according to the abnormality of the voltage converter 110 . Afterwards, the control circuit 300 disconnects one of the first phase 112, the second phase 113, and the third phase 114 in FIG. 1 according to the configured instructions, and controls the other two phases The corresponding switch periodically outputs electric pulses. The control circuit 300 detects whether the abnormality disappears after the certain item is disconnected. For example, the disappearance of the abnormality means that the voltage across the load 120 does not exceed a third value. The third value is less than the second value. If the first phase 112 is off, and the second phase 113 and the third phase 114 are on, and the abnormality disappears, then the abnormality detection module determines that the first phase 112 faults lead to abnormal conditions of the voltage converter 110 . Further, the abnormality detection module sends the identification of the first phase 112 to the fault control module 310 and the phase control module 320 .

Optionally, in an example, after S202 and before S203, the control circuit 300 further includes disconnecting the first phase 112 .

For example, disconnection of the first phase 112 by the control circuit 300 may be implemented by the fault control module 310 shown in FIG. 3 controlling the first PWM module 330 . The fault control module 310 sets the output of the first PWM module 330 to a high-impedance state (English: highimpedance), so that the first PWM module 330 no longer periodically outputs the low-level signal or the high level signal. Further, the output end of the first PWM module is also connected to an intermediate level output module, and the intermediate level output module may be implemented by a voltage dividing resistor connected between V _in and ground. The first PWM module outputs an intermediate level to the first switch, so that neither the PMOS nor the NMOS of the first switch is turned on. That is, when the first switch is in the state 3, the first phase 112 is disconnected.

Optionally, in another example, after S302 and before S303, the control circuit further includes disconnecting the N phases. The control circuit saves the identifier of the first phase 112, or the control circuit saves identifiers of N−1 phases. The N−1 phases are phases in the N phases, and the N−1 phases do not include the first phase 112 .

For example, the identification of the first phase 112, or the identifications of the N−1 phases, is stored in a register (not shown in FIG. 3 ) of the control circuit 300 . The registers can be respectively located in the phase control module 320 and the fault control module 310 , and can also be located in the control circuit 300 . The communication between the phase control module 320 and the fault control module 310 can access the register through the bus.

FIG. 5 shows a possible implementation of the electric pulse output by the second switch 116 at point C in the second period in S203 and the waveform of the electric pulse output by the third switch 117 at point E. Way. In this embodiment, the N is equal to 3, and N-1 is equal to 2. The second period is composed of a fourth sub-period and a fifth sub-period. The duration of the second period is T ₂ . Assume that the start time of the second period is 0. The end time of the second period is T ₂ . The start time of the fourth sub-period is 0, and the end time is T ₂ /2. The starting time of the fifth sub-period is T ₂ /2, and the ending time is T ₂ . In the second period, the second switch 116 and the third switch 117 both output the electrical pulse for a duration of T ₄ . Each switch in the second switch 116 and the third switch 117 does not output an electric pulse for a period of time T ₂ -T ₄ in the second period.

Optionally, the T ₃ is equal to the T ₄ , and the T ₁ is equal to the T ₂ .

Optionally, if after S202 and before S203, it also includes that the control circuit disconnects the N phases, and the control circuit saves the identifier of the first phase 112, then S203 includes that the control circuit An identifier of a phase 112 determines N−1 switches among the N switches. S203 includes the control circuit controlling the N−1 switches determined according to the identification of the first phase 112 to output N−1 electrical pulses in a second cycle.

Specifically, the N switches of the voltage converter are in one-to-one correspondence with the N phases. Determining the N−1 switches according to the identifier of the first phase 112 refers to determining N−1 switches other than the first switch among the N switches.

Optionally, if after S202 and before S203, it also includes that the control circuit disconnects the N phases, and the control circuit saves the identifiers of the N-1 phases, then S203 includes that the control circuit according to the Identify N-1 phases, and determine N-1 switches among the N switches. S203 includes the control circuit controlling the N-1 switches determined according to the identifications of the N-1 phases to output N-1 electrical pulses in a second period.

Specifically, the N switches of the voltage converter are in one-to-one correspondence with the N phases. Determining the N-1 switches according to the identifiers of the N-1 phases refers to determining the N-1 switches included in the N-1 phases.

Fig. 6 is a schematic structural diagram of a voltage converter provided by an embodiment of the present application. The voltage converter 600 includes a control unit 601, a detection unit 602, and N phases 603. The N phases 603 include N switches (not shown in FIG. 6 ), and the N phases 603 and the N The switches are in one-to-one correspondence, and N is an integer greater than 2. For example, the voltage converter 600 may be implemented by using the voltage converter 110 shown in FIG. 1 . For example, the control unit 601 and the detection unit 602 can be realized by using the control circuit 111 shown in FIG. 1 . When N is equal to 3, the N phases 603 can be realized by using the first phase 112 , the second phase 113 and the third phase 114 shown in FIG. 1 .

Referring to FIG. 6 , a voltage converter 600 may be used to implement the method shown in FIG. 2 . The control unit 601 and the detection unit 602 in the voltage converter 600 can be realized by the control circuit 300 in FIG. 3 .

The control unit 601 is configured to control the N switches to output N electric pulses in the first period, and the N switches correspond to the N electric pulses one by one. The duration of the first cycle is T ₁ , the first cycle is composed of N consecutive sub-cycles, the duration of each sub-cycle in the N consecutive sub-cycles is T ₁ /N, and the N The N starting times of the electrical pulses are respectively the N starting times of the N consecutive sub-periods.

Specifically, the N electrical pulses are in one-to-one correspondence with the N starting times. Each of the N electrical pulses has a start time. The N starting times of the N electrical pulses are respectively the N starting times of the N consecutive sub-periods.

For example, the control unit 601 may be configured to execute S201 shown in FIG. 2 .

The detection unit 602 is configured to determine a first phase fault after the control unit 601 controls the N switches to output the N electrical pulses in the first period. The first phase is one of the N phases 603, the first phase includes a first switch, and the first switch is one of the N switches.

For example, the detecting unit 602 may be used to execute S202 shown in FIG. 2 .

The control unit 601 is further configured to, after the detection unit 602 determines that the first phase is faulty, control N-1 switches among the N switches to output N-1 electric pulses in the second cycle, The N-1 switches are in one-to-one correspondence with the N-1 electrical pulses. The N-1 switches do not include the first switch, the second cycle has a duration of T ₂ , the second cycle consists of N-1 consecutive sub-cycles, and the N-1 consecutive sub-cycles The duration of each sub-period in the sub-period is T ₂ /(N-1), and the N-1 start times of the N-1 electric pulses are N of the N-1 consecutive sub-periods respectively. -1 start time.

Specifically, the N-1 electrical pulses are in one-to-one correspondence with the N-1 start times. Each of the N electrical pulses has a start time. The N starting times of the N-1 electrical pulses are respectively the N-1 starting times of the N-1 consecutive sub-periods.

For example, the control unit 601 may also be configured to execute S203 shown in FIG. 2 .

Each of the above units can be realized by pure hardware, or by a combination of hardware and software. For example, the CPU implements the above-mentioned respective units by executing a computer program stored in the memory.

For example, in an example, the detection unit 602 is specifically configured to: determine the value of the average current of the first phase; obtain the values of N average currents of the N phases, and the N phases One-to-one correspondence with the N average current values; and when the difference between the average current value of the first phase and the average value of the N average current values of the N phases exceeds the first value, it is determined that the first phase 112 is faulty.

For example, in another example, the detection unit 602 is specifically configured to: detect that the voltage converter is abnormal; disconnect the first phase according to the detection result; determine when the first phase The abnormality disappears when the phase is in the off state and N-1 phases are in the on state, and the N-1 phases are phases other than the first phase among the N phases; And based on the fact that the abnormality disappears, it is determined that the first phase is faulty.

Optionally, after the detection unit determines that the first phase is faulty, the control unit 601 is further configured to: disconnect the first phase.

Optionally, in an example, the control unit 601 controls N-1 switches among the N switches in the second period after the detection unit determines that the first phase is faulty. Before outputting the N-1 electrical pulses, it is also used to: disconnect the N phases 603; and save the identifier of the first phase. The control unit controls N-1 switches in the N switches to output the N-1 electrical pulses in the second cycle, which specifically includes: determining the N N-1 switches among the switches; and controlling the N-1 switches determined according to the identification of the first phase to output the N-1 electrical pulses in the second period.

Optionally, in another example, after the detection unit determines that the first phase is faulty, the control unit 601 controls N-1 switches among the N switches to switch in the second period Before outputting the N-1 electric pulses, it is also used to: disconnect the N phases 603; and save the identification of the N-1 phases, and the N-1 phases are the N phases For phases in 603, the N-1 phases do not include the first phase. The control unit 601 controls N-1 switches in the N switches to output the N-1 electrical pulses in the second period, specifically including: determining according to the identification of the N-1 phases N-1 switches among the N switches; and controlling the N-1 switches determined according to the identifiers of the N-1 phases to output N-1 electric pulses in the second period.

Optionally, the duration of each of the N electrical pulses is T ₃ , the duration of each of the N-1 electrical pulses is T ₄ , and the T ₃ is equal to the T ₄ . Said T ₁ is equal to said T ₂ .

The control unit 601 and the detection unit 602 in the voltage converter 600 provided in this embodiment can be realized by the control circuit 300 shown in FIG. 3 and applied to the scenario shown in FIG. 1 . For the functions that the voltage converter 600 can implement, please refer to the description of the embodiment shown in FIG. 2 , and details will not be repeated here.

The voltage converter provided in the above-mentioned embodiments is only illustrated by the division of the above-mentioned functional modules. In practical applications, the above-mentioned function allocation can be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functions. module to complete all or part of the functions described above.

Each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments.

The control circuit used to execute the functions of the above-mentioned fault handling device of this application may be a CPU, a general-purpose processor, an ASIC, a field programmable gate array (English: Field-Programmable Gate Array, referred to as: FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. It can implement or execute the various illustrative logical blocks, modules and circuits described in connection with the present disclosure. The processor may also be a combination of computing functions, for example, a combination of one or more microprocessors, a combination of DSP and a microprocessor, and so on.

The steps of the methods or algorithms described in connection with the disclosure of this application can be implemented in the form of hardware, or can be implemented in the form of a processor executing software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory (English: random access memory, referred to as: RAM), flash memory, read-only memory (English: readonly memory, referred to as: ROM), erasable and programmable Read-only memory (English: erasable programmable read-only memory, referred to as: EPROM), electrically erasable programmable read-only memory (English: electrically erasable programmable read-only memory, referred to as: EEPROM), registers, hard disk, mobile hard disk, CD-ROM or any other known in the art form of storage media. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. Of course, the storage medium may also be a component of the processor. The processor and storage medium can be located in the ASIC.

The specific implementation manners described above have further described the purpose, technical solutions and beneficial effects of the application in detail. It should be understood that the above descriptions are only specific implementation modes of the application and are not intended to limit the scope of the application. protected range.

Claims (14)

1. A fault handling method for a voltage converter, characterized in that, the voltage converter includes a control circuit and N phases, the N phases include N switches, the N phases and the N switches One-to-one correspondence, N is an integer greater than 2, The methods include: The control circuit controls the N switches to output N electric pulses in the first cycle, and the N switches correspond to the N electric pulses one by one, and the duration of the first cycle is T ₁ , so The first cycle is composed of N consecutive sub-cycles, the duration of each sub-cycle in the N consecutive sub-cycles is T ₁ /N, and the N starting times of the N electric pulses are respectively the N start times of N consecutive sub-periods; After the control circuit controls the N switches to output the N electrical pulses in the first period, the control circuit determines that the first phase is faulty, and the first phase is one of the N phases phase, the first phase includes a first switch, and the first switch is one of the N switches; After the control circuit determines that the first phase is faulty, the control circuit controls N-1 switches among the N switches to output N-1 electric pulses in the second period, and the N-1 switches One-to-one correspondence with the N-1 electrical pulses, the N-1 switches do not include the first switch, the second cycle has a duration of T ₂ , and the second cycle consists of N-1 Consecutive sub-periods, the duration of each sub-period in the N-1 consecutive sub-periods is T2/(N- ₁ ), and the N-1 start times of the N-1 electrical pulses are respectively are the N-1 start times of the N-1 consecutive sub-periods. 2. The method according to claim 1, wherein the control circuit determining the first phase fault comprises: the control circuit determines a value of the average current of the first phase; The control circuit determines the values of N average currents of the N phases, and the N phases correspond to the N average currents one by one; The control circuit determines that the first phase is faulty when the difference between the value of the average current of the first phase and the average value of the N average current values of the N phases exceeds a first value . 3. The method according to claim 1, wherein the control circuit determining the first phase fault comprises: The control circuit detects that the voltage converter is abnormal; The control circuit disconnects the first phase according to the detection result; The control circuit determines that the abnormality disappears when the first phase is in the off state and N-1 phases are in the on state, the N-1 phases being the N phases a phase other than said first phase; The control circuit determines that the first phase is faulty based on the disappearance of the abnormality. 4. The method according to any one of claims 1 to 3, wherein after the control circuit determines that the first phase is faulty, the method further comprises: The control circuit disconnects the first phase. 5. The method according to any one of claims 1 to 3, wherein after the control circuit determines that the first phase is faulty, and the control circuit controls N-1 switches in the N switches Before outputting the N-1 electrical pulses in the second cycle, the method further includes: the control circuit disconnects the N phases; and The control circuit saves the identity of the first phase; The control circuit controls N-1 switches among the N switches to output the N-1 electrical pulses in the second cycle, specifically including: The control circuit determines N-1 switches among the N switches according to the identifier of the first phase; and The control circuit controls the N-1 switches determined according to the identifier of the first phase to output the N-1 electrical pulses in the second period. 6. The method according to any one of claims 1 to 3, wherein after the control circuit determines that the first phase is faulty, and the control circuit controls N-1 switches in the N switches Before outputting the N-1 electrical pulses in the second cycle, the method further includes: the control circuit disconnects the N phases; and The control circuit saves identifiers of N-1 phases, the N-1 phases are phases of the N phases, and the N-1 phases do not include the first phase; The control circuit controls N-1 switches among the N switches to output the N-1 electrical pulses in the second cycle, specifically including: The control circuit determines N-1 switches among the N switches according to the identifiers of the N-1 phases; and The control circuit controls the N-1 switches determined according to the identifiers of the N-1 phases to output N-1 electric pulses in the second cycle. 7. The method according to any one of claims 1 to 6, characterized in that, the duration of each electrical pulse in the N electrical pulses is T ₃ , and each electrical pulse in the N-1 electrical pulses The duration of the pulse is T ₄ , the T ₃ is equal to the T ₄ , and the T ₁ is equal to the T ₂ . 8. A voltage converter, characterized in that, the voltage converter comprises a control unit, a detection unit and N phases, the N phases comprise N switches, the N phases are identical to the N switches One-to-one correspondence, N is an integer greater than 2, where, The control unit is configured to control the N switches to output N electric pulses in a first cycle, the N switches correspond to the N electric pulses one by one, and the duration of the first cycle is T ₁ , the first cycle is composed of N consecutive sub-cycles, the duration of each sub-cycle in the N consecutive sub-cycles is T ₁ /N, and the N starting times of the N electric pulses are respectively are the N starting times of the N consecutive sub-periods; The detection unit is configured to determine that the first phase is faulty after the control unit controls the N switches to output the N electrical pulses in the first cycle, and the first phase is the N one of the phases, the first phase including a first switch, the first switch being one of the N switches; The control unit is further configured to control N-1 switches among the N switches to output N-1 electrical pulses in a second cycle after the detection unit determines that the first phase is faulty, the The N-1 switches correspond to the N-1 electrical pulses one by one, the N-1 switches do not include the first switch, the duration of the second cycle is T ₂ , and the second cycle It consists of N-1 consecutive sub-cycles, the duration of each sub-cycle in the N-1 consecutive sub-cycles is T ₂ /(N-1), and the N-1 of the N-1 electric pulses The start times are respectively the N-1 start times of the N-1 consecutive sub-periods. 9. The voltage converter according to claim 8, wherein the detection unit is specifically used for: determining the value of the average current of the first phase; determining the values of N average currents of the N phases, the N phases corresponding to the N average currents one by one; When the difference between the average current value of the first phase and the average value of the N average current values of the N phases exceeds a first value, it is determined that the first phase is faulty. 10. The voltage converter according to claim 8, wherein the detection unit is specifically used for: An abnormality of the voltage converter is detected; disconnecting the first phase according to a result of the detection; It is determined that the abnormality disappears when the first phase is in the off state and N-1 phases are in the on state, and the N-1 phases are the N phases except the first phase other than phase; and Based on the disappearance of the abnormality, it is determined that the first phase is faulty. 11. The voltage converter according to any one of claims 8 to 10, wherein the control unit is further configured to: after the detection unit determines that the first phase is faulty disconnect the first phase. 12. The voltage converter according to any one of claims 8 to 10, wherein the control unit controls N- Before outputting the N-1 electric pulses in the second cycle, one switch is also used for: disconnecting the N phases; and saving the identity of the first phase; The control unit controls N-1 switches among the N switches to output the N-1 electrical pulses in the second cycle, specifically including: determining N-1 switches among the N switches according to the identification of the first phase; and controlling the N-1 switches determined according to the identifier of the first phase to output the N-1 electrical pulses in the second cycle. 13. The voltage converter according to any one of claims 8 to 10, wherein the control unit controls N- Before outputting the N-1 electric pulses in the second period, one switch is also used for: disconnecting the N phases; and storing identifiers of N-1 phases, where the N-1 phases are phases in the N phases, and the N-1 phases do not include the first phase; The control unit controls N-1 switches among the N switches to output the N-1 electrical pulses in the second cycle, specifically including: Determine N-1 switches among the N switches according to the identifiers of the N-1 phases; and The N-1 switches determined according to the N-1 phase identifiers are controlled to output N-1 electric pulses in the second cycle. 14. The voltage converter according to any one of claims 8 to 13, characterized in that, the duration of each electrical pulse in the N electrical pulses is T ₃ , and each of the N-1 electrical pulses The duration of an electrical pulse is T ₄ , the T ₃ is equal to the T ₄ , and the T ₁ is equal to the T ₂ .