CN105448920A - Semiconductor device and manufacturing method thereof and electronic device - Google Patents
Semiconductor device and manufacturing method thereof and electronic device Download PDFInfo
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- CN105448920A CN105448920A CN201410325581.6A CN201410325581A CN105448920A CN 105448920 A CN105448920 A CN 105448920A CN 201410325581 A CN201410325581 A CN 201410325581A CN 105448920 A CN105448920 A CN 105448920A
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- material layer
- spacer material
- shallow trench
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Abstract
The invention discloses a semiconductor device and a manufacturing method thereof and an electronic device. The method comprises the following steps: forming a liner oxide layer and a liner nitride layer on a semiconductor substrate in sequence; etching the liner oxide layer, the liner nitride layer and a part of the semiconductor substrate to form shallow trenches; forming first isolation material layers on the bottoms of the shallow trenches by adopting FCVD process; filling the rest shallow trenches by adopting HARP process to form second isolation material layers, wherein the second isolation material layers are arranged on the first isolation material layers respectively; and executing the planarization process. According to the manufacturing method, voids are not generated in the STIs under the GOX, thereby preventing electric leakage between word lines; the STI structure under the GOX is conformal, thereby preventing the distance from a control grid to an active region from being too small; and the HARP cannot fill the STI structure, the depth-to-width ratio of which is 10:1, but can fill the STI structure, the depth-to-width ratio of which is 5: 1.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly relate to a kind of embedded flash memory and preparation method thereof.
Background technology
Nand flash memory is a kind of storage scheme more better than hard disk drive, because nand flash memory reads and writes data in units of page, so be suitable for storing continuous print data, as picture, audio frequency or alternative document data; Simultaneously because its cost is low, capacity large and the advantage that writing speed is fast, the erasing time is short is widely used in the field of storage of device for mobile communication and portable multimedia device.At present, in order to improve the capacity of nand flash memory, need the integration density improving nand flash memory in preparation process.
For the nand flash memory of high integration, fleet plough groove isolation structure (STI, ShallowTrenchIsolation) plays vital effect for gap-fill.When the integrated level of nand flash memory is when 3X is below horizontal, unit to the depth-to-width ratio of unit up to 10:1.Therefore usually adopt HARP (highaspectratioprocess) technique to fill the gap of above-mentioned high-aspect-ratio, but in the fleet plough groove isolation structure that HARP is formed, often there is crack, especially between active area and active area, electric leakage (leakage) problem that this problem will cause between wordline and wordline.
Substitute HARP technique, also someone adopts FCVD (FlowableCVD) technique to be used for gap-fill.FCVD technique has good clearance filling capability, but the high-aspect-ratio due to shallow trench makes FCVD technique still have problems.Adopt water cure and Ann technique can not make the fully densification of central film portion part.This is by too short for the distance caused between control gate to active area.
Therefore, a kind of method of making nand flash memory memory is newly needed, to solve the problems of the prior art.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
In order to solve problems of the prior art, the embodiment of the present invention one proposes a kind of manufacture method of semiconductor device, comprising: provide Semiconductor substrate, is formed with pad oxide and pad nitride layer on the semiconductor substrate successively; Etch the described Semiconductor substrate of described pad nitride layer, described pad oxide and part, to form shallow trench; FCVD technique is adopted to form the first spacer material layer in the bottom of described shallow trench; Adopt the remaining described shallow trench of HARP process filling to form the second spacer material layer, described second spacer material layer is positioned on described first spacer material layer; Perform flatening process.
Alternatively, the step performing wet etching after the described FCVD technique of employing forms described first spacer material layer is also included in.
Alternatively, described first spacer material layer is identical with the material of described second spacer material layer.
Alternatively, described etching is dry etching.
Alternatively, adopt described FCVD technique form described first spacer material layer after also comprise the step of the first spacer material layer described in densification.
Alternatively, what described densification adopted is thermal annealing.
Alternatively, described semiconductor device is flash memory.
Alternatively, the depth-to-width ratio of shallow trench is more than or equal to 10:1.
Alternatively, after filling described first spacer material layer, the depth-to-width ratio of remaining described shallow trench is less than or equal to 5:1.
The embodiment of the present invention two proposes a kind of semiconductor device adopting above-mentioned method to manufacture.
The embodiment of the present invention three proposes a kind of electronic installation, and it comprises semiconductor device as above.
In sum, manufacture method according to the present invention does not have the formation in cavity in the STI of GOX (gate insulating film) lower zone, avoids the electric leakage between wordline and wordline; The sti structure be positioned at below GOX is conformality, avoids control gate too short to the distance of active area; HARP can not fill the fleet plough groove isolation structure that depth-to-width ratio is 10:1, but can fill the fleet plough groove isolation structure that depth-to-width ratio is 5:1.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
The structural representation of the device that Figure 1A-1C obtains for the correlation step making nand flash memory sti structure according to one embodiment of the present invention;
Fig. 2 is the process chart making nand flash memory sti structure according to one embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it will be apparent to one skilled in the art that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to illustrate how the present invention solves the problems of the prior art.Detailed being described below of obvious preferred embodiment of the present invention, but remove outside these detailed descriptions, the present invention can also have other execution modes.
Should give it is noted that term used here is only to describe specific embodiment, and be not intended to restricted root according to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative be also intended to comprise plural form.In addition, it is to be further understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention.But these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.Should be understood that, providing these embodiments to be of the present inventionly disclose thorough and complete to make, and the design of these exemplary embodiments fully being conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, exaggerate the thickness in layer and region, and use the element that identical Reference numeral represents identical, thus will omit description of them.
Embodiment one
Be described in detail the manufacture method of embedded flash memory memory of the present invention below in conjunction with Figure 1A-1C, Figure 1A-1C is the structural section figure made according to one embodiment of present invention in the process of nand flash memory sti structure.
As shown in Figure 1A, provide Semiconductor substrate 100, in the substrate 100 of described semiconductor, be formed with trap and active area.
Described Semiconductor substrate can be at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.Exemplarily, in the present embodiment, the constituent material of Semiconductor substrate selects monocrystalline silicon.
There is provided the bulk silicon substrate 100 that includes source region, form cushion oxide layer 101 on a semiconductor substrate 100, its main material is silicon dioxide.This pad oxide is formed by thermal oxidation method, and general thickness is 30 ~ 200 dusts, and it is not subject to chemical spot (as isolating oxide layer) to protect active area when removing silicon nitride mainly as separator.Pad oxide 101 is formed pad nitride layer 102; the preferred silicon nitride layer of material of nitride layer 102; boiler tube deposition process or Low Pressure Chemical Vapor Deposition can be adopted to form pad nitride layer; its thickness is generally 500 ~ 2000 dusts; this pad nitride layer 102 is mainly used in protecting active area in deposition oxide process in fleet plough groove isolation structure, and can be used as the barrier material of grinding when the silica that cmp is filled.
Exemplarily, pad nitride layer 102 forms dielectric anti-reflective coating (DARC), its material is silicon oxynitride, the method that chemical gas can be adopted to deposit prepares dielectric anti-reflective coating, the object of deposition formation dielectric anti-reflective coating is the reflectivity in order to reduce silicon nitride layer, dielectric anti-reflective coating forms photoresist layer, adopts photoetching process, after the steps such as exposure imaging, form the photoresist layer of patterning.
In a specific embodiment of the present invention, the method for definition shallow trench 103 is: at semiconductor substrate surface coating photoresist, expose and develop, by predefined graph transfer printing on photoresist to photoresist.According to photoresist layer etching dielectrics antireflecting coating, pad nitride layer 102, the pad oxide 101 successively of patterning.Wherein, etching gas can adopt the gas based on chlorine or the gas based on hydrogen bromide or both mists.Adopt dry etch process, dry method etch technology includes but not limited to: reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting.Dry etching is carried out preferably by one or more RIE step.The range of flow of etching gas can be 0 ~ 200 cc/min (sccm), and reative cell internal pressure can be 5 ~ 20 millis millimetres of mercury (mTorr).Then, photoresist, the dielectric anti-reflective coating of patterning is removed, to form opening in pad nitride layer 102 and pad oxide skin(coating) 101.Then, then main etching is carried out, to form shallow trench 103.Concrete, according to the described opening etched portions Semiconductor substrate 100 in pad nitride layer 102 and pad oxide skin(coating) 101, to form shallow trench 103.The etching agent of usual employing is fluorine-containing gas, such as CF
4or CHF
3.Dry etching can be adopted, such as the combination in any of reactive ion etching, ion beam etching, plasma etching, laser ablation or these methods.Single lithographic method can be used, or also can use more than one lithographic method.Etching gas comprises HBr, Cl
2, CH
2f
2, O
2one or several gases, and some add gases as nitrogen, argon gas.The range of flow of described etching gas can be 0 ~ 150 cc/min (sccm), and reative cell internal pressure can be 3 ~ 50 millitorrs (mTorr), is to carry out plasma etching under the condition of 600W ~ 1500W at radio-frequency power.
Exemplarily, the depth-to-width ratio of described shallow trench 103 is more than or equal to 10:1.
Then, as shown in Figure 1B, carry out the filling of groove 103, at the underfill spacer material layer 104 of described shallow trench 103, the material of spacer material layer 104 can be silicon dioxide.
Adopt the bottom of FCVD process filling shallow trench 103, it is that the shallow trench of 10:1 is to avoid wordline to the inefficacy of wordline that FCVD technique can fill depth-to-width ratio.Can crack be produced when adopting the horizontal ratio of HARP process filling to be the shallow trench of 10:1 thus cause wordline to the generation of word line leakage.
The step of the first spacer material layer described in densification is also comprised after the described FCVD technique of employing forms described spacer material layer 104.Described densification is exactly that the steam in FCVD is removed by a kind of heat treatment.
Exemplarily, what described densification adopted is thermal annealing.
Exemplarily, the top of spacer material layer 104 adopting FCVD technique to be formed and the top of Semiconductor substrate flush.
Alternatively, after spacer material layer 104 is formed on the bottom performing FCVD process filling shallow trench 103, wet-etching technology is performed.
In the shallow trench filling process with high-aspect-ratio, the film that FCVD technique is formed can not densification completely, the formation of protrusion (protrusion) is had when adding wet-etching technology, these protrusions will cause control gate shorter to active area distance, and impact programming and sassafras are except performance.Wet-etch rate " incomplete densification " in FCVD technique is different from " densification " in FCVD technique.
Exemplarily, in the spacer material layer 104 adopting FCVD process deposits to be formed, there is no cavity, be equivalent to, in the FCVD film formed in GOX lower zone, there is no cavity.
It should be noted that, adopt FCVD technique to form spacer material layer and know for a person skilled in the art, be not just described in detail at this, FCVD technique well known to those skilled in the art can be adopted to form spacer material layer.
Exemplarily, after filling described spacer material layer 104, the depth-to-width ratio of remaining described shallow trench is less than or equal to 5:1.
Then, as shown in Figure 1 C, carry out the filling at shallow trench 103 top, on spacer material layer 104 in shallow trench 103 and pad silicon nitride layer 102 on depositing isolation material layer 105, the material of spacer material layer 105 can be silicon dioxide.
Adopt HARP technique in shallow trench 103 and pad silicon nitride layer 102 forms spacer material layer 105, the top of spacer material layer 105 filling groove 103, and spacer material layer 105 covers spacer material layer 104.
In a specific embodiment of the present invention, HDP (high-density plasma) depositing operation is adopted to form spacer material layer in described shallow trench and on nitride layer, the material of spacer material layer is preferably silicon dioxide, HDP-CVD (high density plasma chemical vapor deposition) is adopted to form oxide skin(coating), HDP-CVD technique synchronously carries out depositing in same reaction chamber and sputter reacting, and the reacting gas that HDP-CVD technique adopts comprises SiH
4and O
2, and sputtering gas hydrogen and helium.Because deposition and sputtering technology are carried out simultaneously, by adjustment SiH
4and O
2and the content of hydrogen and helium is to make sputtering sedimentation ratio for 1:1.
It should be noted that, the method for above-mentioned formation spacer material layer is exemplary, is not limited to described method, as long as this area additive method can realize described object, all can be applied to the present invention, not repeat them here.
Exemplarily, when active area depth-to-width ratio is only 5:1 below GOX, HARP technique is adopted to perform filling.
Carry out planarization to the spacer material layer 105 of Semiconductor substrate, the surface of described spacer material layer 105 is concordant, concrete with the surface of described pad silicon nitride layer 102, adopts cmp to perform flatening process.
Exemplarily, the present invention first adopts FCVD depositing operation to adopt HARP depositing operation to form STI again, and sti structure formed according to the present invention can obtain good electrical property.
Exemplarily, the densification that the thin layer adopting FCVD to be formed according to the inventive method can be good and without empty gap-fill, thus stop the electric leakage between wordline to wordline.
Exemplarily, the film layer structure that adopts HARP technique to be formed is general character, thus control gate can be avoided shorter to the distance of active area.
With reference to Fig. 2, illustrated therein is the process chart into making nand flash memory sti structure according to one embodiment of the present invention.For schematically illustrating the flow process of whole manufacturing process.
In step 201, provide Semiconductor substrate, be formed with pad oxide skin(coating) and pad nitride layer on the semiconductor substrate, form shallow trench on the semiconductor substrate;
In step 202., adopt the bottom of shallow trench described in FCVD process filling, flush to make described first spacer material layer and Semiconductor substrate;
In step 203, the top of shallow trench described in HARP process filling is adopted, to form the second spacer material layer on described first spacer material layer.
In sum, manufacture method according to the present invention does not have the formation in cavity to avoid electric leakage between wordline and wordline in the STI of GOX lower zone; The sti structure be positioned at below GOX is conformality, to avoid control gate shorter to the distance of active area; HARP can not fill the fleet plough groove isolation structure that depth-to-width ratio is 10:1, but can fill the fleet plough groove isolation structure that depth-to-width ratio is 5:1.
Embodiment two
Manufacture method according to the present invention also proposed a kind of semiconductor device, the semiconductor device that the manufacture method that described semiconductor device is the semiconductor device according to embodiment one manufactures.
Embodiment three
The embodiment of the present invention provides a kind of electronic installation, and it comprises semiconductor device.Wherein, the semiconductor device described in embodiment semiconductor device two, or the semiconductor device that the manufacture method of semiconductor device according to embodiment one manufactures.
The electronic installation of the present embodiment, can be mobile phone, panel computer, notebook computer, net book, game machine, television set, VCD, DVD, navigator, camera, video camera, recording pen, any electronic product such as MP3, MP4, PSP or equipment, also can be any intermediate products comprising semiconductor device.The electronic installation of the embodiment of the present invention, owing to employing above-mentioned semiconductor device, thus has better performance.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to the present invention, within these variants and modifications all drop on the present invention's scope required for protection.
Claims (11)
1. a manufacture method for semiconductor device, comprising:
Semiconductor substrate is provided,
Be formed with pad oxide and pad nitride layer on the semiconductor substrate successively;
Etch the described Semiconductor substrate of described pad nitride layer, described pad oxide and part, to form shallow trench;
FCVD technique is adopted to form the first spacer material layer in the bottom of described shallow trench;
Adopt the remaining described shallow trench of HARP process filling to form the second spacer material layer, described second spacer material layer is positioned on described first spacer material layer;
Perform flatening process.
2. the method for claim 1, is characterized in that, is also included in the step performing wet etching after the described FCVD technique of employing forms described first spacer material layer.
3. the method for claim 1, is characterized in that, described first spacer material layer is identical with the material of described second spacer material layer.
4. the method for claim 1, is characterized in that, described etching is dry etching.
5. the method for claim 1, is characterized in that, adopt described FCVD technique form described first spacer material layer after also comprise the step of the first spacer material layer described in densification.
6. method as claimed in claim 5, is characterized in that, what described densification adopted is thermal annealing.
7. the method for claim 1, is characterized in that, described semiconductor device is flash memory.
8. the method for claim 1, is characterized in that, the depth-to-width ratio of shallow trench is more than or equal to 10:1.
9. the method for claim 1, is characterized in that, after filling described first spacer material layer, the depth-to-width ratio of remaining described shallow trench is less than or equal to 5:1.
10. the semiconductor device of the method manufacture adopting one of claim 1-9 described.
11. 1 kinds of electronic installations, is characterized in that, comprise arbitrary described semiconductor device in claim 10.
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| CN201410325581.6A CN105448920A (en) | 2014-07-09 | 2014-07-09 | Semiconductor device and manufacturing method thereof and electronic device |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110049669A1 (en) * | 2009-09-02 | 2011-03-03 | Lee Yu-Jin | Method for forming isolation layer of semiconductor device |
| CN103794543A (en) * | 2012-10-31 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Isolation structure and formation method thereof |
| CN103907182A (en) * | 2011-09-26 | 2014-07-02 | 应用材料公司 | Improved intrench profile |
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- 2014-07-09 CN CN201410325581.6A patent/CN105448920A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110049669A1 (en) * | 2009-09-02 | 2011-03-03 | Lee Yu-Jin | Method for forming isolation layer of semiconductor device |
| CN103907182A (en) * | 2011-09-26 | 2014-07-02 | 应用材料公司 | Improved intrench profile |
| CN103794543A (en) * | 2012-10-31 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Isolation structure and formation method thereof |
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Application publication date: 20160330 |