CN105448810A - Interconnection structure forming method - Google Patents
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- CN105448810A CN105448810A CN201410294750.4A CN201410294750A CN105448810A CN 105448810 A CN105448810 A CN 105448810A CN 201410294750 A CN201410294750 A CN 201410294750A CN 105448810 A CN105448810 A CN 105448810A
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Abstract
The invention discloses an interconnection structure forming method, and the method comprises the steps: providing a substrate which comprises a lower dielectric layer and a lower metal conductive structure located in the lower dielectric layer, wherein the top surface of the lower metal conductive structure is aligned with the surface of the lower dielectric layer; forming a top blocking layer on the surfaces of the lower dielectric layer and the lower metal conductive structure; carrying out the ultraviolet curing of the top blocking layer; forming a top dielectric layer on the surface of the top blocking layer; and forming a top metal conductive structure in the top dielectric layer, wherein the surface of the top metal conductive structure is aligned with the surface of the top dielectric layer. The method can improve the reliability of a formed interconnection structure.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of formation method of interconnection structure.
Background technology
In existing semiconductor applications, semiconductor circuit has developed into the integrated circuit (integratedcircuit, IC) with multilayer interconnection.In the IC of multilayer interconnection, interconnection structure comprises the interlayer dielectric layer of multiple-level stack, has metallic conduction structure in described interlayer dielectric layer, and the conductive structure in adjacent interlayer dielectric layer is electrically connected to each other.Isolated by dielectric layer between metallic conduction structure, so can parasitic capacitance be formed between metallic conduction structure.Because the speed of IC and parasitic capacitance are inversely proportional to, so need to reduce described parasitic capacitance to improve the performance of IC.
At present, low-K dielectric material has substituted the dielectric material of traditional silica as interlayer dielectric layer, but along with improving constantly requirement on devices, further propose the use K value ultralow K dielectric material lower than low-K dielectric material to reduce the parasitic capacitance of device further, wherein, the K value of ultra-low K dielectric layer material is usually below 2.7.But ultralow K dielectric material mostly is porous material, and mechanical strength is more weak, easily sustains damage under effect of stress, in heat treatment or plasma treatment procedure and be out of shape.
At present, in prior art, interconnection structure comprises lower metal conductive structure and top-level metallic conductive structure, lower metal conductive structure is for the formation of circuit structure, connect levels device etc., larger for device performance impact, so, the interlayer dielectric layer being formed with lower metal conductive structure is generally ultralow K dielectric material, the parasitic capacitance between lower metal conductive structure can be reduced, and top layer metallic layer is generally used for the metal of protection lower floor and the contact jaw as outwards connection, insensitive to parasitic capacitance, so, the top layer dielectric layer at described top layer metallic layer place generally adopts silica material, do not need to adopt ultra low-K material again.
Interlayer dielectric layer below top-level metallic conductive structure is generally sandwich construction, is formed with barrier layer between adjacent interlayer dielectric layer, and the lower metal conductive structure electrical connection in adjacent interlayer dielectric layer.In the interconnection structure that prior art is formed, the dielectric breakdown voltage of top-level metallic conductive structure adjacent layer is lower, affects the reliability of interconnection structure.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of interconnection structure, improves the reliability of interconnection structure.
For the technical scheme of the present invention that solves the problem provides a kind of formation method of interconnection structure, comprise: substrate is provided, described substrate comprises underlying dielectric layers and is positioned at the lower metal conductive structure of described underlying dielectric layers, and the described top surface of lower metal conductive structure flushes with the surface of underlying dielectric layers; Capping barrier layer is formed at described underlying dielectric layers and lower metal conductive structure surfaces; Ultra-violet curing process is carried out to described Capping barrier layer; Top layer dielectric layer is formed on described Capping barrier layer surface; In described top layer dielectric layer, form top-level metallic conductive structure, described top-level metallic conductive structure surfaces flushes with top layer dielectric layer surface.
Optionally, described ultra-violet curing process is carried out under atmosphere of inert gases, carries out ultraviolet irradiation to described Capping barrier layer.
Optionally, the time of the ultraviolet irradiation of described ultra-violet curing process is 180s ~ 300s, and temperature is 300 DEG C ~ 500 DEG C.
Optionally, described ultraviolet wavelength is 100nm ~ 400nm, and described ultraviolet is continuous ultraviolet or pulsed ultraviolet.
Optionally, the material of described Capping barrier layer is carbonitride of silicium or silicon nitride.
Optionally, the thickness of described Capping barrier layer is
Optionally, the dielectric coefficient of described top layer dielectric layer is greater than the dielectric coefficient of underlying dielectric layers.
Optionally, the material of described top layer dielectric layer is silica, and using plasma strengthens chemical vapor deposition method and forms described top layer dielectric layer.
Optionally, the dielectric coefficient of described underlying dielectric layers is equal to or less than 2.55.
Optionally, the material of described underlying dielectric layers comprises SiCOH, porous silica or fluorine-doped silica.
Optionally, the formation method of described underlying dielectric layers comprises: spin coating proceeding, plasma enhanced chemical vapor deposition technique or inductively coupled plasma chemical vapor deposition method.
Optionally, described underlying dielectric layers comprises first medium layer and is positioned at the second dielectric layer above described first medium layer.
Optionally, between described first medium layer and second dielectric layer, there is Lower blocking layer.
Optionally, the material of described Lower blocking layer is carbonitride of silicium or silicon nitride.
Optionally, the thickness of described Lower blocking layer is
Optionally, also comprise: process is cured to described second dielectric layer.
Optionally, described solidification process is carried out in an inert atmosphere, and carry out ultraviolet irradiation to described second dielectric layer, the time is 120s ~ 240s, and temperature is 300 DEG C ~ 500 DEG C.
Optionally, described ultraviolet wavelength is 100nm ~ 400nm, and described ultraviolet is continuous ultraviolet or pulsed ultraviolet.
Optionally, while process is cured to described second dielectric layer, process is cured to Lower blocking layer.
Optionally, the method forming described top-level metallic conductive structure comprises: on described top layer dielectric layer, form the mask layer with opening, with described mask layer for top layer dielectric layer and Capping barrier layer described in mask etching, form groove, expose the surface of section bottom metallic conduction structure; In described groove, fill metal level, form top-level metallic conductive structure.
Compared with prior art, technical scheme of the present invention has the following advantages:
Technical scheme of the present invention, after formation Capping barrier layer, carries out ultra-violet curing process to described Capping barrier layer.By Capping barrier layer described in ultraviolet irradiation, the material in described Capping barrier layer is made to absorb ultraviolet energy, because ultraviolet energy is higher, the chemical bond that in barrier layer, combination can be lower can be made to disconnect, again the chemical bond that combination can be higher is formed, and active end group or group can formed on the surface of Capping barrier layer, described active end group or group can and underlying dielectric layers surface to form the chemical bond having and combine comparatively by force energy between the atom on lower floor's metallic conduction structure surface, thus improve described underlying dielectric layers, interface quality between lower metal conductive structure and described Capping barrier layer, avoid the metallic atom of top-level metallic conductive structure from Capping barrier layer and underlying dielectric layers, occur in gap between lower metal conductive structure move and diffuse in described underlying dielectric layers, thus the dielectric breakdown voltage that can improve between lower metal conductive structure, thus improve the reliability of interconnection structure.
Further, described ultra-violet curing process is carried out under atmosphere of inert gases, and described inert gas has lower reactivity, and can avoid in the process of carrying out ultra-violet curing, the character of Capping barrier layer reacts.
Further, the time of the ultraviolet irradiation of described ultra-violet curing process is 180s ~ 300s, and temperature is 300 DEG C ~ 500 DEG C.The time long enough of described ultraviolet irradiation, the material of described Capping barrier layer is made can fully to absorb ultraviolet energy, the chemical bond that in Capping barrier layer, combination can be lower is disconnected, again the chemical bond that combination can be higher is formed, form enough active end groups or group on the surface of Capping barrier layer, thus make described formation dielectric layer, interface quality between lower metal conductive structure and described Capping barrier layer effectively improves.Described ultra-violet curing treatment temperature remains within the scope of 300 DEG C ~ 500 DEG C, avoids the too high material to Capping barrier layer of temperature to damage, and avoids again chemical bond energy in the too low Capping barrier layer of temperature lower, not easily forms active cardinal extremity or group.
Accompanying drawing explanation
Fig. 1 to Figure 10 is the structural representation of the forming process of the interconnection structure of embodiments of the invention.
Embodiment
As described in the background art, the puncture voltage of the interlayer dielectric layer adjacent with top-level metallic conductive structure place layer is lower, and the reliability of described interconnection structure need further raising.
Research finds, generally Capping barrier layer is formed with between top-level metallic conductive structure place layer and the interlayer dielectric layer below it, and the Capping barrier layer that prior art is formed and interlayer dielectric layer, interface quality between lower metal conductive structure are poor, after voltage is applied to metallic conduction structure, metallic atom in described lower metal conductive structure can be migrated in interlayer dielectric layer by the gap between Capping barrier layer and interlayer dielectric layer, lower metal conductive structure, and causes dielectric breakdown.And and the interface quality of barrier layer between the some stacking lower floor's interlayer dielectric layer below this top-level metallic conductive structure place layer and adjacent interlayer dielectric layer and lower floor's interlayer dielectric layer higher, so the puncture voltage of lower floor's interlayer dielectric layer is higher.
Further research finds, because the mechanical strength of ultralow K dielectric material is lower, deformation easily occurs or sustains damage, in order to improve the intensity of ultralow K dielectric material, process can be cured, such as ultra-violet curing process, to strengthen the intensity of low-K dielectric material to low-K dielectric material.Because described low-K dielectric material is generally transparent material, low-K dielectric material is being carried out in the process of ultra-violet curing process, ultraviolet light can be cured process through described low-K dielectric material to the barrier layer below it simultaneously, thus the interface quality between described barrier layer and adjacent metal conductive structure and dielectric layer is improved.And due to the dielectric layer material at top-level metallic conductive structure place be not ultralow K dielectric material, generally can not carry out ultra-violet curing process to it, so Capping barrier layer below top-level metallic conductive structure and interlayer dielectric layer, interface quality between lower metal conductive structure are poor, thus the dielectric breakdown voltage of the interlayer dielectric layer adjacent with top-level metallic conductive structure place layer is caused to decline.
In order to solve the problem, embodiments of the invention are after formation Capping barrier layer, ultra-violet curing process is carried out to described Capping barrier layer, to improve the interface quality between described Capping barrier layer and lower metal conductive structure, underlying dielectric layers, thus improve the dielectric breakdown voltage being positioned at the dielectric layer of Capping barrier layer lower surface.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Please refer to Fig. 1, provide substrate, described substrate comprises first medium layer 100 and is positioned at the first lower metal conductive structure 101 of described first medium layer 100, and the top surface of described first lower metal conductive structure 101 flushes with the surface of first medium layer 100.
Described substrate can also comprise the device layer be positioned at below first medium layer 100, the semiconductor device that described device layer comprises Semiconductor substrate and formed on a semiconductor substrate.Described first lower metal conductive structure 101 is connected to form circuit structure with the semiconductor device in device layer.
In the present embodiment, described substrate comprises first medium layer 100 and is positioned at the first lower metal conductive structure 101 of described first medium layer 100.Described first lower metal conductive structure can comprise metal plug connected vertically with semiconductor device and be positioned at interconnection line metal plug being connected multiple metal plug, and different semiconductor device is connected into circuit structure by interconnection line.
In other embodiments of the invention, described substrate can comprise the first medium layer 100 of multiple-level stack, is electrically connected, can also has barrier layer between adjacent first medium layer 100 between the first lower metal conductive structure 101 in adjacent first medium layer 100.
The material of described first medium layer 100 is low-K dielectric material or ultralow K dielectric material.The dielectric coefficient of described first medium layer 100 can be less than or equal to 2.55, contributes to the parasitic capacitance between reduction by first lower metal conductive structure 101, improves the operating efficiency of semiconductor device.
The material of described first medium layer 100 comprises the dielectric materials such as SiCOH, porous silica or fluorine-doped silica.Described first medium layer 100 can adopt spin coating proceeding, plasma enhanced chemical vapor deposition technique or inductively coupled plasma chemical vapor deposition method to be formed.In the present embodiment, the material of described first medium layer 100 is SiCOH, adopts spin coating proceeding to form described first medium layer 100.
The material of described first lower metal conductive structure 101 can be the conductive metal material such as copper, aluminium or tungsten.In other embodiments of the invention, also diffusion impervious layer is formed with between described first lower metal conductive structure 101 and first medium layer 100, the material of described diffusion impervious layer can be the metal materials such as Ti, TiN, Ta, TaN, for stopping that the metallic atom in the first lower metal conductive structure 101 diffuses in first medium layer 100.
Please refer to Fig. 2, form Lower blocking layer 102 at described first medium layer 100 and the first lower metal conductive structure 101 surface.
The material of described Lower blocking layer 102 is comparatively fine and close dielectric material, can be SiCN or SiN etc.In the present embodiment, the material of described Lower blocking layer 102 is SiCN.The thickness of described Lower blocking layer 102 is
chemical vapor deposition method or atom layer deposition process etc. can be adopted to form described Lower blocking layer 102.
Follow-up in described Lower blocking layer 102 surface formation second dielectric layer, in described second dielectric layer, form groove, then in described groove, form the second lower metal conductive structure.Described Lower blocking layer 102 can be formed in the process of groove in etching second dielectric layer; as etching stop layer; protect the top surface of the first lower metal conductive structure 101, and can stop that the metallic atom of the first lower metal conductive structure 101 upwards diffuses in second dielectric layer.
Please refer to Fig. 3, form second dielectric layer 200 on described Lower blocking layer 102 surface.
The material of described second dielectric layer 200 is low-K dielectric material or ultralow K dielectric material.The dielectric coefficient of described second dielectric layer 200 can be less than or equal to 2.55, contributes to reducing the parasitic capacitance between follow-up the second lower metal conductive structure formed in described second dielectric layer 200, improves the operating efficiency of semiconductor device.The material of described second dielectric layer 200 comprises the dielectric materials such as SiCOH, porous silica or fluorine-doped silica.Described second dielectric layer 200 can adopt spin coating proceeding, plasma enhanced chemical vapor deposition technique or inductively coupled plasma chemical vapor deposition method to be formed.
In the present embodiment, the material of described second dielectric layer 200 is all SiCOH mutually with the material of first medium layer 100, and the dielectric coefficient of described second dielectric layer 200 is 2.55, and spin coating proceeding can be adopted to form described second dielectric layer 200.Described spin coating proceeding can adopt the alcoholic solution of tetraethoxysilance to toast after the surperficial spin-coating film of Lower blocking layer 102, forms described second dielectric layer 200.
In other embodiments of the invention, also using plasma enhancing chemical vapor deposition method can form described second dielectric layer 200, the reacting gas that described plasma enhanced chemical vapor deposition technique adopts can comprise decamethylcyclopentaandoxane (DMCPS) and fluoroform (CHF
3).
In other embodiments of the invention, also directly can form described second dielectric layer 200 on described first medium layer 100 surface, and not form described Lower blocking layer 102.
Please refer to Fig. 4, process is cured to described second dielectric layer 200.
Because the material of described second dielectric layer 200 has lower dielectric coefficient, be porous material, the mechanical strength of material is poor, easily deforms.In the present embodiment, process is cured to described second dielectric layer 200, to improve the mechanical performance of described second dielectric layer 200, avoids described second dielectric layer 200 in follow-up problem of entering to deform etc. in shape etching or chemical mechanical planarization process.
In the present embodiment, the solidification of employing is treated to ultra-violet curing process, and the mechanical strength of described second dielectric layer 200 is improved.Concrete, described solidification process is carried out under atmosphere of inert gases, carries out ultraviolet irradiation to described second dielectric layer 200.In described solidification processing procedure, the time of ultraviolet irradiation is 120s ~ 240s, and temperature is 300 DEG C ~ 500 DEG C, and described ultraviolet wavelength is 100nm ~ 400nm, can be continuous ultraviolet or pulsed ultraviolet.
Because ultraviolet frequency is higher, there is higher energy, carrying out in the process of ultraviolet irradiation to described second dielectric layer 200, the material of described second dielectric layer 200 can absorb ultraviolet energy, the energy of ultraviolet irradiation can make the chemical bond that in the material of second dielectric layer 200, combination can be more weak that the active end group of fracture generation or group occur, the structure of these instability active structure that is easy and surrounding is recombinated at this, form rock-steady structure, chemical bonds in described second dielectric layer 200 material can be strengthened, such as C-C key increases, the crosslink density of Si-O-Si skeleton and rigidity reinforced, thus the density of second dielectric layer 200 and mechanical strength are strengthened.And, described solidification process can by forming microcellular structure in the material of second dielectric layer 200, the dielectric coefficient of the described second dielectric layer 200 of further reduction, thus improve the insulation property of described second dielectric layer 200 further, and then reduce the parasitic capacitance of the interconnection structure formed further.The thickness of described second dielectric layer 200 is about large, in described solidification processing procedure, the time of ultraviolet irradiation is longer, and temperature is higher, to make the material of described second dielectric layer 200 fully can absorb ultraviolet energy, the mechanical strength of second dielectric layer 200 is fully enhanced.
Further, the solidification process adopted in the present embodiment have technique simple, to advantages such as second dielectric layer 200 surface damage are less.In other embodiments of the invention, the methods such as Microwave Treatment also can be adopted to be cured process to described second dielectric layer 200.
Be cured in the process of process to described second dielectric layer 200, material due to described second dielectric layer 200 is transparent material, ultraviolet in described solidification processing procedure can also penetrate described second dielectric layer 200, be radiated to described Lower blocking layer 102, while process is cured to second dielectric layer 200, process is cured to described Lower blocking layer 102.
Under the effect of ultraviolet irradiation, the material of described Lower blocking layer 102 absorbs ultraviolet energy, formation has the chemical bond of higher combination energy and can form active end group or group on described Lower blocking layer 102 surface, and form the chemical bond having and combine comparatively by force energy between first medium layer 100 surface and the first lower metal conductive structure 101 surface atom, thus improve described first medium layer 100, interface quality between first lower metal conductive structure 101 and described Lower blocking layer 102, the first lower metal conductive structure 101 can be avoided at Lower blocking layer 102 and first medium layer 100, diffusion and migration is there is in gap between first lower metal conductive structure 101 interface, thus the dielectric breakdown voltage that can improve between the first lower metal conductive structure 101, improve the reliability of interconnection structure.
Please refer to Fig. 5, in described second dielectric layer 200, form groove 201.
The method forming described groove 201 comprises: form the mask layer with opening on second dielectric layer 200 surface, with described mask layer for second dielectric layer described in mask etching 200 and Lower blocking layer 102, form groove 201, described groove 201 exposes the surface of the first lower metal conductive structure 101.Follow-up in described groove 201 formed the second lower metal conductive structure, the lower surface of described second lower metal conductive structure is electrically connected with the top surface of the first lower metal conductive structure 101.
Concrete, in the present embodiment, described groove 201 comprises the through hole 201b exposing the first lower metal conductive structure 101 surface and the interconnected grooves 201a be positioned at above described through hole 201b.In the present embodiment, can form the first Patterned masking layer on second dielectric layer 200 surface, described first Patterned masking layer defines position and the size of through hole to be formed, with described first Patterned masking layer for mask, etch described second dielectric layer 200, form through hole 201b; Then described first Patterned masking layer is removed, second graphical mask layer is formed again on described second dielectric layer 200 surface, described second graphical mask layer defines position and the size of interconnected grooves to be formed, described second graphical mask layer exposes through hole 201b, and the A/F in described second graphical mask layer is greater than the width of through hole 201b; With described second graphical mask layer for second dielectric layer described in mask etching 200, formed and be positioned at above through hole 201b, and the interconnected grooves 201a through with described through hole 201b.Follow-uply in described through hole 201b, form metal plug, in interconnected grooves 201a, form interconnection line.
In other embodiments of the invention, Damascus technics can be adopted to form described groove 201.
Please refer to Fig. 6, the second lower metal conductive structure 202 is formed in described groove 201 (please refer to Fig. 5), described second lower metal conductive structure 202 is electrically connected with between the first lower metal conductive structure 101, and the top surface of described second lower metal conductive structure 202 flushes with second dielectric layer 200 surface.
The method forming described second lower metal conductive structure 202 comprises: in described groove 201, form metal material layer with second dielectric layer 200 surface, described metal material layer fills full described groove 201; Using described second dielectric layer 200 as stop-layer, adopt chemical mechanical milling tech, planarization is carried out to described metal material layer, form the second lower metal conductive structure 202 being positioned at described groove 201, the surface of described second lower metal conductive structure 202 flushes with the surface of second dielectric layer 200.Described second lower metal conductive structure 202 is connected with semiconductor device by described first lower metal structure 101, forms circuit.
Owing to carrying out overcuring process to described second dielectric layer 200, so the mechanical strength of described second dielectric layer 200 is larger, can not in above-mentioned chemical mechanical planarization process, deform problem, thus can make after the described second lower metal conductive structure 202 of formation, the surface of described second dielectric layer 200 is smooth.
In other embodiments of the invention, after described groove 201 inner wall surface forms diffusion impervious layer, more described top-level metallic conductive structure is formed.The material of described diffusion impervious layer can be the metal materials such as Ti, TiN, Ta, TaN, for stopping that the metallic atom horizontal proliferation in the second lower metal conductive structure 202 enters the dielectric coefficient improving described second dielectric layer 200 in second dielectric layer 200, avoid the insulation property affecting described second dielectric layer 200.
In the present embodiment, described first medium layer 100 and second dielectric layer 200 are as a part for underlying dielectric layers or underlying dielectric layers, and the first lower metal conductive structure 101, second lower metal conductive structure 202 is as a part for lower metal conductive structure or lower metal conductive structure; Described underlying dielectric layers and lower metal conductive structure form a part for substrate or substrate, follow-up at described substrate surface formation Capping barrier layer.
Please refer to Fig. 7, form Capping barrier layer 203 in described second dielectric layer 200 and the second lower metal conductive structure 202 surface.
The material of described Capping barrier layer 203 is comparatively fine and close dielectric material, can be SiCN or SiN etc.In the present embodiment, the material of described Capping barrier layer 203 is identical with the material of Lower blocking layer 102, is SiCN.The thickness of described Capping barrier layer 203 is
because the thickness of the follow-up top-level metallic conductive structure formed on described Capping barrier layer 203 is comparatively large, etch period is longer, so be greater than the thickness of Lower blocking layer 102 as the thickness of the Capping barrier layer 203 of etching barrier layer.Chemical vapor deposition method or atom layer deposition process etc. can be adopted to form described Capping barrier layer 203.
The decreasing insulating of second medium 200 and top layer dielectric layer is caused in the metallic atom that described Capping barrier layer 203 can stop in the second lower metal conductive structure 202 diffuses to second dielectric layer 200 and follow-up formation top layer dielectric layer from described second lower metal conductive structure 202 top surface.
Please refer to Fig. 8, ultra-violet curing process is carried out to described Capping barrier layer 203.
Described ultra-violet curing carries out under atmosphere of inert gases, carries out ultraviolet irradiation to described Capping barrier layer 203.
In described ultra-violet curing processing procedure, Capping barrier layer 203 absorbs ultraviolet energy, make in described Capping barrier layer 203, form the chemical bond with higher combination energy, the concentration of wherein carbon atom is improved, and the concentration of nitrogen-atoms declines, and form active end group or group on the surface of described Capping barrier layer 203, described active end group or group can and the atom on second dielectric layer 200 surface and the second lower metal conductive structure 202 surface between forms the chemical bond having and combine comparatively by force energy, thus improve described second dielectric layer 200, interface quality between second lower metal conductive structure 202 and described Capping barrier layer 203, make described Capping barrier layer 203 and second dielectric layer 200, between second lower metal conductive structure 202, there is higher adhesiveness, avoid the metallic atom of the second lower metal conductive structure 202 from Capping barrier layer 203 and second dielectric layer 200, occur in gap between second lower metal conductive structure 202 move and diffuse in described second dielectric layer 200.
The time of described ultraviolet irradiation is 180s ~ 300s, and temperature is 300 DEG C ~ 500 DEG C.Described ultraviolet wavelength is 100nm ~ 400nm, is continuous print ultraviolet or pulsed ultraviolet.The time long enough of described ultraviolet irradiation, the material of described Capping barrier layer 203 is made can fully to absorb ultraviolet energy, the chemical bond that in described Capping barrier layer 203, combination can be lower is disconnected, again the chemical bond that combination can be higher is formed, form enough active end groups or group on the surface of Capping barrier layer 203, thus the interface quality between described second dielectric layer 200, second lower metal conductive structure 202 and described Capping barrier layer 203 is effectively improved.Described ultra-violet curing treatment temperature remains within the scope of 300 DEG C ~ 500 DEG C, avoids the too high material to Capping barrier layer 203 of temperature to damage, and avoids again chemical bond energy in the too low Capping barrier layer of temperature 203 lower, not easily forms active cardinal extremity or group.Thickness due to described Capping barrier layer 203 is greater than the thickness of Lower blocking layer 102, so the time of described ultra-violet curing process and temperature can be greater than time and the temperature of described solidification process.
Ultra-violet curing process is carried out to described Capping barrier layer 203, the metallic atom of the second lower metal conductive structure 202 can be avoided by the gap electromigration between Capping barrier layer 203 and second dielectric layer 200, second lower metal conductive structure 202 or diffuse in second dielectric layer 200, thus the dielectric breakdown voltage of the second dielectric layer 200 at described second lower metal conductive structure 202 place can be improved, and then improve the reliability of the final interconnection structure formed.
Please refer to Fig. 9, form top layer dielectric layer 300 on described Capping barrier layer 203 surface.
The material of described top layer dielectric layer 300 is silica, and the thickness of described top layer dielectric layer 300 is 18nm ~ 20nm.Using plasma enhancing chemical vapor deposition method can form described top layer dielectric layer 300.The reacting gas that described plasma enhanced chemical vapor deposition technique adopts is tetraethoxysilane (TEOS) and oxygen, argon gas is as gas carrier, reaction temperature is 150 DEG C ~ 350 DEG C, and the flow of argon gas is 20sccm ~ 200sccm, and oxygen flow is 20sccm ~ 200sccm.In other embodiments of the invention, SiH can also be adopted
4and H
2o, as reacting gas, forms described top layer dielectric layer 300.Follow-uply in described top layer dielectric layer 300, form top-level metallic conductive structure.
In the present embodiment, anti-reflecting layer 301 can also be formed on described top layer dielectric layer 300 surface.The material of described anti-reflecting layer 301 can be silicon oxynitride or silicon nitride; described anti-reflecting layer 301 carries out in the process of photoetching follow-up to described top layer dielectric layer 300 surface; improve the quality of photoetching, and the surface of described top layer dielectric layer 300 can be protected further.
Please refer to Figure 10, in described top layer dielectric layer 300, form top-level metallic conductive structure 302, described top-level metallic conductive structure surfaces flushes with top layer dielectric layer 300 surface.
The method forming described top-level metallic conductive structure 302 comprises: on described top layer dielectric layer 300, form the mask layer with opening, with described mask layer for top layer dielectric layer 300 described in mask etching and Capping barrier layer 203, form groove, expose the surface of part second lower metal conductive structure 202; Formed in described groove and fill full described groove and the metal material covering top layer dielectric layer 300, and carry out planarization to described metal material, form top-level metallic conductive structure 302, described top-level metallic conductive structure 302 flushes with top layer dielectric layer 300 surface.
In sum, after forming the second lower metal conductive structure 202 in second dielectric layer 200, form Capping barrier layer 203 on described second dielectric layer 200 surface and the second lower metal conductive structure 202 surface, and ultra-violet curing process is carried out to described Capping barrier layer 203.Material in described Capping barrier layer 203 absorbs ultraviolet energy, active end group or group is formed on the surface of Capping barrier layer 203, described active end group or group, can and the atom on second dielectric layer 200 surface and the second lower metal conductive structure 202 surface between forms the chemical bond having and combine comparatively by force energy, thus the interface quality improved between described second dielectric layer 200, second lower metal conductive structure 202 and described Capping barrier layer 203, improve the puncture voltage of described second dielectric layer 200, thus improve the reliability of interconnection structure.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. a formation method for interconnection structure, is characterized in that, comprising:
There is provided substrate, described substrate comprises underlying dielectric layers and is positioned at the lower metal conductive structure of described underlying dielectric layers, and the described top surface of lower metal conductive structure flushes with the surface of underlying dielectric layers;
Capping barrier layer is formed at described underlying dielectric layers and lower metal conductive structure surfaces;
Ultra-violet curing process is carried out to described Capping barrier layer;
Top layer dielectric layer is formed on described Capping barrier layer surface;
In described top layer dielectric layer, form top-level metallic conductive structure, described top-level metallic conductive structure surfaces flushes with top layer dielectric layer surface.
2. the formation method of interconnection structure according to claim 1, is characterized in that, described ultra-violet curing process is carried out under atmosphere of inert gases, carries out ultraviolet irradiation to described Capping barrier layer.
3. the formation method of interconnection structure according to claim 2, is characterized in that, the time of the ultraviolet irradiation of described ultra-violet curing process is 180s ~ 300s, and temperature is 300 DEG C ~ 500 DEG C.
4. the formation method of interconnection structure according to claim 3, is characterized in that, described ultraviolet wavelength is 100nm ~ 400nm, and described ultraviolet is continuous ultraviolet or pulsed ultraviolet.
5. the formation method of interconnection structure according to claim 1, is characterized in that, the material of described Capping barrier layer is carbonitride of silicium or silicon nitride.
6. the formation method of interconnection structure according to claim 1, is characterized in that, the thickness of described Capping barrier layer is
7. the formation method of interconnection structure according to claim 1, is characterized in that, the dielectric coefficient of described top layer dielectric layer is greater than the dielectric coefficient of underlying dielectric layers.
8. the formation method of interconnection structure according to claim 7, is characterized in that, the material of described top layer dielectric layer is silica, and using plasma strengthens chemical vapor deposition method and forms described top layer dielectric layer.
9. the formation method of interconnection structure according to claim 1, is characterized in that, the dielectric coefficient of described underlying dielectric layers is equal to or less than 2.55.
10. the formation method of interconnection structure according to claim 9, is characterized in that, the material of described underlying dielectric layers comprises SiCOH, porous silica or fluorine-doped silica.
The formation method of 11. interconnection structures according to claim 10, is characterized in that, the formation method of described underlying dielectric layers comprises: spin coating proceeding, plasma enhanced chemical vapor deposition technique or inductively coupled plasma chemical vapor deposition method.
The formation method of 12. interconnection structures according to claim 1, is characterized in that, described underlying dielectric layers comprises first medium layer and is positioned at the second dielectric layer above described first medium layer.
The formation method of 13. interconnection structures according to claim 12, is characterized in that, has Lower blocking layer between described first medium layer and second dielectric layer.
The formation method of 14. interconnection structures according to claim 13, is characterized in that, the material of described Lower blocking layer is carbonitride of silicium or silicon nitride.
The formation method of 15. interconnection structures according to claim 13, is characterized in that, the thickness of described Lower blocking layer is
The formation method of 16. interconnection structures according to claim 12, is characterized in that, also comprise: be cured process to described second dielectric layer.
The formation method of 17. interconnection structures according to claim 16, is characterized in that, described solidification process is carried out in an inert atmosphere, and carry out ultraviolet irradiation to described second dielectric layer, the time is 120s ~ 240s, and temperature is 300 DEG C ~ 500 DEG C.
The formation method of 18. interconnection structures according to claim 17, is characterized in that, described ultraviolet wavelength is 100nm ~ 400nm, and described ultraviolet is continuous ultraviolet or pulsed ultraviolet.
The formation method of 19. interconnection structures according to claim 17, is characterized in that, while being cured process to described second dielectric layer, is cured process to Lower blocking layer.
The formation method of 20. interconnection structures according to claim 1, it is characterized in that, the method forming described top-level metallic conductive structure comprises: on described top layer dielectric layer, form the mask layer with opening, with described mask layer for top layer dielectric layer and Capping barrier layer described in mask etching, form groove, expose the surface of section bottom metallic conduction structure; In described groove, fill metal level, form top-level metallic conductive structure.
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| US20110081776A1 (en) * | 2009-10-06 | 2011-04-07 | Kotaro Nomura | Method for manufacturing semiconductor device |
| CN102024790A (en) * | 2009-09-22 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device for interconnection process and manufacturing method thereof |
| US20120181694A1 (en) * | 2011-01-14 | 2012-07-19 | Renesas Electronics Corporation | Semiconductor device and manufacturing method thereof |
| CN103531527A (en) * | 2012-07-03 | 2014-01-22 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for metal interconnection structure |
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| CN102024790A (en) * | 2009-09-22 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device for interconnection process and manufacturing method thereof |
| US20110081776A1 (en) * | 2009-10-06 | 2011-04-07 | Kotaro Nomura | Method for manufacturing semiconductor device |
| US20120181694A1 (en) * | 2011-01-14 | 2012-07-19 | Renesas Electronics Corporation | Semiconductor device and manufacturing method thereof |
| CN103531527A (en) * | 2012-07-03 | 2014-01-22 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for metal interconnection structure |
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