CN105446701A - Data processing method, electronic device, and controller - Google Patents
Data processing method, electronic device, and controller Download PDFInfo
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- CN105446701A CN105446701A CN201510755573.XA CN201510755573A CN105446701A CN 105446701 A CN105446701 A CN 105446701A CN 201510755573 A CN201510755573 A CN 201510755573A CN 105446701 A CN105446701 A CN 105446701A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
Abstract
The present invention discloses a data processing method. The method comprises: receiving a data operation instruction; parsing the data operation instruction to obtain a first data operation address; based on the first data operation address and a data information table, determining a data operation policy; and reading corresponding data from a first data storage location or a second data storage location according to the determined data operation policy, wherein, the first data storage location differs from the second data storage location. The present invention also discloses an electronic device and a controller.
Description
Technical field
The present invention relates to data processing technique, particularly relate to a kind of data processing method, electronic equipment and controller.
Background technology
Solid state hard disc (SSD, SolidStateDrives) inner when reading the data in NANDflash, first data are read in register (register) from the unit of NAND inside (cell), and then by bus by digital independent to controller, but the utilization factor of data is not high in register, wherein partial data has often been left in the basket, so that when again carrying out digital independent, still need repetition to read from cell, the data reading performance using redundancy of such SSD is very low.
Summary of the invention
In view of this, the embodiment of the present invention is expected to provide a kind of data processing method, electronic equipment and controller, can improve data reading performance using redundancy, and realization is simple, cost is low.
For achieving the above object, the technical scheme of the embodiment of the present invention is achieved in that
Embodiments provide a kind of data processing method, described method comprises:
Receive data manipulation instruction;
Resolve described data manipulation instruction, obtain the first data manipulation address;
Based on described first data manipulation address and data message table determination data manipulation strategy;
Corresponding data is read from the first data storage location or the second data storage location according to established data operation strategy; Wherein, described first data storage location is different from described second data storage location.
In such scheme, describedly to comprise based on described first data manipulation address and data message table determination data manipulation strategy:
Described first data manipulation address is mated with the second data manipulation address stored in described data message table;
When the match is successful, determine that data manipulation strategy is for reading corresponding data from described second data storage location;
When it fails to match, determine that data manipulation strategy is for reading corresponding data from described first data storage location.
In such scheme, described first data storage location is positioned at the first data storage cell, and described second data storage location is positioned at the second data storage cell; Described first data storage cell comprises at least one first sub-storage unit, and described second data storage cell is used for the data that buffer memory reads from described first sub-storage unit.
In such scheme, described method also comprises:
Obtain at least one first data manipulation address that in the very first time, resolution data operational order obtains, record at least one first data manipulation address described is to form described data message table.
In such scheme, described according to established data operation strategy from after the first data storage location reads corresponding data, described method also comprises:
Described first data manipulation address is recorded to described data message table, and deletes data address invalid in described data message table.
In such scheme, described according to established data operation strategy from after the second data storage location reads corresponding data, described method also comprises:
Obtain the state data memory of described second data storage location;
Determine that the state data memory of described second data storage location is for empty, deletes the second data manipulation address of corresponding described first data manipulation address in described data message table.
The embodiment of the present invention additionally provides a kind of electronic equipment, and described electronic equipment comprises: controller, first memory and second memory;
Described controller, for receiving data manipulation instruction;
Resolve described data manipulation instruction, obtain the first data manipulation address;
Based on described first data manipulation address and data message table determination data manipulation strategy;
Corresponding data is read from first memory or second memory according to established data operation strategy.
In such scheme, described controller, specifically for mating described first data manipulation address with the second data manipulation address stored in described data message table;
When the match is successful, determine that data manipulation strategy is for reading corresponding data from described second memory;
When it fails to match, determine that data manipulation strategy is for reading corresponding data from described first memory.
In such scheme, described controller, also for obtaining at least one first data manipulation address that resolution data operational order in the very first time obtains, record at least one first data manipulation address described is to form described data message table.
In such scheme, described controller, specifically for described first data manipulation address is recorded to described data message table, and deletes data address invalid in described data message table.
In such scheme, described controller, specifically for obtaining the state data memory of described second memory;
Determine that the state data memory of described second memory is for empty, deletes the second data manipulation address of corresponding described first data manipulation address in described data message table.
The embodiment of the present invention additionally provides a kind of controller, and described controller comprises: receiver module, parsing module, determination module and processing module; Wherein,
Described receiver module, for receiving data manipulation instruction;
Described parsing module, for resolving described data manipulation instruction, obtains the first data manipulation address;
Described determination module, for based on described first data manipulation address and data message table determination data manipulation strategy;
Described processing module, for reading corresponding data according to established data operation strategy from the first data storage location or the second data storage location; Wherein, described first data storage location is different from described second data storage location.
The data processing method that the embodiment of the present invention provides, electronic equipment and controller, receive data manipulation instruction; Receive data manipulation instruction; Resolve described data manipulation instruction, obtain the first data manipulation address; Based on described first data manipulation address and data message table determination data manipulation strategy; Corresponding data is read from the first data storage location or the second data storage location according to established data operation strategy; Wherein, described first data storage location is different from described second data storage location.So, data can be read according to different data manipulation strategies from corresponding data storage location, improve data reading performance using redundancy, and realization is simple, cost is low.
Accompanying drawing explanation
Fig. 1 is the realization flow schematic diagram of the embodiment of the present invention one data processing method;
Fig. 2 is that embodiment of the present invention data message represents intention;
Fig. 3 is the realization flow schematic diagram of the embodiment of the present invention two data processing method;
Fig. 4 is embodiment of the present invention electronic equipment composition structural representation;
Fig. 5 is the invention process csr controller composition structural representation.
Embodiment
In embodiments of the present invention, data manipulation instruction is received; Receive data manipulation instruction; Resolve described data manipulation instruction, obtain the first data manipulation address; Based on described first data manipulation address and data message table determination data manipulation strategy; Corresponding data is read from the first data storage location or the second data storage location according to established data operation strategy; Wherein, described first data storage location is different from described second data storage location.
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Embodiment one
Figure 1 shows that the embodiment of the present invention one data processing method schematic flow sheet, be applied to an electronic equipment, as shown in Figure 1, embodiment of the present invention data processing method comprises:
Step 101: receive data manipulation instruction;
In embodiments of the present invention, described electronic equipment can be SSD, and described SSD comprises NAND flash controller and NANDflash; Described data manipulation instruction can be data reading instructions, is external control order, is used to indicate the data that NAND flash controller reads relevant position in described NANDflash; Described NAND flash controller one end connects on the system bus, and the other end is directly connected with NANDflash.
Step 102: resolve described data manipulation instruction, obtains the first data manipulation address;
Here, described first data manipulation address indicates the first data storage location;
When described electronic equipment is SSD, accordingly, described first data manipulation address can be the physical address of described NANDflash page (page), if the first data manipulation address can be Chip0Plane0Addr, indicate some concrete page in the Chip0Plane0 of described NANDflash; Chip0Plane1Addr, indicates the some concrete page of Plane1 in described Chip0.
In an inventive embodiments, described method also comprises:
Obtain at least one first data manipulation address that in the very first time, resolution data operational order obtains, record at least one first data manipulation address described is to form described data message table;
Here, the described very first time can for the historical time section preset, and described very first time size can set according to actual needs;
Described data message table is empty table at the beginning of establishment, when after resolution data operational order, when obtaining the first data manipulation address first, by the data manipulation address obtained record to form described data message table; Described data message represents that intention as shown in Figure 2.
Step 103: based on described first data manipulation address and data message table determination data manipulation strategy;
In embodiments of the present invention, described data message table stores the second data manipulation address; Accordingly, describedly to comprise based on described first data manipulation address and data message table determination data manipulation strategy:
Described first data manipulation address is mated with the second data manipulation address stored in described data message table by NAND flash controller;
When the match is successful, determine that data manipulation strategy is for reading corresponding data from the second data storage location;
When it fails to match, determine that data manipulation strategy is for reading corresponding data from the first data storage location.
Wherein, described first data storage location is different from described second data storage location; First data storage location is positioned at the first data storage cell, and described second data storage location is positioned at the second data storage cell; Described first data storage cell comprises at least one first sub-storage unit; Described second data storage cell and described first sub-storage unit are one-to-one relationship; Described second data storage cell is used for the data that buffer memory reads from described first sub-storage unit;
In embodiments of the present invention, described first data storage cell can be NANDflash; Accordingly, described first sub-storage unit is the plane in described NANDflash; Described second data storage cell can be register; Described register is data register (dataregister); Described register and described plane are one-to-one relationship; Described register is used for the data that buffer memory reads from described plane; Described second data manipulation address is the address of the last read operation of each plane of each chip in NANDflash, is also the physical address of the data stored in described register.
Namely described the match is successful there is the second data manipulation address identical with described first data manipulation address in described data message table, and the data that read, can from described second data storage location reading corresponding data at the second data storage cell;
In embodiments of the present invention, when the match is successful, showing that the data that will read have been stored in corresponding register, namely reading in NANDflash without the need to going, can directly go to read required data in corresponding register; As: if the first data manipulation address that the match is successful is Chip0Plane0Addr, can directly go to carry out digital independent in the register of corresponding described Plane0; So, improve each page data of reading from NANDflash in prior art to the data reading performance using redundancy of register, more because described register-bit is in NAND flash controller, do not increase extra internal memory, provide cost savings.
It is namely described that it fails to match there is not the second data manipulation address identical with described first data manipulation address in described data message table, corresponding data is read from described first data storage location, in embodiments of the present invention, namely from NANDflash, read corresponding data, namely perform data from NANDflash to register to the data read process of NAND flash controller.
Step 104: read corresponding data from the first data storage location or the second data storage location according to established data operation strategy.
In one embodiment, according to established data operation strategy from after the first data storage location reads corresponding data, described method also comprises:
Described first data manipulation address is recorded to described data message table, and deletes data address invalid in described data message table;
Here, described first data manipulation address is increased to described data message table, when next time reads the data of identical address, directly data can be read by register read operation.
The described invalid data address data that namely this address is corresponding do not exist in described second data storage cell, in embodiments of the present invention, if described register experienced by the operation write/wipe, then the address that in described register, data are corresponding just becomes invalid data address.
In one embodiment, described according to established data operation strategy from after the second data storage location reads corresponding data, described method also comprises:
Obtain the state data memory of described second data storage location;
Determine that the state data memory of described second data storage location is for empty, deletes the second data manipulation address of corresponding described first data manipulation address in described data message table;
Here, described state data memory comprises sky and non-NULL;
When described state data memory is empty, show that the data in described second data storage cell have been read, namely need to delete the address that the data that have been read described in data message table are corresponding, delete the second data manipulation address of corresponding described first data manipulation address in described data message table; When described state data memory is non-NULL, show that the data in described second data storage cell have not also been read, without the need to making any relevant treatment.
Embodiment two
Fig. 3 is the realization flow schematic diagram of the embodiment of the present invention two data processing method, is applied to an electronic equipment, and as shown in Figure 3, embodiment of the present invention data processing method comprises:
Step 301: receive data manipulation instruction;
In embodiments of the present invention, described electronic equipment can be SSD, and described SSD comprises NAND flash controller and NANDflash; Described data manipulation instruction can be data reading instructions, is external control order, is used to indicate the data that NAND flash controller reads relevant position in described NANDflash; Described NAND flash controller one end connects on the system bus, and the other end is directly connected with NANDflash.
In one embodiment, before this step, described method also comprises: create data message table; Described data message table is for storing the second data manipulation address; Described second data manipulation address is the address of the data that the second data storage cell stores.
Step 302: resolve described data manipulation instruction, obtains the first data manipulation address;
Here, described first data manipulation address indicates the first data storage location;
When described electronic equipment is SSD, accordingly, described first data manipulation address can be the physical address of described NANDflash page (page), if the first data manipulation address can be Chip0Plane0Addr, indicate some concrete page in the Chip0Plane0 of described NANDflash; Chip0Plane1Addr, indicates some concrete page in the Chip0Plane1 of described NANDflash.
Step 303: mated with the second data manipulation address stored in described data message table described first data manipulation address, it fails to match, performs step 304; The match is successful, performs step 306;
Here, described first data manipulation address is mated with the second data manipulation address stored in described data message table, namely search in described data message table and whether there is the address identical with described first data manipulation address, if exist, show that the data that will read are stored in the second data storage cell, be namely stored in register; If do not exist, namely it fails to match, shows not store the data that will read in the second data storage cell, and the first data storage cell need be gone to carry out digital independent.
Step 304: read corresponding data from the first data storage location;
Here, the first data storage location is positioned at the first data storage cell, and described first data storage cell comprises at least one first sub-storage unit; In embodiments of the present invention, described first data storage cell can be NANDflash; Accordingly, described first sub-storage unit is the plane in described NANDflash.
This step specifically comprises: according to described first data manipulation address, corresponding data is read out to corresponding register from described NANDflash, then read the data in described register.
Step 305: record described first data manipulation address to described data message table, and delete data address invalid in described data message table, perform step 308;
Here, described first data manipulation address is increased to described data message table, when next time reads the data of identical address, directly data can be read by register read operation.
The described invalid data address data that namely this address is corresponding do not exist in described second data storage cell, in embodiments of the present invention, if described register experienced by the operation write/wipe, then the address that in described register, data are corresponding just becomes invalid data address.
Step 306: read corresponding data from the second data storage location;
Here, described second data storage location is different from described first data storage location; Described second data storage location is positioned at the second data storage cell; Described second data storage cell and described first sub-storage unit are one-to-one relationship; Described second data storage cell is used for the data that buffer memory reads from described first sub-storage unit;
In embodiments of the present invention, described second data storage cell can be register; Described register is data register (dataregister); Described register and described plane are one-to-one relationship; Described register is used for the data that buffer memory reads from described plane; Described second data manipulation address is the address of the last read operation of each plane of each chip in NANDflash, is also the physical address of the data stored in described register.
In embodiments of the present invention, when the match is successful, described in show that the data that will read have been stored in corresponding register, namely reading in NANDflash without the need to going, can directly go to read required data in corresponding register; As: if the first data manipulation address that the match is successful is Chip0Plane0Addr, can directly go to carry out digital independent in the register of corresponding described Plane0; So, improve each page data of reading from NANDflash in prior art to the data reading performance using redundancy of register, more because described register-bit is in NAND flash controller, do not increase extra internal memory, provide cost savings.
Step 307: the state data memory obtaining described second data storage location, determines that the state data memory of described second data storage location is for empty, deletes the second data manipulation address of corresponding described first data manipulation address in described data message table;
Here, described state data memory comprises sky and non-NULL;
When described state data memory is empty, show that the data in described second data storage cell have been read, namely need to delete the address that the data that have been read described in data message table are corresponding, delete the second data manipulation address of corresponding described first data manipulation address in described data message table; When described state data memory is non-NULL, show that the data in described second data storage cell have not also been read, without the need to making any relevant treatment.
Step 308: terminate this treatment scheme.
Embodiment three
Fig. 4 is embodiment of the present invention electronic equipment composition structural representation, and as shown in Figure 4, embodiment of the present invention electronic equipment composition comprises: controller 41, first memory 42 and second memory 43; Described second memory 43 is positioned at described controller 41;
Described controller 41, for receiving data manipulation instruction;
Resolve described data manipulation instruction, obtain the first data manipulation address;
Based on described first data manipulation address and data message table determination data manipulation strategy;
Corresponding data is read from the first data storage location or the second data storage location according to established data operation strategy.
In one embodiment, described electronic equipment can be SSD, and described controller is NAND flash controller, and described first memory is NANDflash, and described second controller is register; Described data manipulation instruction can be data reading instructions, is used to indicate the data that NAND flash controller reads relevant position in described NANDflash.
In one embodiment, described first data manipulation address indicates the first data storage location; Described first data manipulation address can be the physical address of described NANDflash page (page); As: the first data manipulation address can be Chip0Plane0Addr, indicates some concrete page in the Chip0Plane0 of described NANDflash;
In one embodiment, described controller 41, specifically for mating described first data manipulation address with the second data manipulation address stored in described data message table;
When the match is successful, determine that data manipulation strategy is for read corresponding data from described second memory 43;
When it fails to match, determine that data manipulation strategy is for read corresponding data from described first memory 42;
Wherein, first memory 42 comprises at least one quantum memory, and described second memory 43 is one-to-one relationship with described quantum memory; The data that described second memory 43 reads from described quantum memory for buffer memory;
In one embodiment, when described first memory 42 is NANDflash, accordingly, described quantum memory is the plane in described NANDflash, and described second memory 43 is the register of corresponding described plane;
When the match is successful, showing that the data that will read have been stored in corresponding register, namely reading in the plane of NANDflash without the need to going, can directly go to read required data in corresponding register; As: if the first data manipulation address that the match is successful is Chip0Plane0Addr, can directly go to carry out digital independent in the register of corresponding described Plane0; So, improve each page data of reading from NANDflash in prior art to the data reading performance using redundancy of register, more because described register-bit is in NAND flash controller, do not increase extra internal memory, provide cost savings.
It is namely described that it fails to match there is not the second data manipulation address identical with described first data manipulation address in described data message table, corresponding data is read from described first memory, in embodiments of the present invention, namely from NANDflash, read corresponding data, namely perform data from NANDflash to register to the data read process of NAND flash controller.
In one embodiment, described controller 41, also for obtaining at least one first data manipulation address that resolution data operational order in the very first time obtains, record at least one first data manipulation address described is to form described data message table.
In one embodiment, described controller 41, specifically for described first data manipulation address is recorded to described data message table, and deletes data address invalid in described data message table;
Here, described first data manipulation address is increased to described data message table, when next time reads the data of identical address, directly data can be read by register read operation.
The described invalid data address data that namely this address is corresponding do not exist in described register, and in embodiments of the present invention, if described register experienced by the operation write/wipe, then the address that in described register, data are corresponding just becomes invalid data address.
In one embodiment, described controller 41, specifically for obtaining the state data memory of described second memory;
Determine that the state data memory of described second memory is for empty, deletes the second data manipulation address of corresponding described first data manipulation address in described data message table;
Here, described state data memory comprises sky and non-NULL;
When described state data memory is empty, show that the data in described second memory have been read, namely need to delete the address that the data that have been read described in data message table are corresponding, delete the second data manipulation address of corresponding described first data manipulation address in described data message table; When described state data memory is non-NULL, show that the data in described second memory have not also been read, without the need to making any relevant treatment.
Embodiment four
Fig. 5 is the invention process csr controller composition structural representation; As shown in Figure 5, for the invention process csr controller composition comprises: receiver module 51, parsing module 52, determination module 53 and processing module 54; Wherein,
Described receiver module 51, for receiving data manipulation instruction;
Described parsing module 52, for resolving described data manipulation instruction, obtains the first data manipulation address;
Described determination module 53, for based on described first data manipulation address and data message table determination data manipulation strategy;
Described processing module 54, for reading corresponding data according to established data operation strategy from the first data storage location or the second data storage location; Wherein, described first data storage location is different from described second data storage location.
In one embodiment, described first data storage location is positioned at the first data storage cell, and described second data storage location is positioned at the second data storage cell; Described second data storage cell is used for the data that buffer memory reads from the first data storage cell.
In one embodiment, described determination module 53, specifically for mating described first data manipulation address with the second data manipulation address of recording in described data message table;
When the match is successful, determine that data manipulation strategy is for reading corresponding data from described second data storage location;
When it fails to match, determine that data manipulation strategy is for reading corresponding data from described first data storage location.
In one embodiment, described controller also comprises creation module 55, and for obtaining at least one first data manipulation address that resolution data operational order in the very first time obtains, record at least one first data manipulation address described is to form described data message table.
In one embodiment, described processing module 54, also for described first data manipulation address is recorded to described data message table, and deletes data address invalid in described data message table.
In one embodiment, described processing module 54, also for obtaining the state data memory of described second data storage location;
Determine that the state data memory of described second data storage location is for empty, deletes the second data manipulation address of corresponding described first data manipulation address in described data message table.
In embodiments of the present invention, receiver module 51, parsing module 52, determination module 53, processing module 54 and creation module 55 all can by the central processing unit (CPU in terminal or server, or digital signal processor (DSP CentralProcessingUnit), or field programmable gate array (FPGA DigitalSignalProcessor), FieldProgrammableGateArray) or integrated circuit (ASIC, ApplicationSpecificIntegratedCircuit) realize.
Here it is to be noted: the description relating to electronic equipment and controller item above, it is similar for describing with said method, and the beneficial effect with method describes, and does not repeat.For the ins and outs do not disclosed in device of the present invention and system embodiment, please refer to the description of the inventive method embodiment.
One of ordinary skill in the art will appreciate that: all or part of step realizing said method embodiment can have been come by the hardware that programmed instruction is relevant, aforesaid program can be stored in a computer read/write memory medium, this program, when performing, performs the step comprising said method embodiment; And aforesaid storage medium comprises: movable storage device, ROM (read-only memory) (ROM, Read-OnlyMemory), random access memory (RAM, RandomAccessMemory), magnetic disc or CD etc. various can be program code stored medium.
Or, if the above-mentioned integrated unit of the present invention using the form of software function module realize and as independently production marketing or use time, also can be stored in a computer read/write memory medium.Based on such understanding, the technical scheme of the embodiment of the present invention can embody with the form of software product the part that prior art contributes in essence in other words, this computer software product is stored in a storage medium, comprises some instructions and performs all or part of of method described in each embodiment of the present invention in order to make a computer equipment (can be personal computer, server or the network equipment etc.).And aforesaid storage medium comprises: movable storage device, ROM, RAM, magnetic disc or CD etc. various can be program code stored medium.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.
Claims (12)
1. a data processing method, is characterized in that, described method comprises:
Receive data manipulation instruction;
Resolve described data manipulation instruction, obtain the first data manipulation address;
Based on described first data manipulation address and data message table determination data manipulation strategy;
Corresponding data is read from the first data storage location or the second data storage location according to established data operation strategy; Wherein, described first data storage location is different from described second data storage location.
2. method according to claim 1, is characterized in that, describedly comprises based on described first data manipulation address and data message table determination data manipulation strategy:
Described first data manipulation address is mated with the second data manipulation address stored in described data message table;
When the match is successful, determine that data manipulation strategy is for reading corresponding data from described second data storage location;
When it fails to match, determine that data manipulation strategy is for reading corresponding data from described first data storage location.
3. method according to claim 1, it is characterized in that, described first data storage location is positioned at the first data storage cell, and described second data storage location is positioned at the second data storage cell; Described first data storage cell comprises at least one first sub-storage unit, and described second data storage cell is used for the data that buffer memory reads from described first sub-storage unit.
4. method according to claim 1, it is characterized in that, described method also comprises:
Obtain at least one first data manipulation address that in the very first time, resolution data operational order obtains, record at least one first data manipulation address described is to form described data message table.
5. method according to claim 1, is characterized in that, described according to established data operation strategy from after the first data storage location reads corresponding data, described method also comprises:
Described first data manipulation address is recorded to described data message table, and deletes data address invalid in described data message table.
6. method according to claim 1, is characterized in that, described according to established data operation strategy from after the second data storage location reads corresponding data, described method also comprises:
Obtain the state data memory of described second data storage location;
Determine that the state data memory of described second data storage location is for empty, deletes the second data manipulation address of corresponding described first data manipulation address in described data message table.
7. an electronic equipment, is characterized in that, described electronic equipment comprises: controller, first memory and second memory;
Described controller, for receiving data manipulation instruction;
Resolve described data manipulation instruction, obtain the first data manipulation address;
Based on described first data manipulation address and data message table determination data manipulation strategy;
Corresponding data is read from first memory or second memory according to established data operation strategy.
8. electronic equipment according to claim 7, is characterized in that, described controller, specifically for being mated with the second data manipulation address stored in described data message table described first data manipulation address;
When the match is successful, determine that data manipulation strategy is for reading corresponding data from described second memory;
When it fails to match, determine that data manipulation strategy is for reading corresponding data from described first memory.
9. electronic equipment according to claim 7, it is characterized in that, described controller, also for obtaining at least one first data manipulation address that resolution data operational order in the very first time obtains, record at least one first data manipulation address described is to form described data message table.
10. electronic equipment according to claim 7, is characterized in that, described controller, specifically for described first data manipulation address is recorded to described data message table, and deletes data address invalid in described data message table.
11. electronic equipments according to claim 7, is characterized in that, described controller, specifically for obtaining the state data memory of described second memory;
Determine that the state data memory of described second memory is for empty, deletes the second data manipulation address of corresponding described first data manipulation address in described data message table.
12. 1 kinds of controllers, is characterized in that, described controller comprises: receiver module, parsing module, determination module and processing module; Wherein,
Described receiver module, for receiving data manipulation instruction;
Described parsing module, for resolving described data manipulation instruction, obtains the first data manipulation address;
Described determination module, for based on described first data manipulation address and data message table determination data manipulation strategy;
Described processing module, for reading corresponding data according to established data operation strategy from the first data storage location or the second data storage location; Wherein, described first data storage location is different from described second data storage location.
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| CN109558386A (en) * | 2018-11-26 | 2019-04-02 | 北京微播视界科技有限公司 | A kind of caching method of client data, device, equipment and medium |
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