CN105430420B - A kind of discrete cosine transform dct8 device and methods for realizing multiplexing - Google Patents
A kind of discrete cosine transform dct8 device and methods for realizing multiplexing Download PDFInfo
- Publication number
- CN105430420B CN105430420B CN201510979672.6A CN201510979672A CN105430420B CN 105430420 B CN105430420 B CN 105430420B CN 201510979672 A CN201510979672 A CN 201510979672A CN 105430420 B CN105430420 B CN 105430420B
- Authority
- CN
- China
- Prior art keywords
- dimensional transform
- register group
- transform device
- dimensional
- dimentional
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
- G06F17/147—Discrete orthonormal transforms, e.g. discrete cosine transform, discrete sine transform, and variations therefrom, e.g. modified discrete cosine transform, integer transforms approximating the discrete cosine transform
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Computational Mathematics (AREA)
- Pure & Applied Mathematics (AREA)
- Data Mining & Analysis (AREA)
- Theoretical Computer Science (AREA)
- Discrete Mathematics (AREA)
- Algebra (AREA)
- Databases & Information Systems (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Compression Or Coding Systems Of Tv Signals (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
The present invention provides a kind of 8 device of discrete cosine transform for realizing multiplexing, including:One-dimensional transform device, two 8 path multiplexers, two-dimentional register group, two-dimensional transform device and reg registers;The two dimension register group is by 8 two-dimentional register groups into each two dimension register stores 1 pixel data;It is described that 8 pixel datas obtained after 8X8 discrete cosine transforms transform block progress one-dimensional transform processing in coded image are write direct into the position specified in two-dimentional register group after the multiplexing of one 8 path multiplexers;By another 8 path multiplexer, the map function that 8 pixel datas carry out two dimension is read in the same position from two-dimentional register group to the two-dimensional transform device;Result data after the reg registers storage two-dimensional transform operation.The present invention realizes the high-performance code demand of video 4kx2k@30FPS, 1080p@120FPS, and saves the resource consumption in dct conversion processes and power consumption consumption.
Description
Technical field
The present invention relates to technical field of video coding more particularly to a kind of discrete cosine transform dct8 devices for realizing multiplexing
And method.
Background technology
H.264 it is current newest international video compression standards.H.264 possess high code efficiency, be primarily due to
The more accurate intra prediction (intra prediction) and inter-prediction (inter prediction) used.But these
The raising of code efficiency all can be with the raising of encoder complexity, to realize that real time algorithm proposes new challenge.
With the rise of wearable smart machine, the hardware device requirement increasingly low-power consumption integrated in little space,
And can efficient process items affairs, especially for the social demand of the popularity such as video acquisition, this also results in video
The challenge of coded system.Discrete cosine transform dct conversion is as a great computing of calculation amount in H.264 Video coding
For journey, it is necessary to consume many register resources, this also results in the video encoder problem of area and power consumption in design.
The intermediate transposing portion of the discrete cosine transform dct8 devices of the prior art uses random access memory ram, and
And need to split independent 8 ram units, entire area can't be saved too much;The processing time of entire 8x8DCT transform blocks
13 clock cycle is needed to complete;The operation and use of ram is complex, and the later stage needs individually to carry out the maintenance of ram;
In addition, ram not necessarily supports same address to read while write, therefore during the multiple dct8x8 blocks of processing, every time two
It ties up converter to read the ram data moment, one-dimensional transform device needs of the latter dct8x8 blocks etc. can just write after running through.
The content of the invention
One of the technical problem to be solved in the present invention is that providing a kind of discrete cosine transform 8 for realizing multiplexing fills
It puts, realizes the high-performance code demand of video 4kx2k@30FPS, 1080p@120FPS, and save the resource in dct conversion processes
Consumption and power consumption consumption.
What one of problem of the present invention was realized in:A kind of 8 device of discrete cosine transform for realizing multiplexing,
Including:One-dimensional transform device, two 8 path multiplexers, two-dimentional register group, two-dimensional transform device and reg registers;
The two dimension register group is by 8 two-dimentional register groups into each two dimension register stores 1 pixel data;
The one-dimensional transform device is connected through 8 path multiplexers with the two-dimentional register group, the two dimension register group
It is connected by another 8 path multiplexer with the two-dimensional transform device, two-dimensional transform device is connected with the reg registers;
The one-dimensional transform device will in coded image 8X8 discrete cosine transformation blocks carry out one-dimensional transform processing after obtain 8
A pixel data writes direct the position specified in two-dimentional register group after the multiplexing of one 8 path multiplexers;
By another 8 path multiplexer, 8 pixels are read in the same position from two-dimentional register group to the two-dimensional transform device
Data carry out the map function of two dimension;
Result data after the reg registers storage two-dimensional transform operation.
Further, 8X8 discrete cosine transformation blocks pass through one-dimensional transform device and two-dimensional transform device in the coded image
If 11 clock cycle of processing time, and meet sequential processing requirement.
Further, the behaviour that the two-dimentional register group is controlled reading and write data respectively using two 4Bits counters
Make.
Further, it is two-dimensional transform device behaviour in the case that transverse direction is write to write two-dimentional register group when the operation of one-dimensional transform device
Work is also laterally to read the two-dimentional register row pixel that one-dimensional transform device was write to carry out two-dimensional process, so as to carry out at energy flowing water
Reason;
In the case that one-dimensional transform device longitudinally writes two-dimentional register group, two-dimensional transform device is also longitudinal reading;Equally into
Row stream treatment;
Then horizontal and vertical is all public a set of two-dimentional register group, while horizontal and vertical can be grasped using register
The characteristic of work.
The second technical problem to be solved by the present invention is to provide a kind of 8 side of discrete cosine transform for realizing multiplexing
Method, realizes the high-performance code demand of 4kx2k@30FPS, 1080p@120FPS, and saves the resource consumption in dct conversion processes
It is consumed with power consumption.
What the two of problem of the present invention were realized in:A kind of 8 method of discrete cosine transform for realizing multiplexing, the side
Method need to provide one-dimensional transform device, two 8 path multiplexers, two-dimentional register group, two-dimensional transform device and reg registers;Described two
Register group is tieed up by 8 two-dimentional register groups into each two dimension register stores 1 pixel data;
The method is specially:
The one-dimensional transform device will in coded image 8X8 discrete cosine transformation blocks carry out one-dimensional transform processing after obtain 8
A pixel data writes direct the position specified in two-dimentional register group after the multiplexing of one 8 path multiplexers;
By another 8 path multiplexer, 8 pixels are read in the same position from two-dimentional register group to the two-dimensional transform device
Data carry out the map function of two dimension;Without the behaviour that pauses when the one-dimensional transform device and two-dimensional transform device procession read-write operation
Make, it can complete stream treatment;
Result data after the reg registers storage two-dimensional transform operation.
Further, 8X8 discrete cosine transformation blocks pass through one-dimensional transform device and two-dimensional transform device in the coded image
If 11 clock cycle of processing time, and meet sequential processing requirement.
Further, the behaviour that the two-dimentional register group is controlled reading and write data respectively using two 4Bits counters
Make.
Further, it is two-dimensional transform device behaviour in the case that transverse direction is write to write two-dimentional register group when the operation of one-dimensional transform device
Work is also laterally to read the two-dimentional register row pixel that one-dimensional transform device was write to carry out two-dimensional process, so as to carry out at energy flowing water
Reason;
In the case that one-dimensional transform device longitudinally writes two-dimentional register group, two-dimensional transform device is also longitudinal reading;Equally into
Row stream treatment;
Then horizontal and vertical is all public a set of two-dimentional register group, while horizontal and vertical can be grasped using register
The characteristic of work.
The invention has the advantages that:The two-dimentional register group of the present invention can support very well while ranks read-write operation;
Due to supporting to read while write, more consumption can't be brought to area;It realizes the resource multiplex in dct8 conversion processes, reduces core
Piece design area and power consumption.Present invention eliminates the independent maintenances of random access memory ram in the prior art and increase simultaneously
Ram tests logic.
Description of the drawings
Fig. 1 is the structure diagram of apparatus of the present invention.
Fig. 2 is the flow diagram of the method for the present invention.
Fig. 3 is the structure that one-dimensional transform device of the present invention is read toward two-dimentional register group according to two-dimensional transform device after row write according to row
Schematic diagram.
Fig. 4 writes structure of the rear two-dimensional transform device according to row reading toward two-dimentional register group for one-dimensional transform device of the present invention according to row
Schematic diagram.
Specific embodiment
Refering to Figure 1, a kind of 8 device of discrete cosine transform for realizing multiplexing of the present invention, including:One-dimensional change
10, two 8 path multiplexers 11 of parallel operation, two-dimentional register group 12, two-dimensional transform device 13 and reg registers 14;The two dimension is posted
Storage group 12 is by 8 two-dimentional register groups into each two dimension register stores 1 pixel data;
The one-dimensional transform device 10 is connected through 8 path multiplexers 11 with the two-dimentional register group 12, and the two dimension is posted
Storage group 12 is connected by another 8 path multiplexer 11 with the two-dimensional transform device 13, and the two-dimensional transform device 13 and reg is deposited
Device 14 connects;
The one-dimensional transform device 10 obtains after 8X8 discrete cosine transformation blocks in coded image are carried out one-dimensional transform processing
8 pixel datas write direct the position specified in two-dimentional register group 12 after the multiplexing of one 8 path multiplexers 11;It answers on 8 tunnel
It can make one path channels of multichannel data information sharing with device 11.
By another 8 path multiplexer 11, the same position from two-dimentional register group 12 reads 8 to the two-dimensional transform device 13
A pixel data carries out the map function of two dimension;
The reg registers 14 store the result data after two-dimensional transform operation.
In the present invention, 8X8 discrete cosine transformation blocks pass through one-dimensional transform device and two-dimensional transform device in the coded image
As long as 11 clock cycle of processing time, and meet sequential processing requirement.The two dimension register group is counted using two 4Bits
Number device reads and writes the operation of data to control respectively.
Wherein, it is two-dimensional transform device operation in the case that transverse direction is write to write two-dimentional register group when the operation of one-dimensional transform device
It is laterally to read the two-dimentional register row pixel that one-dimensional transform device was write to carry out two-dimensional process, so as to carry out energy stream treatment;
In the case that one-dimensional transform device longitudinally writes two-dimentional register group, two-dimensional transform device is also longitudinal reading;Equally into
Row stream treatment;
Then horizontal and vertical is all public a set of two-dimentional register group, this just saves resource, while utilizes register
It can horizontal and vertical all operable characteristic.
It refers to shown in Fig. 2 to Fig. 4, a kind of 8 method of discrete cosine transform for realizing multiplexing of the invention, the side
Method need to provide one-dimensional transform device, two 8 path multiplexers, two-dimentional register group, two-dimensional transform device and reg registers;Described two
Register group is tieed up by 8 two-dimentional register groups into each two dimension register stores 1 pixel data;8 path multiplexer can make more
One path channels of circuit-switched data information sharing.
The method is specially:
S1:The one-dimensional transform device obtains after 8X8 discrete cosine transformation blocks in coded image are carried out one-dimensional transform processing
8 pixel datas by one 8 path multiplexers multiplexing after write direct the position specified in two-dimentional register group;
S2:By another 8 path multiplexer, 8 pictures are read in the same position from two-dimentional register group to the two-dimensional transform device
Prime number is according to the map function for carrying out two dimension;Without pausing when the one-dimensional transform device and two-dimensional transform device procession read-write operation
Operation, can complete stream treatment;
S3:Result data after the reg registers storage two-dimensional transform operation.
Wherein, the processing that 8X8 discrete cosine transformation blocks pass through one-dimensional transform device and two-dimensional transform device in the coded image
If 11 clock cycle of time, and meet sequential processing requirement.The two dimension register group is come using two 4Bits counters
The operation of data is read and is write in control respectively.
The 8X8DCT transform blocks conversion of the present invention, is divided into one-dimensional transform and two-dimensional transform, it is that one-dimensional transform obtains as a result,
Transposition is needed, is then followed by two-dimensional transform.
The design of the present invention, 8X8 discrete cosine transformation blocks convert a clock cycle cycle and operate 8 pixels.8
Clock cycle cycle completes the one-dimensional row conversion of 8 rows, then just can be with start to process rank transformation.Improve conversion efficiency.
When one-dimensional transform device operation write two-dimentional register group be laterally write in the case of, two-dimensional transform device operation be also laterally
It reads the two-dimentional register row pixel that one-dimensional transform device was write and carries out two-dimensional process, so as to carry out energy stream treatment;
In the case that one-dimensional transform device longitudinally writes two-dimentional register group, two-dimensional transform device is also longitudinal reading;Equally into
Row stream treatment;
Then horizontal and vertical is all public a set of two-dimentional register group, this just saves resource, while utilizes register
It can horizontal and vertical all operable characteristic.
In short, the two-dimentional register group of the present invention can support very well while ranks read-write operation;Due to supporting to read simultaneously
It writes, more consumption can't be brought to area;It realizes the resource multiplex in dct8 conversion processes, reduces chip design area and work(
Consumption.Present invention eliminates the independent maintenances of random access memory ram in the prior art and increase ram test logics simultaneously.
The foregoing is merely presently preferred embodiments of the present invention, all equivalent changes done according to scope of the present invention patent with
Modification should all belong to the covering scope of the present invention.
Claims (8)
1. a kind of 8 device of discrete cosine transform for realizing multiplexing, it is characterised in that:
Including:One-dimensional transform device, two 8 path multiplexers, two-dimentional register group, two-dimensional transform device and reg registers;It is described
Two-dimentional register group is by 8 two-dimentional register groups into each two dimension register stores 1 pixel data;
The one-dimensional transform device is connected through 8 path multiplexers with the two-dimentional register group, and the two dimension register group passes through
Another 8 path multiplexer is connected with the two-dimensional transform device, and two-dimensional transform device is connected with the reg registers;
8 pictures that 8X8 discrete cosine transformation blocks in coded image obtain after one-dimensional transform processing by the one-dimensional transform device
Prime number writes direct the position specified in two-dimentional register group according to after the multiplexing of one 8 path multiplexers;
By another 8 path multiplexer, 8 pixel datas are read in the same position from two-dimentional register group to the two-dimensional transform device
Carry out the map function of two dimension;
Result data after the reg registers storage two-dimensional transform operation.
2. a kind of 8 device of discrete cosine transform for realizing multiplexing according to claim 1, it is characterised in that:
As long as the processing time 11 that 8X8 discrete cosine transformation blocks pass through one-dimensional transform device and two-dimensional transform device in the coded image
A clock cycle, and meet sequential processing requirement.
3. a kind of 8 device of discrete cosine transform for realizing multiplexing according to claim 1, it is characterised in that:Described two
The operation that dimension register group is controlled reading and write data respectively using two 4Bits counters.
4. a kind of 8 device of discrete cosine transform for realizing multiplexing according to claim 1, it is characterised in that:When one-dimensional
It is in the case of laterally writing that converter operation, which writes two-dimentional register group, and the operation of two-dimensional transform device is also laterally to read one-dimensional transform device
The two-dimentional register row pixel write carries out two-dimensional process, so as to carry out stream treatment;
In the case that one-dimensional transform device longitudinally writes two-dimentional register group, two-dimensional transform device is also longitudinal reading;Equally flowed
Water process;
Then horizontal and vertical is all public a set of two-dimentional register group, while utilizes the horizontal and vertical all operable spy of register
Property.
A kind of 5. 8 method of discrete cosine transform for realizing multiplexing, it is characterised in that:The method need to provide one-dimensional transform device,
Two 8 path multiplexers, two-dimentional register group, two-dimensional transform device and reg registers;The two dimension register group is by 8 two dimensions
Register group is into each two dimension register stores 1 pixel data;
The method is specially:
8 pictures that 8X8 discrete cosine transformation blocks in coded image obtain after one-dimensional transform processing by the one-dimensional transform device
Prime number writes direct the position specified in two-dimentional register group according to after the multiplexing of one 8 path multiplexers;
By another 8 path multiplexer, 8 pixel datas are read in the same position from two-dimentional register group to the two-dimensional transform device
Carry out the map function of two dimension;Without quiescent operation when the one-dimensional transform device and two-dimensional transform device procession read-write operation,
It can complete stream treatment;
Result data after the reg registers storage two-dimensional transform operation.
6. a kind of 8 method of discrete cosine transform for realizing multiplexing according to claim 5, it is characterised in that:
As long as the processing time 11 that 8X8 discrete cosine transformation blocks pass through one-dimensional transform device and two-dimensional transform device in the coded image
A clock cycle, and meet sequential processing requirement.
7. a kind of 8 method of discrete cosine transform for realizing multiplexing according to claim 5, it is characterised in that:Described two
The operation that dimension register group is controlled reading and write data respectively using two 4Bits counters.
8. a kind of 8 method of discrete cosine transform for realizing multiplexing according to claim 5, it is characterised in that:When one-dimensional
It is in the case of laterally writing that converter operation, which writes two-dimentional register group, and the operation of two-dimensional transform device is also laterally to read one-dimensional transform device
The two-dimentional register row pixel write carries out two-dimensional process, so as to carry out stream treatment;
In the case that one-dimensional transform device longitudinally writes two-dimentional register group, two-dimensional transform device is also longitudinal reading;Equally flowed
Water process;
Then horizontal and vertical is all public a set of two-dimentional register group, while utilizes the horizontal and vertical all operable spy of register
Property.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510979672.6A CN105430420B (en) | 2015-12-24 | 2015-12-24 | A kind of discrete cosine transform dct8 device and methods for realizing multiplexing |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510979672.6A CN105430420B (en) | 2015-12-24 | 2015-12-24 | A kind of discrete cosine transform dct8 device and methods for realizing multiplexing |
Publications (2)
Publication Number | Publication Date |
---|---|
CN105430420A CN105430420A (en) | 2016-03-23 |
CN105430420B true CN105430420B (en) | 2018-05-22 |
Family
ID=55508305
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510979672.6A Active CN105430420B (en) | 2015-12-24 | 2015-12-24 | A kind of discrete cosine transform dct8 device and methods for realizing multiplexing |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN105430420B (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101866330A (en) * | 2009-04-20 | 2010-10-20 | 天津天极视讯科技发展有限公司 | System, method and device for realizing two-dimensional transformation processing |
CN102857756A (en) * | 2012-07-19 | 2013-01-02 | 西安电子科技大学 | Transfer coder adaptive to high efficiency video coding (HEVC) standard |
CN103067718A (en) * | 2013-01-30 | 2013-04-24 | 上海交通大学 | One-dimensional inverse discrete cosine transform (IDCT) module circuit suitable for digital video coding/decoding |
CN103237219A (en) * | 2013-04-24 | 2013-08-07 | 南京龙渊微电子科技有限公司 | Two-dimensional discrete cosine transformation (DCT)/inverse DCT circuit and method |
-
2015
- 2015-12-24 CN CN201510979672.6A patent/CN105430420B/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101866330A (en) * | 2009-04-20 | 2010-10-20 | 天津天极视讯科技发展有限公司 | System, method and device for realizing two-dimensional transformation processing |
CN102857756A (en) * | 2012-07-19 | 2013-01-02 | 西安电子科技大学 | Transfer coder adaptive to high efficiency video coding (HEVC) standard |
CN103067718A (en) * | 2013-01-30 | 2013-04-24 | 上海交通大学 | One-dimensional inverse discrete cosine transform (IDCT) module circuit suitable for digital video coding/decoding |
CN103237219A (en) * | 2013-04-24 | 2013-08-07 | 南京龙渊微电子科技有限公司 | Two-dimensional discrete cosine transformation (DCT)/inverse DCT circuit and method |
Non-Patent Citations (2)
Title |
---|
DCT算法分析与结构设计;张晓晨;《中国优秀硕士学位论文全文数据库》;20101015;第三章第3.7节 * |
高精度二维DCT的结构优化算法研究及FPGA实现;何业军;《电视技术》;20110802(第15期);全文 * |
Also Published As
Publication number | Publication date |
---|---|
CN105430420A (en) | 2016-03-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN107704923B (en) | Convolutional neural network operation circuit | |
Mohanty et al. | Memory-efficient high-speed convolution-based generic structure for multilevel 2-D DWT | |
CN102158694B (en) | Remote-sensing image decompression method based on GPU (Graphics Processing Unit) | |
CN107085562A (en) | A kind of neural network processor and design method based on efficient multiplexing data flow | |
CN102932643B (en) | A kind of expansion variable-block motion estimation circuit being applicable to HEVC standard | |
CN103237157B (en) | A kind of real-time high-definition video image transpose device | |
CN105488753B (en) | A kind of pair of image carries out the method and device of two-dimension fourier transform or inverse transformation | |
CN103778086A (en) | Coarse-grained dynamic reconfigurable system based multi-mode data access device and method | |
CN105430420B (en) | A kind of discrete cosine transform dct8 device and methods for realizing multiplexing | |
CN103377686B (en) | Nand Flash storer and realize the method for the continuous read operation of Nand Flash storer | |
CN103389413A (en) | Real-time statistical method for frequency spectrum histogram | |
CN102970545A (en) | Static image compression method based on two-dimensional discrete wavelet transform algorithm | |
CN101534439A (en) | Low power consumption parallel wavelet transforming VLSI structure | |
CN104270643B (en) | Address mapping algorithm for transposed matrix based on single-port SRAM | |
CN105160622B (en) | The implementation method of image super-resolution based on FPGA | |
Błażewicz et al. | Two-dimensional discrete wavelet transform on large images for hybrid computing architectures: GPU and CELL | |
CN111368250B (en) | Data processing system, method and equipment based on Fourier transformation/inverse transformation | |
CN102880594B (en) | Parallel matrix based on multi-core DSP full pivoting Gauss Jordan inversion technique | |
CN102231202B (en) | SAD (sum of absolute difference) vectorization realization method oriented to vector processor | |
DE102022117746A1 (en) | STORAGE INTERFACE WITH ENERGY-SAVING TRANSFER MODE | |
CN104185030A (en) | JPEG 2000 image uncompressing implementation method based on GPU | |
CN102663759A (en) | Remote-sensing image rapid-processing method | |
Zhang et al. | Design and Implementation of Parallel FFT on CUDA | |
CN102487439A (en) | Audio and video acquisition and play processing method with whole embedding of memory | |
CN102104773B (en) | Radix-4 module of FFT (Fast Fourier Transform)/IFFT (Inverse Fast Fourier Transform) processor for realizing variable data number |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant | ||
CP01 | Change in the name or title of a patent holder | ||
CP01 | Change in the name or title of a patent holder |
Address after: 350000 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee after: Ruixin Microelectronics Co., Ltd Address before: 350000 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee before: Fuzhou Rockchips Electronics Co.,Ltd. |