CN105428352B

CN105428352B - The method for forming layout designs

Info

Publication number: CN105428352B
Application number: CN201510573824.2A
Authority: CN
Inventors: 谢东衡; 林仲德; 王胜雄; 庄惠中; 蔣敏雄; 江庭玮; 田丽钧
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2014-09-12
Filing date: 2015-09-10
Publication date: 2018-08-31
Anticipated expiration: 2035-09-10

Abstract

A kind of method of layout designs the invention discloses formation for manufacturing integrated circuit (IC).This method includes identifying one or more of layout designs that one or more segments by multiple gate structure layout patterns of layout designs occupy region；And generate the layout patterns group Chong Die with one or more regions of identification.There is multiple gate structure layout patterns preset space length, preset space length to be less than the spatial resolution of predetermined photoetching technique.The width of first layout patterns of layout patterns group is less than twice of preset space length.The invention further relates to the methods for forming layout designs.

Description

The method for forming layout designs

Technical field

The present invention relates to the methods for forming layout designs.

Background technology

Integrated circuit (IC) is manufactured according to the layout designs that can be used to form multiple masks, mask is for being formed selectively Or the layer of the multiple components of removal, such as layer of active area, gate electrode, the layer of multiple isolation structures and/or multiple conductive structures. In some applications, IC includes the transistor for having different threshold voltages.In an example, along the critical speed path of IC Transistor in unit has lower threshold voltage than transistor those of in the unit along the non-critical speed path of IC. In another example, the gate structure at elementary boundary constitutes pseudocone pipe and is adjusted to have more than other functional transistors High threshold voltage, for reducing the current leakage by pseudocone pipe.

Invention content

In order to solve the problems in the prior art, according to some embodiments of the present invention, a kind of formed for making is provided The method for making the layout designs of integrated circuit (IC), the method includes：Identify multiple gate structures by the layout designs One or more of the layout designs that one or more segments of layout patterns occupy region, one or more of areas Domain is corresponding with electrical characteristics adjusting one or more regions of the IC of technique are subjected to, and the electrical characteristics adjust technique for manufacturing The IC, the multiple gate structure layout patterns extend along a first direction and with can be measured along second direction it is pre- Determining deviation, and the preset space length is less than the spatial resolution of predetermined photoetching technique；And it generates and one of the identification Or the layout patterns group of multiple regions overlapping, the layout patterns group will be formed with before implementing the electrical characteristics and adjusting technique One or more openings in the mask layer correspond to, and the first layout patterns of the layout patterns group have can be along described second The width of orientation measurement, and the width of first layout patterns is less than twice of the preset space length.

Other embodiments according to the present invention provide a kind of layout designs formed for manufacturing integrated circuit (IC) Method, the method includes：It identifies by one or more segments of multiple gate structure layout patterns of the layout designs One or more of the layout designs occupied region, one or more of regions adjust technique with electrical characteristics are subjected to One or more regions of the IC correspond to, and the electrical characteristics adjust technique for manufacturing the IC, the multiple gate structure Layout patterns extend and have the preset space length that can be measured along second direction, and the preset space length along a first direction Less than the spatial resolution of predetermined photoetching technique；And generate the layout patterns Chong Die with one or more regions of the identification Group, the layout patterns group with will be formed in one or more of mask layer before implementing the electrical characteristics and adjusting technique and open Mouth is corresponding, and the first layout patterns and the second layout patterns of the layout patterns group are by the first gap along the second direction It separates, and can be less than along the width in first gap that the second direction measures twice of the preset space length.

Other embodiment according to the present invention provides a kind of layout designs for manufacturing integrated circuit (IC), packet It includes：First layout layer, including multiple gate structure layout patterns, the multiple gate structure layout patterns prolong along a first direction The preset space length that can be measured along second direction is stretched and has, and the preset space length is less than the space of predetermined photoetching technique Resolution ratio；And second layout layer, including based on one or more open region arrangement mask layout pattern group, it is one or One or more Chong Die, the multiple gate structure layout patterns of multiple open regions and the multiple gate structure layout patterns One or more be subjected to electrical characteristics adjusting one or more gate structures of technique it is corresponding, the mask layout pattern group First mask layout pattern has the width that can be measured along the second direction, and the width of the first mask layout pattern Degree is equal to the preset space length.

Description of the drawings

When reading in conjunction with the accompanying drawings, from it is described in detail below can best understanding each aspect of the present invention.It should be noted that According to the standard practices in industry, all parts are not drawn on scale.In fact, in order to clearly discuss, the ruler of all parts It is very little to arbitrarily increase or reduce.

Figure 1A is the figure of the section layout design of circuit in accordance with some embodiments.

Figure 1B is the figure of the section layout design of another circuit in accordance with some embodiments.

Fig. 1 C are the figures of section layout design corresponding with the circuit of Figure 1A or Figure 1B in accordance with some embodiments.

Fig. 2 is the flow chart of the method in accordance with some embodiments for forming layout designs.

Fig. 3 A to Fig. 3 I are the figures of the part of multiple layout designs in accordance with some embodiments, are shown for definition graph 2 Shown in method operation multiple examples.

Fig. 4 A to Fig. 4 B are the sectional views of the part of difference IC in accordance with some embodiments, and different IC can be used for illustrating two Different threshold voltage adjustments technique.

Fig. 5 A to Fig. 5 B are the sectional views of part IC in accordance with some embodiments, and IC can be used for illustrating that gate structure cuts down work Skill.

Fig. 6 is the flow chart of the method for manufacture IC in accordance with some embodiments.

Fig. 7 is the block diagram of layout designs system in accordance with some embodiments.

Specific implementation mode

Following disclosure provides the different embodiments or example of many different characteristics for realizing the present invention.Below The specific example of component and arrangement is described to simplify the present invention.Certainly, these are only example, and are not intended to be limited to this hair It is bright.For example, in the following description, above second component or the upper formation first component may include the first component and second Part is in direct contact the embodiment to be formed, and can also be included between the first component and second component and can form additional portion Part, so that the embodiment that the first component and second component can be not directly contacted with.In addition, the present invention can be in various embodiments Repeat reference numerals and/or character.The repetition is for purposes of simplicity and clarity, and itself not indicate to be discussed each Relationship between a embodiment and/or configuration.

Moreover, for ease of description, can use herein such as " ... under ", " in ... lower section ", " lower part ", " ... it On ", the spatially relative term on " top " etc., to describe an element as shown in the figure or component and another (or other) member The relationship of part or component.Other than orientation shown in figure, spatially relative term be intended to include device in use or operation Different direction.Device can otherwise orient (be rotated by 90 ° or in other directions), and space used herein is opposite Descriptor can be explained similarly accordingly.

In some embodiments, it can be used for the layout layer of multiple gate structures with the spatial discrimination than predetermined photoetching technique The smaller preset space length of rate.Moreover, the mask layout layer that can be used to form mask has the minimum spacing equal to the preset space length, Mask limits the region of the electrical characteristics adjusting technique of the transistor for implementing to generate.With with twice more than preset space length The mask layout layer of minimum spacing is compared, and the cost that mask is used to form according to the present invention is larger, but the integrated circuit generated (IC) whole gate densities are higher.In some embodiments, the overall cost of IC constructed in accordance actually is lower than root The cost of IC is manufactured according to the mask layout layer with twice of the minimum spacing more than preset space length.

Figure 1A is the figure of the section layout design 100A of circuit in accordance with some embodiments.Layout designs 100A, which is shown, to be come From the layout patterns of the overlapping of multiple layout layers of layout designs 100A.Simplify or be omitted some layouts of layout designs 100A Pattern and some layout layers.Layout designs 100A shows the non-limiting examples for being used to help illustrate the present invention.

Layout designs 100A includes that the first oxide spreads (OD) layout patterns 102；2nd OD layout patterns 104；It is multiple Gate structure layout patterns 121,123,125,127 and 129；Multiple conductive component layout patterns 132,134,136,142,144 With 146；And multiple via arrangements patterns 150.Layout designs 100A also includes the first power generation configuration pattern 162, second source Layout patterns 164 and gate structure grooving blast pattern 166.Component shown in layout drawing 1A is to form respectively by elementary boundary 176 and 178 two circular logic units 172 and 174.

Elementary boundary 176 has the top edge 176a (Fig. 1 C) across the centre of power generation configuration pattern 162, passes through power supply cloth Lower edge 176b (Fig. 1 C), the left hand edge 176c Chong Die with gate structure layout patterns 121 (Fig. 1 C) of the centre of office's pattern 164 And the right hand edge 176d (Fig. 1 C) Chong Die with gate structure layout patterns 125.Elementary boundary 178 has across power generation configuration figure The top edge 178a (Fig. 1 C) of the centre of case 162, across the centre of power generation configuration pattern 164 lower edge 178b (Fig. 1 C), with The left hand edge 178c (Fig. 1 C) and the right Chong Die with gate structure layout patterns 129 that gate structure layout patterns 125 are overlapped Edge 178d (Fig. 1 C).In the embodiment shown in figure 1A, a left side of the right hand edge 176d and elementary boundary 178 of elementary boundary 176 Edge 176c is also overlapped.

OD layout patterns 102 can be used to form N well regions, which extends through unit 172 and 174 along direction X；And And OD layout patterns 104 can be used to form p-well region, which extends through unit 172 and 174 along direction X.Power generation configuration Pattern 162 can be used to form the power rail (power rail) that unit 172 and 174 is extended through along direction X, and power rail It is configured to delivery supply voltage；And power generation configuration pattern 164 can be used to form extends through unit 172 and 174 along direction X Power rail, and power rail be configured to delivery ground reference.

Conductive component layout patterns 132 can be used to form conductive component, which passes through by corresponding via arrangements The via plug N well regions that are limited by OD layout patterns 102 of connection and limited by power generation configuration pattern 162 that pattern 150 limits Power rail.Conductive component layout patterns 134 can be used to form conductive component, which passes through by corresponding via arrangements figure The via plug connection p-well region limited by OD layout patterns 104 that case 150 limits and the electricity limited by power generation configuration pattern 164 Source rail.Conductive component layout patterns 136 can be used to form conductive component, and conductive component connection is limited by OD layout patterns 102 N well regions and the p-well region that is limited by OD layout patterns 104.Gate structure layout patterns 123 are located at conductive component layout patterns Between 136 and conductive component layout patterns 132,134, and it can be used for above N well regions and p-well region forming gate structure.

Gate structure layout patterns 121,123,125,127 and 129 extend and had along direction Y can be along direction X The spacing P of measurement_G.Gate structure layout patterns 121,123,125,127 and 129 can be used to form multiple hard mask components or grid Electrod assembly, plurality of gate electrode are made of gate electrode component.In some embodiments, spacing P_GLess than predetermined photoetching technique Spatial resolution, and therefore gate structure layout patterns 121,123,125,127 and 129 can be used for be based on predetermined photoetching skill The multiple Patternized technique of art.

Gate structure layout patterns 123, conductive component layout patterns 132 and conductive component layout patterns 136 can be used for shape At the P-type crystal with source electrode (corresponding to layout patterns 132), drain electrode (layout patterns 136) and grid (layout patterns 123) Pipe.Gate structure layout patterns 123, conductive component layout patterns 134 and conductive component layout patterns 136, which can be used to form, to be had The N-type transistor of source electrode (corresponding to layout patterns 134), drain electrode (layout patterns 136) and grid (layout patterns 123).More than The component enumerated is collectively used for being formed with input terminal (corresponding to layout patterns 123) and output end (layout patterns 136) Phase inverter.Unit 172 is inverter module as a result,.

In element 174, gate structure layout patterns 127 correspond to gate structure layout patterns 123；Conductive component is laid out Pattern 142 corresponds to conductive component layout patterns 132；Conductive component layout patterns 144 correspond to conductive component layout patterns 134；And conductive component layout patterns 146 correspond to conductive component layout patterns 136.Therefore, gate structure layout patterns 127, conductive component layout patterns 142 and conductive component layout patterns 146 can be used to form P-type transistor；Gate structure is laid out Pattern 127, conductive component layout patterns 144 and conductive component layout patterns 146 can be used to form N-type transistor；And unit 174 be also inverter module.

Gate structure layout patterns 125, OD layout patterns 102 and conductive component layout patterns 136 can be used to form with 146 Pseudo- P-type transistor 182.Gate structure layout patterns 125, OD layout patterns 104 and conductive component layout patterns 136 and 146 It can be used to form pseudo- N-type transistor 184.For isolated location 172 and 174,182 He of pseudocone pipe is closed by following operation 184：The gate electrode (corresponding to layout patterns 125) of pseudocone pipe 182 is connected to power rail (layout patterns 162)；It will be pseudo- brilliant The gate electrode (layout patterns 125) of body pipe 184 is connected to power rail (layout patterns 164)；And removal is cut with by gate structure Cut the circular 125 corresponding part gate electrode of layout patterns of layout patterns 166.

Figure 1B is the figure of the section layout design 100B of circuit in accordance with some embodiments.It gives and group those of in Figure 1A The same or analogous reference label of component in the same or analogous Figure 1B of part.Layout designs 100B, which is shown, to be used to help illustrate Another non-limiting examples of the present invention.

Compared with layout designs 100A, in layout designs 100B, by fin structure layout patterns 106 and 108 replace and/or Augment OD layout patterns 102 and 104.Fin structure layout patterns 106 and 108 can be used for above the substrate of circuit forming multiple fins Structure.There is multi-gate framework and otherwise referred to as FinFET according to the transistor of the generation of layout designs 100B manufactures.

Fig. 1 C are the figures of section layout design 100C corresponding with the circuit of Figure 1A or Figure 1B in accordance with some embodiments.It gives It gives and the same or analogous reference label of component in the same or analogous Fig. 1 C of component those of in Figure 1A or Figure 1B.Layout is set Meter 100C summarizes example as shown in FIG. 1A and 1B and de-emphasizes or omit multiple layouts in Figure 1A and Figure 1B Pattern is to help to illustrate the present invention.

As shown in above in association with Figure 1A, close pseudocone pipe 182 corresponding with gate electrode structure layout patterns 125 and 184.In order to reduce the leakage current by pseudocone pipe 182 and 184, pseudocone pipe is subjected to further handling to increase them Threshold voltage.Therefore, layout patterns 192 and 194 are introduced to limit the region for being subjected to electrical characteristics and adjusting technique.In some implementations Example in, layout patterns 192 and 194 can also be used for regulatory function transistor (such as constitute with gate structure layout patterns 123 and The transistor of the p-type and N-type transistor of 127 corresponding phase inverters) electrical characteristics.

In some embodiments, layout patterns 192 and 194 can be used for limiting the opening in mask layer, opening exposure warp The region of technique is adjusted by electrical characteristics.In some embodiments, layout patterns 192 and 194 can be used for limiting the resistance in mask layer Region is kept off, barrier zones will implement the region of electrical characteristics adjusting technique for exposure.In some embodiments, electrical characteristics adjust work Skill can be used for reducing the leakage of the pseudocone pipe of IC or adjust the power of the functional transistor of integrated circuit.In some embodiments In, it includes that threshold voltage adjustments technique or gate structure cut down technique that suitable electrical characteristics, which adjust technique,.In some embodiments, The impacted electrical characteristics that experience adjusts the transistor of technique include corresponding threshold voltage, conducting electric current or the leakage of transistor Electric current.

In some embodiments, layout patterns 192 and 194 have than spacing P_GSmall twice of width W₁.In some implementations In example, width W₁Equal to spacing P_G.In some embodiments, layout patterns 192 and 194 are formed on mask layout layer, and are covered Mould, which is laid out layer, to be had equal to spacing P_GMinimum spacing.

Fig. 2 is the flow chart of the method 200 in accordance with some embodiments for forming layout designs.It should be understood that showing in fig. 2 It can implement additional operation before, during and/or after the method 200 gone out, and one can be described only briefly herein Other a little techniques.

Method 200 starts from operation 210, wherein identifies by one of multiple gate structure layout patterns of layout designs Or one or more of layout designs for occupying of multiple segments region.The regions of one or more identification and IC are subjected to being used for The electrical characteristics for manufacturing IC adjust one or more regions correspondence of technique.In some embodiments, implement electrical characteristics and adjust technique Purpose be to increase or reduce the threshold voltage of corresponding transistor.

Method is carried out to operation 220, wherein is generated in the mask layout layer of layout designs and one or more region weights Folded layout patterns group.Multiple gate structure layout patterns have preset space length.Layout patterns group has equal to preset space length Minimum spacing.In some embodiments, the width of the first layout patterns of layout patterns group or the first cloth of layout patterns group Gap between office's pattern and the second layout patterns is less than twice of the preset space length of multiple gate structure layout patterns.At some In embodiment, the width of the first layout patterns of layout patterns group is the integral multiple of preset space length.In some embodiments, it is laid out Gap between the first layout patterns and the second layout patterns of pattern groups is the integral multiple of preset space length.

Now by by several examples come the embodiment of the method 200 of explanation figure 2.Fig. 3 A to Fig. 3 I are according to some realities Apply the figure of the part of multiple layout designs of example.

Fig. 3 A are the figures of the section layout design 300A in accordance with some embodiments for manufacturing IC.Layout designs 300A can Multiple exemplary layout patterns in mask layout layer for showing to be generated according to method 200.

Layout designs 300A include power generation configuration pattern 302 corresponding with the power generation configuration pattern 164 in Figure 1A to Fig. 1 C, With 104 corresponding first OD layout patterns 304U of OD layout patterns and also corresponding with OD layout patterns 104 and be around electricity Second layout patterns 304L of the mirrored arrangement pattern of the OD layout patterns 304U of source layout pattern 302.With the side of logic unit The corresponding reference line 306 of edge (such as edge 176b and 178b) passes through the centre of power generation configuration pattern 302.

Layout designs 300A further includes multiple gate structure layout patterns 310a-310s and by corresponding with method 200 Process Production layout patterns group 320a-320m.Multiple gate structure layout patterns 310a-310s extend simultaneously along direction Y And with the preset space length P that can be measured along direction X_G.In some embodiments, spacing P_GLess than the space of predetermined photoetching technique Resolution ratio, and therefore gate structure layout patterns 310a-310s can be used for the multiple pattern chemical industry based on predetermined photoetching technique Skill.

Identify the cloth occupied by one or more segment 312a-312m of multiple gate structure layout patterns 310a-310s The regions one or more of office design 300A, so that one or more segment 312a-312m expressions are subjected to electrical characteristics tune The corresponding transistor of section.Will implement electrical characteristics adjust technique for manufacture IC, and layout patterns group 320a-320m with will It is formed in one or more of mask layer opening before implementing electrical characteristics and adjusting technique or stop member corresponds to.

Each layout patterns of layout patterns group 320a-320m all have the width W that can be measured along direction X₁.Width W₁ Less than preset space length P_GTwice.In some embodiments, width W₁Equal to preset space length P_G.Layout patterns group 320a-320m exhibitions Some of many possible layout combinations of the layout patterns of mask layout layer are shown.

In an example, layout patterns 320a have with the elementary boundary indicated by reference line 306 it is Chong Die and not with The edge of any other layout patterns adjoining of mask layout layer.In another example, each layout patterns 320b and 320c is equal With the edge Chong Die with elementary boundary 306, and layout patterns 320b and 320c is in the corresponding sides Chong Die with elementary boundary 306 It is adjacent to each other at edge.

In another example, each layout patterns 320d and 320e all has the edge Chong Die with elementary boundary 306, and The turning of layout patterns 320d is adjacent to each other on the edge Chong Die with elementary boundary 306 with the turning of layout patterns 320e. In another example, in addition to layout patterns 320f and 320g is around other than the reference axis parallel with direction Y is mirror image, layout patterns The arrangement of 320f and 320g is similar with the arrangement of layout patterns 320d and 320e.

In another example, each layout patterns 320h, 320i and 320j all have the side Chong Die with elementary boundary 306 Edge.The angle of turning left of layout patterns 320i is adjacent each other on the edge Chong Die with elementary boundary 306 with the turning of layout patterns 320h It connects；And layout patterns 320i turn right angle and the turning of layout patterns 320j on the edge Chong Die with elementary boundary 306 that This adjoining.Layout patterns 320h and 320j is by with the width W that can be measured along direction X₂Gap separate.Width W₂It is less than Preset space length P_GTwice.In some embodiments, width W₂Equal to preset space length P_G.In another example, in addition to layout patterns 320k, 320l and 320m be except mirror image around the reference axis parallel with direction X, layout patterns 320k, 320l and 320m's Arrangement is similar with the arrangement of layout patterns 320h, 320i and 320j.

Fig. 3 B to Fig. 3 I are the figures of section layout design 300B-300I in accordance with some embodiments.Based on being shown in Fig. 3 A Example, Fig. 3 B to Fig. 3 I show more exemplary layout patterns as combination.It gives and component phase those of in Fig. 3 A The same or analogous reference label of component in same or similar Fig. 3 B to Fig. 3 I.For purposes of clarity, grid knot is omitted The reference label of structure layout patterns and OD layout patterns.

In figure 3b, layout designs 300B includes the layout patterns group 330a- for being used to form mask layer as shown above 330g.Each layout patterns of layout patterns group 330a-330g all have width W₁And it is arranged along reference line 306.Layout Pattern 330a-330g is only adjacent to each other with the corresponding corner of the elementary boundary overlapping indicated by reference line 306.Layout patterns 330a, 330c, 330e and 330g pass through with width W₂Correspondence gap it is separated from one another.Layout patterns 330b, 330d and 330f passes through with width W₂Correspondence gap it is separated from one another.In some embodiments, width W₁With width W₂Equal to grid knot The preset space length P of structure layout patterns_G。

In fig. 3 c, compared with layout designs 300B, in layout designs 300C, layout patterns 330c and 330e are by being laid out Pattern 330h is replaced.Layout patterns 330h with covering three continuous gate structure layout patterns and be suitable for receiving three lists The region of first layout patterns corresponds to, and cell layout's pattern has preset space length P_GWidth.Here, the width of layout patterns 330h W₃Equal to preset space length P_GThree times.

In fig. 3d, compared with layout designs 300C, in layout designs 300D, layout patterns 330b-330f is by being laid out Pattern 330i is replaced.Layout patterns 330i with covering five continuous gate structure layout patterns and be suitable for receiving five lists The region of first layout patterns (the layout patterns 320a in such as Fig. 3 A) corresponds to, and cell layout's pattern has preset space length P_GWidth Degree.Here, the width W of layout patterns 330i₄Equal to preset space length P_GFive times.

In fig. 3e, compared with layout designs 300C, in layout designs 300E, layout patterns 330d and 330f are by being laid out Pattern 330j is replaced.Layout patterns 330j with covering two continuous gate structure layout patterns and be suitable for receiving two lists The region of first layout patterns corresponds to, and cell layout's pattern has preset space length P_GWidth.In addition, layout patterns 330b and 330j By with width W₅Gap separate.Gap between layout patterns 330b and 330j extends in overlying regions, the region with Two continuous gate structure layout patterns are corresponding and are suitable for accommodating Liang Ge cell layouts pattern, and cell layout's pattern has Preset space length P_GWidth.Here, the width W in gap₅Equal to preset space length P_GTwice.

As the variation of embodiment shown in Fig. 3 C and Fig. 3 D, in some embodiments, the width of layout patterns is pre- Determining deviation P_GIntegral multiple.As the variation of embodiment shown in Fig. 3 E, in some embodiments, two layout patterns are by width Degree is preset space length P_GThe gap of integral multiple separate.

For example, in Fig. 3 F, compared with layout designs 300E, in layout designs 300F, layout patterns 330h is by being laid out Pattern 330k is replaced.The width of layout patterns 330k is preset space length P_GTwice, rather than preset space length P_GThree times of (such as cloth Office pattern 330h).The width in the gap between layout patterns 330k and layout patterns 330g is preset space length P_GTwice.Such as In another example shown in Fig. 3 G, compared with layout designs 300E, in layout designs 300G, layout patterns 330b and 330j by Layout patterns 330l is replaced.The width of layout patterns 330l is preset space length P_GSeven times.

Fig. 3 H show and another exemplary layout designs 300H, layout designs 300H include layout patterns 330a, 330m, 330n and 330o.The width of layout patterns 330a is single preset space length P_G.The width of layout patterns 330m is preset space length P_G's Four times.The width of layout patterns 330n is preset space length P_GThree times.The width of layout patterns 330o is preset space length P_GTwo Times.Layout patterns 330n is abutted at elementary boundary 306 with layout patterns 330a and layout patterns 330m.Layout patterns 330m exists It is abutted with layout patterns 330n and layout patterns 330o at elementary boundary 306.Layout patterns 330a and layout patterns 330m by Width is single preset space length P_GGap separate.Layout patterns 330n and layout patterns 330o is preset space length P by width_G Twice of gap separate.

Fig. 3 I show and another exemplary layout designs 300I, layout designs 300I include layout patterns 330l, 330p, 330r and 330g.The width of layout patterns 330g is single preset space length P_G.The width of layout patterns 330l is preset space length P_G's Seven times.The width of layout patterns 330p is preset space length P_GTwice.The width of layout patterns 330r is preset space length P_GTwo Times.Layout patterns 330l is abutted at elementary boundary 306 with layout patterns 330p, 330r and 330g.Layout patterns 330p and cloth Office pattern 330r is single preset space length P by width_GGap separate.Layout patterns 330r and layout patterns 330g are by width It is single preset space length P_GGap separate.

Fig. 4 A are the part IC in accordance with some embodiments that can be used for illustrating that the first example thresholds voltage adjusts technique The sectional view of 400A.Fig. 4 A are intercepted along the reference surface for not cutting through corresponding gate structure.

IC 400A include substrate 410；From the upper surface 410a of substrate 410 multiple fin structures 412,414 and 416 outstanding； Above the upper surface 410a of substrate 410 and partly cover the separation layer 422 of fin structure 412,414 and 416；And position Mask layer 424 above separation layer 422 and fin structure 412 and 416.Multiple components in IC 400A are arranged in first crystal In area under control 432, second transistor area 434 and third transistor area 436.First crystal area under control 432 corresponds to the crystalline substance of the first kind Body pipe, and second transistor area 434 and third transistor area 436 correspond to the transistor of Second Type.In some embodiments, The transistor of the first kind refers to N-type transistor, and the transistor of Second Type refers to P-type transistor.In some implementations In example, the transistor of the first kind refers to P-type transistor, and the transistor of Second Type refers to N-type transistor.

Mask layer 424, which has, to be limited in mask layer 424 and the opening of expose portion fin structure 414 426.In some realities It applies in example, mask layer 424 is formed according to mask layout layer, which includes the layout patterns group 320a- in Fig. 3 A Layout patterns group 330a-330h in 320m Fig. 3 B to Fig. 3 G.In some embodiments, according to layout patterns group 320a- 320m or 330a-330h limits opening 426.In Figure 4 A, the transistor formed in transistor area 434 and 436 had into phase Same type.However, the transistor formed in transistor area 434 is exposed by opening 426, and therefore will handle in transistor The transistor formed in area 434 is to adjust its electrical characteristics.

For example, implementing injection technology 440 to adjust the Effective Doping concentration at fin structure 414.In some embodiments, it notes Enter technique 440 to increase or reduce at the fin structure 414 for the transistor that can be used to form same type and homologue fin structure 416 The Effective Doping concentration at place.As a result, the threshold voltage of the transistor of generation at transistor area 434 in transistor area 436 The threshold voltage of transistor is different.In some embodiments, if the transistor generated in region 434 and 436 is N-type crystal Pipe, then the p-type doping concentration for increasing fin structure 414 generates smaller threshold voltage, and the p-type doping for reducing fin structure 414 is dense Degree generates larger threshold voltage.In some embodiments, if the transistor generated in region 434 and 436 is P-type crystal Pipe, then the n-type doping concentration for increasing fin structure 414 generates smaller threshold voltage, and the n-type doping for reducing fin structure 414 is dense Degree generates larger threshold voltage.

Fig. 4 B are the part IC in accordance with some embodiments that can be used for illustrating that the second example thresholds voltage adjusts technique The sectional view of 400B.Give reference label identical with the component in the same or analogous Fig. 4 B of the component in Fig. 4 A.Along not The reference surface for cutting through corresponding gate structure 452,454 and 456 intercepts Fig. 4 B.

Compared with IC 400A, instead of implementing injection technology 440 in opening 426, gate electrode structure 454 is formed to have The material and/or structure different from those of electrode structure 452 and 456 material and/or structure.In some embodiments, grid electricity The material of pole structure 454 has the work function metal different from the work function metal of gate electrode 456.As a result, the production at transistor area 434 The threshold voltage of raw transistor is different from the threshold voltage of the transistor in transistor area 436.

In some embodiments, implement technique as shown in Figure 4 A and 4 B shown in FIG. to adjust the threshold value electricity of the transistor in IC Pressure.In some embodiments, only implement technique one of as shown in Figure 4 A and 4 B shown in FIG. to adjust the threshold of the transistor in IC Threshold voltage.

It in some embodiments, will be according to corresponding with layout patterns 192 and 194 when implementing threshold voltage adjustments technique Layout patterns, exposure or blocking and the pseudocone pipe 182 and 184 corresponding pseudocone pipes in Figure 1A to Fig. 1 C.

Fig. 5 A to Fig. 5 B are the part IC 500 in accordance with some embodiments that can be used for illustrating gate structure and cut down technique Sectional view.

In fig. 5, IC 500 includes substrate 510, the polysilicon layer 520 above substrate 510, is located at polysilicon layer The multiple hard mask component 532a-532f and the mask layer 542 above polysilicon layer 520 of 520 tops and hard mask portion Part 532a-532c and 532e-532f.According to multiple grid of such as layout patterns 121-129 (Fig. 1) or 310a-310s (Fig. 3 A) Pole topology layout pattern carrys out hard mask component 532a-532f.Mask layer 542, which has, is limited to opening in mask layer 542 Mouth 544, and according to layout patterns group (such as layout patterns 320a-320m (Fig. 3 A) or 330a-330h (Fig. 3 B to figure Mask layout layer 3G)) forms opening 544.In fig. 5, implement the first etch process 550 to reduce hard mask component 532d Width.

In figure 5B, after the first etch process, hard mask component 532d is cut down with as with the hard of smaller width Mask parts 532d '.Mask layer 542 is removed, and then implements the second etch process 550 to pattern polysilicon layer 520 At multiple polysilicon features 522a-522f.Polysilicon features 522a-522f can be used as gate structure or be subjected to subsequent grid replacing Change the dummy gate structure of technique.Since the width of polysilicon features 522d is less than other polysilicon features 522a-522c and 522e- The width of 522f, thus the transistor ratio of generation corresponding with polysilicon features 522d and polysilicon features 522a-522c and The transistor of the same type of the corresponding generations of 522e-522f has the faster speed of service.

It in some embodiments, will be according to corresponding with layout patterns 192 and 194 when implementing gate structure reduction technique Layout patterns blocking and the pseudocone pipe 182 and 184 corresponding pseudocone pipes in Figure 1A to Fig. 1 C.

Fig. 6 is the flow chart of the method 600 of manufacture IC in accordance with some embodiments.It should be understood that the side being shown in FIG. 6 It can implement additional operation before, during and/or after method 600, and can be described only briefly herein some other Technique.

Method 600 starts from operation 610, wherein according to multiple gate structure layout patterns (such as layout patterns 121- 129 (Fig. 1) or 310a-310s (Fig. 3 A)) form multiple patterned components.Use the multiple pattern based on predetermined photoetching technique Chemical industry skill forms multiple patterned component.Therefore, multiple patterned components are along corresponding with the direction Y in Fig. 3 A First direction extends, and has can be measured along the direction X and spacing P in Fig. 3 A_GCorresponding preset space length.In some realities It applies in example, spacing P_GLess than the spatial resolution of predetermined photoetching technique.In some embodiments, multiple patterned components and figure Hard mask component 532a-532f in 5A is corresponded to, or with 522a-522f pairs of polysilicon features being formed according to hard mask component It answers.

Technique is carried out to operation 620, wherein forms mask layer above multiple patterned components.Mask layer includes limit It is scheduled on one or more of mask layer opening, and one or more opening exposes one with multiple patterned components Or the corresponding one or more regions of multiple segments.In some embodiments, mask layer is corresponding with the mask layer 542 in Fig. 5 A, Mask layer 542 has the opening 544 being limited in mask layer 542.According to the layout patterns group of mask layout layer, (such as Fig. 3 A are extremely Layout patterns 320a-320m or 330a-330l in Fig. 3 G) limit one or more opening.Therefore, in some embodiments In, the minimum spacing of one or more opening is equal to the preset space length P of multiple patterned components_G。

Technique is carried out to operation 630, wherein is implemented electrical characteristics to exposed one or more regions and is adjusted technique.One In a little embodiments, it includes threshold voltage adjustments technique or such as combination as shown in conjunction with Fig. 4 A and Fig. 4 B that electrical characteristics, which adjust technique, Gate structure shown in Fig. 5 A and Fig. 5 B cuts down technique.

Fig. 7 is the block diagram of layout designs system 700 in accordance with some embodiments.Layout designs system 700 can be used for implementing Method disclosed in Fig. 2, and layout designs system 700 is explained further in conjunction with Fig. 1 and Fig. 3 A to Fig. 3 G.

System 700 includes hardware processor 710, non-transitory computer-readable storage media 720, is connected to external circuit Input/output interface 730 and pass through the socket 740 communicatively connected to each other of bus 750.

Utilize 722 code storage medium 720 of executable instruction set.Processor 710 is configured to execute executable instruction set 722 So that system 700 can be used for implementing some or all operations as shown in Figure 2.In some embodiments, processor 710 is center Processing unit (CPU), multiprocessor, distributed processing system(DPS), application-specific integrated circuit (ASIC) and/or suitable processing unit.

In some embodiments, computer readable storage medium 720 be electronics, it is magnetic, optical, electromagnetism, red Outer and/or semiconductor system (or device or equipment).For example, computer readable storage medium 720 is including semiconductor or admittedly Phase memory, tape, mobile computer floppy disk, random access memory (RAM), read-only memory (ROM), hard disc and/or CD.In some embodiments using CD, computer readable storage medium 720 includes compact disc-ROM (CD- ROM), disk read/write (CD-R/W) and/or digital video disk (DVD).

In some embodiments, storage medium 720 stores executable instruction set 722, and executable instruction set 722 is configured to make System 700 implements method as shown in Figure 2.In some embodiments, storage medium 720 is also required for storage implementation method 200 Information or the information that is generated during implementation, such as identification piece of layout designs file 724, gate structure layout patterns Section 726 and/or any intermediate data 728.

Socket 740 allows system 700 to be communicated with network 760, the connection of wherein one or more other computer systems To network 760.Socket 740 includes the wireless network interface of such as BLUETOOTH, WIFI, WIMAX, GPRS or WCDMA； Or the cable network interface of such as ETHERNET, USB or IEEE-1394.In some embodiments, in more than two systems The method for executing Fig. 2, and executable instruction or layout information are exchanged between different systems 700 by network 760.

According to one embodiment, a kind of method forming the layout designs for manufacturing integrated circuit (IC) is disclosed.It should Method includes identifying in layout designs that one or more segments by multiple gate structure layout patterns of layout designs occupy One or more regions；And generate the layout patterns group Chong Die with one or more regions of identification.One or more areas Domain be subjected to for manufacture IC electrical characteristics adjust one or more regions of IC of technique it is corresponding.Multiple gate structure layouts Case extends and along a first direction with the preset space length that can be measured along second direction.Preset space length is less than predetermined photoetching skill The spatial resolution of art.Layout patterns group and one or more by formation in the mask layer before implementing electrical characteristics and adjusting technique A opening corresponds to.First layout patterns of layout patterns group have the width that can be measured along second direction, and the first layout The width of pattern is less than twice of preset space length.

According to another embodiment, a kind of method forming the layout designs for manufacturing integrated circuit (IC) is disclosed.It should Method includes identifying in layout designs that one or more segments by multiple gate structure layout patterns of layout designs occupy One or more regions；And generate the layout patterns group Chong Die with one or more regions of identification.One or more areas Domain be subjected to for manufacture IC electrical characteristics adjust one or more regions of IC of technique it is corresponding.Multiple gate structure layouts Case extends and along a first direction with the preset space length that can be measured along second direction.Preset space length is less than predetermined photoetching skill The spatial resolution of art.Layout patterns group and one or more by formation in the mask layer before implementing electrical characteristics and adjusting technique A opening corresponds to.The first layout patterns and the second layout patterns of layout patterns group are by the first gap separation along second direction It opens, and can be less than along the width in the first gap that second direction measures twice of preset space length.

According to another embodiment, a kind of layout designs for manufacturing integrated circuit (IC) are disclosed.The layout designs packet Include the first layout layer and the second layout layer.First layout layer includes multiple gate structure layout patterns.Multiple gate structure layouts Pattern extends and along a first direction with the preset space length that can be measured along second direction, and preset space length is less than predetermined The spatial resolution of photoetching technique.Second layout layer includes the mask layout pattern group of open region arrangement based on one or more. One or more open regions with and be subjected to electrical characteristics and adjust the corresponding multiple gate structures of one or more gate structures of technique One or more of layout patterns are overlapped.First mask layout pattern of mask layout pattern group has can be along second direction The width of measurement, and the width of the first mask layout pattern is equal to preset space length.

Foregoing has outlined the features of several embodiments so that the side of the present invention may be better understood in those skilled in the art Face.It should be appreciated by those skilled in the art that they can be easily using designing or modifying based on the present invention for real It grants the identical purpose of embodiment defined herein and/or realizes other process and structures of identical advantage.People in the art Member it should also be appreciated that this equivalent constructions without departing from the spirit and scope of the present invention, and without departing substantially from the present invention essence In the case of refreshing and range, they can make a variety of variations, replace and change herein.

In the above-mentioned methods, wherein the second layout patterns of the layout patterns group have to be surveyed along the second direction The width of amount, and the integral multiple that the width of second layout patterns is the preset space length.

In the above-mentioned methods, wherein the electrical characteristics adjust technique be used to reduce the IC pseudocone pipe leakage or Adjust the power of the functional transistor of the IC.

In the above-mentioned methods, wherein the layout patterns group includes the second layout patterns；First layout patterns have The edge Chong Die with the elementary boundary of the layout designs；And second layout patterns have the institute with the layout designs State the edge of elementary boundary overlapping.

In the above-mentioned methods, wherein the layout patterns group includes the second layout patterns；First layout patterns have The edge Chong Die with the elementary boundary of the layout designs；And second layout patterns have the institute with the layout designs State the edge of elementary boundary overlapping；Wherein, the edge of the edge of first layout patterns and second layout patterns is each other It is adjacent.

In the above-mentioned methods, wherein the layout patterns group includes the second layout patterns；First layout patterns have The edge Chong Die with the elementary boundary of the layout designs；And second layout patterns have the institute with the layout designs State the edge of elementary boundary overlapping；Wherein, it is located at the of first layout patterns on the edge of first layout patterns One turning and the turning of second layout patterns on the edge of second layout patterns are adjacent to each other.

In the above-mentioned methods, wherein the layout patterns group includes the second layout patterns；First layout patterns have The edge Chong Die with the elementary boundary of the layout designs；And second layout patterns have the institute with the layout designs State the edge of elementary boundary overlapping；Wherein, it is located at the of first layout patterns on the edge of first layout patterns One turning and the turning of second layout patterns on the edge of second layout patterns are adjacent to each other；Wherein, institute It further includes third layout patterns to state layout patterns group；The third layout patterns have the element sides with the layout designs The edge of boundary's overlapping；And the second turning and position of first layout patterns on the edge of first layout patterns It is adjacent to each other in the turning of the third layout patterns on the edge of the third layout patterns.

In the above-mentioned methods, wherein it includes that threshold voltage adjustments technique or gate structure are cut that the electrical characteristics, which adjust technique, Subtract technique.

In the above-mentioned methods, wherein the width in first gap is equal to the preset space length.

In the above-mentioned methods, wherein the third layout patterns of the layout patterns group and first layout patterns are by edge The second gap for the second direction separates, and the width in second gap that can be measured along the second direction For the integral multiple of the preset space length.

In the above-mentioned methods, wherein first layout patterns have the width that can be measured along the second direction, and And the integral multiple that the width of first layout patterns is the preset space length.

In the above-mentioned methods, wherein the layout patterns group includes third layout patterns；First layout patterns have The edge Chong Die with the elementary boundary of the layout designs；And the third layout patterns have the institute with the layout designs State the edge of elementary boundary overlapping.

In the above-mentioned methods, wherein the layout patterns group includes third layout patterns；First layout patterns have The edge Chong Die with the elementary boundary of the layout designs；And the third layout patterns have the institute with the layout designs State the edge of elementary boundary overlapping；Wherein, the edge of the edge of first layout patterns and the third layout patterns is each other It is adjacent.

In the above-mentioned methods, wherein the layout patterns group includes third layout patterns；First layout patterns have The edge Chong Die with the elementary boundary of the layout designs；And the third layout patterns have the institute with the layout designs State the edge of elementary boundary overlapping；Wherein, it is located at the of first layout patterns on the edge of first layout patterns One turning and the turning of the third layout patterns on the edge of the third layout patterns are adjacent to each other.

In the above-mentioned methods, wherein the layout patterns group includes third layout patterns；First layout patterns have The edge Chong Die with the elementary boundary of the layout designs；And the third layout patterns have the institute with the layout designs State the edge of elementary boundary overlapping；Wherein, it is located at the of first layout patterns on the edge of first layout patterns One turning and the turning of the third layout patterns on the edge of the third layout patterns are adjacent to each other；Wherein, institute It further includes the 4th layout patterns to state layout patterns group；4th layout patterns have the element sides with the layout designs The edge of boundary's overlapping；And the second turning and position of first layout patterns on the edge of first layout patterns It is adjacent to each other in the turning of the 4th layout patterns on the edge of the 4th layout patterns.

In the above-mentioned methods, wherein the second mask layout pattern of the mask layout pattern group has can be along described The width that second direction measures, and the integral multiple that the width of the second mask layout pattern is the preset space length.

Claims

1. a kind of method of layout designs of formation for manufacturing integrated circuit (IC), the method includes：

Identify that the layout occupied by one or more segments of multiple gate structure layout patterns of the layout designs is set One or more of meter region, one or more of regions and the one of the integrated circuit for being subjected to electrical characteristics adjusting technique A or multiple regions correspond to, and the electrical characteristics adjust technique for manufacturing the integrated circuit, the multiple gate structure layout Pattern extends and along a first direction with the preset space length that can be measured along second direction, and the preset space length is less than The spatial resolution of predetermined photoetching technique；And

Generate the layout patterns group Chong Die with one or more regions of the identification, the layout patterns group and described in implementation Electrical characteristics will be formed in one or more of mask layer opening and correspond to before adjusting technique, the first cloth of the layout patterns group Office's pattern has the width that can be measured along the second direction, and the width of first layout patterns is less than described make a reservation for Twice of spacing.

2. the method for layout designs of the formation according to claim 1 for manufacturing integrated circuit (IC), wherein the cloth Second layout patterns of office's pattern groups have the width measured along the second direction, and the width of second layout patterns Degree is the integral multiple of the preset space length.

3. the method for layout designs of the formation according to claim 1 for manufacturing integrated circuit (IC), wherein the electricity Characteristic adjusts the leakage of pseudocone pipe of the technique for reducing the integrated circuit or adjusts the functional crystal of the integrated circuit The power of pipe.

4. the method for layout designs of the formation according to claim 1 for manufacturing integrated circuit (IC), wherein

The layout patterns group includes the second layout patterns；

First layout patterns have the edge Chong Die with the elementary boundary of the layout designs；And

Second layout patterns have the edge Chong Die with the elementary boundary of the layout designs.

5. the method for layout designs of the formation for manufacturing integrated circuit (IC) according to claim 4, wherein described the The edge of the edge of one layout patterns and second layout patterns is adjacent to each other.

6. the method for layout designs of the formation according to claim 4 for manufacturing integrated circuit (IC), wherein be located at institute State the first turning of first layout patterns on the edge of the first layout patterns and the side for being located at second layout patterns The turning of second layout patterns on edge is adjacent to each other.

7. the method for layout designs of the formation according to claim 6 for manufacturing integrated circuit (IC), wherein

The layout patterns group further includes third layout patterns；

The third layout patterns have the edge Chong Die with the elementary boundary of the layout designs；And

Second turning of first layout patterns on the edge of first layout patterns be located at the third cloth The turning of the third layout patterns on the edge of office's pattern is adjacent to each other.

8. the method for layout designs of the formation according to claim 1 for manufacturing integrated circuit (IC), wherein the electricity It includes that threshold voltage adjustments technique or gate structure cut down technique that characteristic, which adjusts technique,.

9. a method of the layout designs for manufacturing integrated circuit (IC) are formed, the method includes：

Generate the layout patterns group Chong Die with one or more regions of the identification, the layout patterns group and described in implementation Electrical characteristics will be formed in one or more of mask layer opening and correspond to before adjusting technique, the first cloth of the layout patterns group Office's pattern and the second layout patterns, and can be along the second directions by being separated along the first gap of the second direction The width in first gap measured is less than twice of the preset space length.

10. the method for layout designs of the formation according to claim 9 for manufacturing integrated circuit (IC), wherein described The width in the first gap is equal to the preset space length.

11. the method for layout designs of the formation according to claim 9 for manufacturing integrated circuit (IC), wherein described The third layout patterns of layout patterns group and first layout patterns by being separated along the second gap of the second direction, And it can be along the integral multiple that the width in second gap that the second direction measures is the preset space length.

12. the method for layout designs of the formation according to claim 9 for manufacturing integrated circuit (IC), wherein described First layout patterns have the width that can be measured along the second direction, and the width of first layout patterns is described The integral multiple of preset space length.

13. the method for layout designs of the formation according to claim 9 for manufacturing integrated circuit (IC), wherein described Electrical characteristics adjust the leakage of pseudocone pipe of the technique for reducing the integrated circuit or adjust the function crystalline substance of the integrated circuit The power of body pipe.

14. the method for layout designs of the formation according to claim 9 for manufacturing integrated circuit (IC), wherein

The layout patterns group includes third layout patterns；

The third layout patterns have the edge Chong Die with the elementary boundary of the layout designs.

15. the method for layout designs of the formation according to claim 14 for manufacturing integrated circuit (IC), wherein described The edge of the edge of first layout patterns and the third layout patterns is adjacent to each other.

16. the method for layout designs of the formation according to claim 14 for manufacturing integrated circuit (IC), wherein be located at First turning of first layout patterns on the edge of first layout patterns with positioned at the third layout patterns The turning of the third layout patterns on edge is adjacent to each other.

17. the method for layout designs of the formation according to claim 16 for manufacturing integrated circuit (IC), wherein

The layout patterns group further includes the 4th layout patterns；

4th layout patterns have the edge Chong Die with the elementary boundary of the layout designs；And

Second turning of first layout patterns on the edge of first layout patterns be located at the 4th cloth The turning of the 4th layout patterns on the edge of office's pattern is adjacent to each other.

18. the method for layout designs of the formation according to claim 9 for manufacturing integrated circuit (IC), wherein described It includes that threshold voltage adjustments technique or gate structure cut down technique that electrical characteristics, which adjust technique,.

19. layout designs structure of the one kind for manufacturing integrated circuit (IC), including：

First layout layer, including multiple gate structure layout patterns, the multiple gate structure layout patterns are along a first direction Extend and there is the preset space length that can be measured along second direction, and the preset space length is less than the sky of predetermined photoetching technique Between resolution ratio；And

Second layout layer, including the mask layout pattern group of open region arrangement based on one or more, it is one or more of to open Mouth region is Chong Die with the one or more of the multiple gate structure layout patterns, one of the multiple gate structure layout patterns Or it is multiple corresponding with electrical characteristics adjusting one or more gate structures of technique are subjected to, the first of the mask layout pattern group covers Mould layout patterns have the width that can be measured along the second direction, and the width of the first mask layout pattern is equal to The preset space length.

20. the layout designs structure according to claim 19 for manufacturing integrated circuit (IC), wherein the mask cloth Second mask layout pattern of office's pattern groups has the width that can be measured along the second direction, and second layout The width of case is the integral multiple of the preset space length.