CN105427434A - Buffer circuit-based wireless voice recognition access control system - Google Patents
Buffer circuit-based wireless voice recognition access control system Download PDFInfo
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- CN105427434A CN105427434A CN201510963548.0A CN201510963548A CN105427434A CN 105427434 A CN105427434 A CN 105427434A CN 201510963548 A CN201510963548 A CN 201510963548A CN 105427434 A CN105427434 A CN 105427434A
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- G—PHYSICS
- G07—CHECKING-DEVICES
- G07C—TIME OR ATTENDANCE REGISTERS; REGISTERING OR INDICATING THE WORKING OF MACHINES; GENERATING RANDOM NUMBERS; VOTING OR LOTTERY APPARATUS; ARRANGEMENTS, SYSTEMS OR APPARATUS FOR CHECKING NOT PROVIDED FOR ELSEWHERE
- G07C9/00—Individual registration on entry or exit
- G07C9/00174—Electronically operated locks; Circuits therefor; Nonmechanical keys therefor, e.g. passive or active electrical keys or other data carriers without mechanical keys
- G07C9/00563—Electronically operated locks; Circuits therefor; Nonmechanical keys therefor, e.g. passive or active electrical keys or other data carriers without mechanical keys using personal physical data of the operator, e.g. finger prints, retinal images, voicepatterns
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- G—PHYSICS
- G07—CHECKING-DEVICES
- G07C—TIME OR ATTENDANCE REGISTERS; REGISTERING OR INDICATING THE WORKING OF MACHINES; GENERATING RANDOM NUMBERS; VOTING OR LOTTERY APPARATUS; ARRANGEMENTS, SYSTEMS OR APPARATUS FOR CHECKING NOT PROVIDED FOR ELSEWHERE
- G07C9/00—Individual registration on entry or exit
- G07C9/00174—Electronically operated locks; Circuits therefor; Nonmechanical keys therefor, e.g. passive or active electrical keys or other data carriers without mechanical keys
- G07C9/00571—Electronically operated locks; Circuits therefor; Nonmechanical keys therefor, e.g. passive or active electrical keys or other data carriers without mechanical keys operated by interacting with a central unit
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- G—PHYSICS
- G07—CHECKING-DEVICES
- G07C—TIME OR ATTENDANCE REGISTERS; REGISTERING OR INDICATING THE WORKING OF MACHINES; GENERATING RANDOM NUMBERS; VOTING OR LOTTERY APPARATUS; ARRANGEMENTS, SYSTEMS OR APPARATUS FOR CHECKING NOT PROVIDED FOR ELSEWHERE
- G07C2209/00—Indexing scheme relating to groups G07C9/00 - G07C9/38
- G07C2209/02—Access control comprising means for the enrolment of users
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Abstract
The invention discloses a buffer circuit-based wireless voice recognition access control system, which mainly consists of a central processing unit, a second wireless transmission module, an A/D (analog to digital) switching circuit, an access control driving circuit, an alarm module, a display module, a memory, a first wireless transmission module, a sound sensor, an access control, a signal processing circuit, a PC (personal computer) and the like, wherein the A/D switching circuit, the access control driving circuit, the alarm module, the display module, the memory and the first wireless transmission module are respectively connected with the central processing unit; the sound sensor is connected with the A/D switching circuit; the access control is connected with the access control driving circuit; the signal processing circuit is connected with the second wireless transmission module; the PC is connected with the signal processing circuit. According to the buffer circuit-based wireless voice recognition access control system disclosed by the invention, data transmission is performed by adopting a wireless manner to realize access control and the information exchange of the PC, therefore the construction difficulty is reduced, and an administrator is helped to transform an access control network in the future; the buffer circuit-based wireless voice recognition access control system disclosed by the invention is provided with a buffer circuit; the buffer circuit can be used for smoothly inputting a signal into the central processing unit, so that the phenomenon that signal processing and recognition of the central processing unit is influenced by signal fluctuation is avoided, and the recognition precision of the buffer circuit-based wireless voice recognition access control system disclosed by the invention is improved.
Description
Technical field
The present invention relates to a kind of gate control system, specifically refer to a kind of wireless speech identification gate control system based on buffer circuit.
Background technology
Gate control system is new-modernization management of public safety system, it integrates microcomputer automatic identification technology and modern safety management measure, relating to many new technologies such as electronics, machinery, optics, computer technology, the communication technology and biotechnology, is the effective guarantee that important department gateway realizes safety precaution management.Existing gate control system mostly is wire transmission mode, the communication of each controller and PC is generally undertaken by RS-232, RS-485 or CAN, and the physical connection between equipment is complicated, network rebuilding constructional difficulties is loaded down with trivial details especially for wiring newly-increased Adding User.
Summary of the invention
The object of the invention is to overcome existing gate control system is wire transmission mode, and the physical connection between its equipment is complicated, and the defect of network rebuilding constructional difficulties, provides a kind of wireless speech identification gate control system based on buffer circuit.
Object of the present invention is achieved through the following technical solutions: a kind of wireless speech identification gate control system based on buffer circuit, primarily of central processing unit, second wireless transport module, the A/D change-over circuit be connected with central processing unit respectively, gate inhibition's driving circuit, alarm module, display module, storer and the first wireless transport module, the sound transducer be connected with A/D change-over circuit, the gate inhibition be connected with gate inhibition's driving circuit, the signal processing circuit be connected with the second wireless transport module, the PC be connected with signal processing circuit, and the printer to be connected with PC forms, described first wireless transport module is connected with the second wireless transport module by wireless network, in order to better implement the present invention, the present invention is also serially connected with buffer circuit between A/D change-over circuit and central processing unit.
Further, described buffer circuit is by amplifier P1, amplifier P2, amplifier P3, triode VT5, one end is connected with the positive pole of amplifier P1, the other end then forms the resistance R13 of the input end of this buffer circuit, P pole is connected with the emitter of triode VT5, the diode D4 that N pole is then connected with the output terminal of amplifier P3 after resistance R16, be serially connected in the resistance R15 between the positive pole of amplifier P2 and output terminal, positive pole is connected with the output terminal of amplifier P2, the electric capacity C7 that negative pole is then connected with the negative pole of amplifier P1 after resistance R14, P pole is connected with the output terminal of amplifier P1, the diode D5 that N pole is then connected with the negative pole of amplifier P1, N pole is connected with the negative pole of amplifier P3, the diode D6 that P pole is then connected with the negative pole of amplifier P1, be serially connected in the resistance R17 between the output terminal of amplifier P3 and the negative pole of electric capacity C7, and one end is connected with the output terminal of amplifier P2, the resistance R18 that the other end then forms the output terminal of this buffer circuit forms, the base stage of described triode VT5 is connected with the positive pole of amplifier P1, and its collector is then connected with the output terminal of amplifier P1, and its emitter is then connected with the positive pole of amplifier P3, the negative pole of described amplifier P2 is connected with the output terminal of amplifier P1, the input end of described buffer circuit is connected with the output terminal of A/D change-over circuit, and its output terminal is then connected with central processing unit.
Described signal processing circuit by signal compensation circuit, the phase lock circuitry be connected with signal compensation circuit, and the filtering circuit be connected with phase lock circuitry forms; The input end of described signal compensation circuit is connected with the second wireless transport module, and the output terminal of filtering circuit is then connected with PC.
Described signal compensation circuit is by triode VT1, field effect transistor MOS1, positive pole is connected with the grid of field effect transistor MOS1 after resistance R3, the polar capacitor C1 of minus earth, one end is connected with the positive pole of polar capacitor C1, the resistance R2 of other end ground connection, negative pole is connected with the grid of field effect transistor MOS1, positive pole then forms the polar capacitor C2 of the input end of this signal compensation circuit, one end is connected with the base stage of triode VT1, the resistance R4 that the other end is then connected with the positive pole of polar capacitor C1 after resistance R1, N pole is connected with the source electrode of field effect transistor MOS1, the diode D1 of P pole ground connection, and positive pole is connected with the collector of triode VT1, the polar capacitor C3 that negative pole is then connected with the N pole of diode D1 forms, the source electrode of described field effect transistor MOS1 is connected with phase lock circuitry, and its drain electrode is then connected with the base stage of triode VT1, the emitter of described triode VT1 is connected with phase lock circuitry, the tie point of described resistance R1 and resistance R4 connects 12V voltage.
Described phase lock circuitry is by phase-locked chip U1, triode VT2, triode VT3, field effect transistor MOS2, be serially connected in the resistance R5 between the base stage of triode VT2 and the base stage of triode VT3, P pole is connected with the drain electrode of field effect transistor MOS2, the diode D3 that N pole is then connected with the collector of triode VT2 after resistance R6, be serially connected in the resistance R8 between the source electrode of field effect transistor MOS2 and the COMP pin of phase-locked chip U1, P pole is connected with the collector of triode VT3, the diode D2 that N pole is then connected with the source electrode of field effect transistor MOS2 after resistance R7, positive pole is connected with the FB pin of phase-locked chip U1, the electric capacity C4 that negative pole is then connected with the N pole of diode D2, positive pole is connected with the DRV pin of phase-locked chip U1, the electric capacity C5 of minus earth, one end is connected with the N pole of diode D3, the resistance R9 that the other end is then connected with the VSS pin of phase-locked chip U1, and one end is connected with the N pole of diode D3, the resistance R10 that the other end is then connected with the VDD pin of phase-locked chip U1 forms, the collector of described triode VT2 is connected with the emitter of triode VT1, and its emitter is then connected with the emitter of triode VT3, the described base stage of triode VT3 is connected with the source electrode of field effect transistor MOS1, and its emitter is then connected with the grid of field effect transistor MOS2, the TOFF pin of described phase-locked chip U1 is all connected with filtering circuit with CS pin.
Described filtered electrical routing amplifier P, triode VT4, be serially connected in the resistance R11 between the TOFF pin of phase-locked chip U1 and the positive pole of amplifier P, be serially connected in the resistance R12 between the CS pin of phase-locked chip U1 and the base stage of triode VT4, and the electric capacity C6 that positive pole is connected with the emitter of triode VT4, negative pole is then connected with the output terminal of amplifier P forms; The emitter of described triode VT4 is connected with the negative pole of amplifier P, its grounded collector; The output terminal of described amplifier P forms the output terminal of this filtering circuit.
Described phase-locked chip U1 is UCT4392 type integrated chip.
The present invention comparatively prior art compares, and has the following advantages and beneficial effect:
(1) the present invention adopts wireless mode to carry out data transmission, realizes the message exchange of access control and PC, decreases difficulty of construction, be beneficial in the future supvr to the transformation of gate inhibition's network.
(2) the present invention can process the signal after wireless transmission, thus improves the accuracy of the data that PC receives.
(4) the present invention is provided with buffer circuit, and it can make the input central processing unit of signal smoothing, avoids signal fluctuation and affect central processing unit processing signal, identifying, thus improves accuracy of identification of the present invention.
Accompanying drawing explanation
Fig. 1 is one-piece construction block diagram of the present invention.
Fig. 2 is the structural drawing of signal processing circuit of the present invention.
Fig. 3 is the structural drawing of buffer circuit of the present invention.
Embodiment
Below in conjunction with embodiment, the present invention is described in further detail, but embodiments of the present invention are not limited to this.
Embodiment
As shown in Figure 1, a kind of wireless speech identification gate control system based on buffer circuit of the present invention, primarily of central processing unit, second wireless transport module, the buffer circuit be connected with central processing unit respectively, gate inhibition's driving circuit, alarm module, display module, storer and the first wireless transport module, the A/D change-over circuit be connected with buffer circuit, the sound transducer be connected with A/D change-over circuit, the gate inhibition be connected with gate inhibition's driving circuit, the signal processing circuit be connected with the second wireless transport module, the PC be connected with signal processing circuit, and the printer to be connected with PC forms, described first wireless transport module is connected with the second wireless transport module by wireless network.
This sound transducer is arranged near gate inhibition, for collected sound signal.A/D change-over circuit is used for that the simulating signal that sound transducer exports is converted to electric signal and exports to buffer circuit.This buffer circuit then for processing signal, the input central processing unit enabling signal level and smooth.This central processing unit is for controlling the running of whole system, and its SPCE061A single-chip microcomputer preferentially adopting Taiwan Ling Yang company to produce realizes.Storer is then for storing the voice signal that can pass in and out gate inhibition personnel in advance; Alarm module adopts traditional hummer, for voice signal coupling not pair time sound the alarm.Display module is then for simultaneous display recognition result, and it uses display to realize, gate inhibition's driving circuit opening then for access control.First wireless transport module and the second wireless transport module are used for carrying out wireless transmission to signal, and the preferential PTR2000 type wireless transport module that adopts realizes.Signal processing circuit is used for processing to the received signal.This PC is then for storing signal; Printer is then for printing data-signal.The IOA2 pin of this SPCE061A type single-chip microcomputer is connected with the output terminal of buffer circuit, its IOA1 pin is then connected with the input end of gate inhibition's driving circuit, its IOA6 pin is then connected with storer, its IOA5 pin is then connected with display module, its DAC1 pin is then connected with alarm module, and its IOA3 pin is then connected with the DI pin of the first wireless transport module.The DI pin of described second wireless transport module is then connected with signal processing circuit.Described A/D change-over circuit, gate inhibition's driving circuit, storer, sound transducer, PC and printer all adopt prior art to realize.
As shown in Figure 2, described signal processing circuit by signal compensation circuit, the phase lock circuitry be connected with signal compensation circuit, and the filtering circuit be connected with phase lock circuitry forms.The input end of described signal compensation circuit is connected with the DI pin of the second wireless transport module, and the output terminal of filtering circuit is then connected with PC.
Described signal compensation circuit by triode VT1, field effect transistor MOS1, resistance R1, resistance R2, resistance R3, resistance R4, polar capacitor C1, polar capacitor C2, polar capacitor C3 and diode D1.
Wherein, the positive pole of polar capacitor C1 be connected with the grid of field effect transistor MOS1 after resistance R3, its minus earth.One end of resistance R2 is connected with the positive pole of polar capacitor C1, its other end ground connection.The input end that the negative pole of polar capacitor C2 is connected with the grid of field effect transistor MOS1, its positive pole then forms this signal compensation circuit.One end of resistance R4 is connected with the base stage of triode VT1, its other end is then connected with the positive pole of polar capacitor C1 after resistance R1.The N pole of diode D1 is connected with the source electrode of field effect transistor MOS1, its P pole ground connection.The positive pole of polar capacitor C3 is connected with the collector of triode VT1, its negative pole is then connected with the N pole of diode D1.
The source electrode of this field effect transistor MOS1 is connected with phase lock circuitry, and its drain electrode is then connected with the base stage of triode VT1.The emitter of described triode VT1 is connected with phase lock circuitry.The tie point of described resistance R1 and resistance R4 connects 12V voltage.This signal compensation circuit can compensate the decay of the appearance of signal in wireless transmission process, wherein field effect transistor MOS1, triode VT1, diode D1 and polar capacitor C3 form amplifying circuit, it carries out amplification process to signal, thus compensate for the decay that signal occurs in transmitting procedure.
Described phase lock circuitry is by phase-locked chip U1, triode VT2, and triode VT3, field effect transistor MOS2, resistance R5, resistance R6, resistance R7, resistance R8, resistance R9, resistance R10, diode D2, diode D3, electric capacity C4 and electric capacity C5 form.
During connection, resistance R5 is serially connected between the base stage of triode VT2 and the base stage of triode VT3.The P pole of diode D3 is connected with the drain electrode of field effect transistor MOS2, its N pole is then connected with the collector of triode VT2 after resistance R6.Resistance R8 is serially connected between the source electrode of field effect transistor MOS2 and the COMP pin of phase-locked chip U1.The P pole of diode D2 is connected with the collector of triode VT3, its N pole is then connected with the source electrode of field effect transistor MOS2 after resistance R7.The positive pole of electric capacity C4 is connected with the FB pin of phase-locked chip U1, its negative pole is then connected with the N pole of diode D2.The positive pole of electric capacity C5 is connected with the DRV pin of phase-locked chip U1, its minus earth.One end of resistance R9 is connected with the N pole of diode D3, its other end is then connected with the VSS pin of phase-locked chip U1.One end of resistance R10 is connected with the N pole of diode D3, its other end is then connected with the VDD pin of phase-locked chip U1.
Meanwhile, the collector of described triode VT2 is connected with the emitter of triode VT1, and its emitter is then connected with the emitter of triode VT3.The described base stage of triode VT3 is connected with the source electrode of field effect transistor MOS1, and its emitter is then connected with the grid of field effect transistor MOS2.The TOFF pin of described phase-locked chip U1 is all connected with filtering circuit with CS pin.This phase lock circuitry can lock the frequency of signal, thus makes signal more stable, and this phase-locked chip U1 is preferably UCT4392 type integrated chip and realizes.
Described filtered electrical routing amplifier P, triode VT4, be serially connected in the resistance R11 between the TOFF pin of phase-locked chip U1 and the positive pole of amplifier P, be serially connected in the resistance R12 between the CS pin of phase-locked chip U1 and the base stage of triode VT4, and the electric capacity C6 that positive pole is connected with the emitter of triode VT4, negative pole is then connected with the output terminal of amplifier P forms.The emitter of described triode VT4 is connected with the negative pole of amplifier P, its grounded collector; The output terminal of described amplifier P forms the output terminal of this filtering circuit.This filtering circuit can suppress the undesired signal in signal, makes the signal stored by PC more accurate.
As shown in Figure 3, this buffer circuit is by amplifier P1, and amplifier P2, amplifier P3, triode VT5, resistance R13, resistance R14, resistance R15, resistance R16, resistance R17, resistance R18, diode D4, diode D5, diode D6 and electric capacity C7 form.
During connection, the input end that one end of resistance R13 is connected with the positive pole of amplifier P1, its other end then forms this buffer circuit is also connected with the output terminal of A/D change-over circuit.The P pole of diode D4 is connected with the emitter of triode VT5, its N pole is then connected with the output terminal of amplifier P3 after resistance R16.Between the positive pole that resistance R15 is serially connected in amplifier P2 and output terminal.The positive pole of electric capacity C7 is connected with the output terminal of amplifier P2, its negative pole is then connected with the negative pole of amplifier P1 after resistance R14.The P pole of diode D5 is connected with the output terminal of amplifier P1, its N pole is then connected with the negative pole of amplifier P1.The N pole of diode D6 is connected with the negative pole of amplifier P3, its P pole is then connected with the negative pole of amplifier P1.Resistance R17 is serially connected between the output terminal of amplifier P3 and the negative pole of electric capacity C7.One end of resistance R18 is connected with the output terminal of amplifier P2, its other end then forms the output terminal of this buffer circuit and is connected with central processing unit.
The base stage of described triode VT5 is connected with the positive pole of amplifier P1, and its collector is then connected with the output terminal of amplifier P1, and its emitter is then connected with the positive pole of amplifier P3.The negative pole of described amplifier P2 is connected with the output terminal of amplifier P1.
Wherein, amplifier P3 and amplifier P2 forms a buffer stage in parallel, and it can make the input central processing unit of signal smoothing, avoids signal fluctuation and affect central processing unit processing signal, identifying, thus improves accuracy of identification of the present invention.
During work, the personnel of turnover are needed to send signal to sound transducer, this sound transducer then gathers voice signal and sends to A/D change-over circuit, this A/D change-over circuit sends to buffer circuit after voice analog signal is converted to electric signal, this electric signal is transferred to central processing unit after buffer circuit process, this central processing unit mates the signal of input with the signal stored in advance in storer, if it fails to match, central processing unit then sends command signal makes alarm module report to the police to alarm module.If the match is successful, central processing unit then sends command signal to gate inhibition's driving circuit, and this gate inhibition's driving circuit then access control is opened.The matching result of this display module then display.Simultaneously, the acoustic information of the personnel of entering, the temporal information that enters gate inhibition are also sent to the second wireless transport module by wireless network by the first wireless transport module by central processing unit, and the second wireless transport module sends PC again to and stores after signal is sent to signal processing circuit process.
As mentioned above, just well the present invention can be implemented.
Claims (7)
1. the wireless speech identification gate control system based on buffer circuit, primarily of central processing unit, second wireless transport module, the A/D change-over circuit be connected with central processing unit respectively, gate inhibition's driving circuit, alarm module, display module, storer and the first wireless transport module, the sound transducer be connected with A/D change-over circuit, the gate inhibition be connected with gate inhibition's driving circuit, the signal processing circuit be connected with the second wireless transport module, the PC be connected with signal processing circuit, and the printer be connected with PC forms; Described first wireless transport module is connected with the second wireless transport module by wireless network; It is characterized in that, between A/D change-over circuit and central processing unit, be also serially connected with buffer circuit.
2. a kind of wireless speech identification gate control system based on buffer circuit according to claim 1, it is characterized in that: described buffer circuit is by amplifier P1, amplifier P2, amplifier P3, triode VT5, one end is connected with the positive pole of amplifier P1, the other end then forms the resistance R13 of the input end of this buffer circuit, P pole is connected with the emitter of triode VT5, the diode D4 that N pole is then connected with the output terminal of amplifier P3 after resistance R16, be serially connected in the resistance R15 between the positive pole of amplifier P2 and output terminal, positive pole is connected with the output terminal of amplifier P2, the electric capacity C7 that negative pole is then connected with the negative pole of amplifier P1 after resistance R14, P pole is connected with the output terminal of amplifier P1, the diode D5 that N pole is then connected with the negative pole of amplifier P1, N pole is connected with the negative pole of amplifier P3, the diode D6 that P pole is then connected with the negative pole of amplifier P1, be serially connected in the resistance R17 between the output terminal of amplifier P3 and the negative pole of electric capacity C7, and one end is connected with the output terminal of amplifier P2, the resistance R18 that the other end then forms the output terminal of this buffer circuit forms, the base stage of described triode VT5 is connected with the positive pole of amplifier P1, and its collector is then connected with the output terminal of amplifier P1, and its emitter is then connected with the positive pole of amplifier P3, the negative pole of described amplifier P2 is connected with the output terminal of amplifier P1, the input end of described buffer circuit is connected with the output terminal of A/D change-over circuit, and its output terminal is then connected with central processing unit.
3. a kind of wireless speech identification gate control system based on buffer circuit according to claim 2, it is characterized in that: described signal processing circuit is by signal compensation circuit, the phase lock circuitry be connected with signal compensation circuit, and the filtering circuit be connected with phase lock circuitry forms; The input end of described signal compensation circuit is connected with the second wireless transport module, and the output terminal of filtering circuit is then connected with PC.
4. a kind of wireless speech identification gate control system based on buffer circuit according to claim 3, it is characterized in that: described signal compensation circuit is by triode VT1, field effect transistor MOS1, positive pole is connected with the grid of field effect transistor MOS1 after resistance R3, the polar capacitor C1 of minus earth, one end is connected with the positive pole of polar capacitor C1, the resistance R2 of other end ground connection, negative pole is connected with the grid of field effect transistor MOS1, positive pole then forms the polar capacitor C2 of the input end of this signal compensation circuit, one end is connected with the base stage of triode VT1, the resistance R4 that the other end is then connected with the positive pole of polar capacitor C1 after resistance R1, N pole is connected with the source electrode of field effect transistor MOS1, the diode D1 of P pole ground connection, and positive pole is connected with the collector of triode VT1, the polar capacitor C3 that negative pole is then connected with the N pole of diode D1 forms, the source electrode of described field effect transistor MOS1 is connected with phase lock circuitry, and its drain electrode is then connected with the base stage of triode VT1, the emitter of described triode VT1 is connected with phase lock circuitry, the tie point of described resistance R1 and resistance R4 connects 12V voltage.
5. a kind of wireless speech identification gate control system based on buffer circuit according to claim 4, it is characterized in that: described phase lock circuitry is by phase-locked chip U1, triode VT2, triode VT3, field effect transistor MOS2, be serially connected in the resistance R5 between the base stage of triode VT2 and the base stage of triode VT3, P pole is connected with the drain electrode of field effect transistor MOS2, the diode D3 that N pole is then connected with the collector of triode VT2 after resistance R6, be serially connected in the resistance R8 between the source electrode of field effect transistor MOS2 and the COMP pin of phase-locked chip U1, P pole is connected with the collector of triode VT3, the diode D2 that N pole is then connected with the source electrode of field effect transistor MOS2 after resistance R7, positive pole is connected with the FB pin of phase-locked chip U1, the electric capacity C4 that negative pole is then connected with the N pole of diode D2, positive pole is connected with the DRV pin of phase-locked chip U1, the electric capacity C5 of minus earth, one end is connected with the N pole of diode D3, the resistance R9 that the other end is then connected with the VSS pin of phase-locked chip U1, and one end is connected with the N pole of diode D3, the resistance R10 that the other end is then connected with the VDD pin of phase-locked chip U1 forms, the collector of described triode VT2 is connected with the emitter of triode VT1, and its emitter is then connected with the emitter of triode VT3, the described base stage of triode VT3 is connected with the source electrode of field effect transistor MOS1, and its emitter is then connected with the grid of field effect transistor MOS2, the TOFF pin of described phase-locked chip U1 is all connected with filtering circuit with CS pin.
6. a kind of wireless speech identification gate control system based on buffer circuit according to claim 5, it is characterized in that: described filtered electrical routing amplifier P, triode VT4, be serially connected in the resistance R11 between the TOFF pin of phase-locked chip U1 and the positive pole of amplifier P, be serially connected in the resistance R12 between the CS pin of phase-locked chip U1 and the base stage of triode VT4, and the electric capacity C6 that positive pole is connected with the emitter of triode VT4, negative pole is then connected with the output terminal of amplifier P forms; The emitter of described triode VT4 is connected with the negative pole of amplifier P, its grounded collector; The output terminal of described amplifier P forms the output terminal of this filtering circuit.
7. a kind of wireless speech identification gate control system based on buffer circuit according to claim 6, is characterized in that: described phase-locked chip U1 is UCT4392 type integrated chip.
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| CN201510963548.0A CN105427434A (en) | 2015-12-19 | 2015-12-19 | Buffer circuit-based wireless voice recognition access control system |
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| CN201510963548.0A CN105427434A (en) | 2015-12-19 | 2015-12-19 | Buffer circuit-based wireless voice recognition access control system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106355715A (en) * | 2016-08-31 | 2017-01-25 | 孟玲 | Wireless speech-recognition door access system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106355715A (en) * | 2016-08-31 | 2017-01-25 | 孟玲 | Wireless speech-recognition door access system |
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Application publication date: 20160323 |