CN105404208A - Cascadable wave control machine, wave control machine system and wave beam control method - Google Patents
Cascadable wave control machine, wave control machine system and wave beam control method Download PDFInfo
- Publication number
- CN105404208A CN105404208A CN201510929091.1A CN201510929091A CN105404208A CN 105404208 A CN105404208 A CN 105404208A CN 201510929091 A CN201510929091 A CN 201510929091A CN 105404208 A CN105404208 A CN 105404208A
- Authority
- CN
- China
- Prior art keywords
- phase
- module
- ripple
- antenna array
- output terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25341—Single chip programmable controller
Abstract
The invention provides a cascadable wave control machine, a wave control machine system and a wave beam control method. The cascadable wave control machine comprises a communication module, a phase matching calculation module, a TR assembly control module and a signal processing module, wherein the input end of the communication module is connected with the output end of a signal processor, the input/output end of the communication module is connected with the input/output end of the signal processing module, the output end of the signal processing module is connected with the input end of the phase matching calculation module, and the output end of the phase matching calculation module is connected with the input end of the TR assembly control module. When the wave control machine works, first of all, the communication module receives a control instruction sent by the signal processor, the signal processing module reads and analyzes the control instruction, sends analyzed information to the phase matching calculation module and controls the phase matching calculation module to carry out phase matching calculation, after the calculation, the phase matching calculation module sends a calculation result to the TR assembly control module, and the TR assembly control module controls a TR assembly to finish phase matching. According to the invention, the versatility and the extensibility of the wave control machine can be improved, the operation is simple, and the operation precision is high.
Description
Technical field
The present invention relates to microwave radio commu technical field, particularly relate to a kind of can the ripple control machine of cascade, ripple control machine system and beam-steering methods.
Background technology
The most outstanding feature of Phased Array Radar Antenna be antenna array motionless when realize antenna beam scanning, the technical foundation of to be phased-array radar to working environment, targeted environment have height adaptive ability that the victory of the rapid scanning of phase array antenna beam and beam shape becomes ability, their realization all depends on ripple control machine.Traditional ripple control design proposal is: when phased-array antenna array unit is fewer, generally adopt centralized architecture; When phased-array antenna array unit is many, generally adopt distributed structure/architecture; With regard to circuit realiration, early stage beam controlling system generally adopts discrete device to build realization, adopts single-chip microcomputer, DSP, FPGA to design beam controlling system afterwards, has occurred again in the recent period using customization ripple control IC to realize the design of ripple control machine scheme.
But centralized ripple control design, when front unit is larger, calculated amount is large, and operation time is long, thus have impact on the speed of beam scanning; Distributed schemes is applicable to the many situations of front unit, but can bring increasing considerably of arithmetic element equipment amount; The beam controlling system equipment needed thereby amount that discrete device is built is large, and underaction, is difficult to the complicated calculations realizing wave beam; Single-chip microcomputer does not calculate beam-control code usually, is only the beam-control code cloth phase according to receiving; Although and DSP oneself can calculate beam-control code, beam-control code calculating and cloth phase can not be carried out to each antenna channels concurrently; Customization ripple control IC dirigibility is not enough, versatility and extended capability limited.
Along with the increase of antenna array unit, ripple control machine is to the cabling more sophisticated of TR assembly, and also corresponding increase computing time of amount of phase shift and amplitude fading amount, existing ripple control machine can not meet the demands.
Summary of the invention
The object of the present invention is to provide a kind of can the ripple control machine of cascade, ripple control machine system and beam-steering methods, can improve versatility and the expandability of ripple control machine, and computing is simple, operational precision is high.
For achieving the above object, the present invention adopts following technical scheme:
A kind of can the ripple control machine of cascade, comprise FPGA module and signal processing module, described FPGA module comprises communication module, joins phase computing module and TR assembly control module, the output terminal of the input end connection signal processor of communication module, the input/output terminal of the input/output terminal connection signal processing module of communication module, the output terminal of signal processing module connects the input end of joining phase computing module, the output terminal of joining phase computing module connects the input end of TR assembly control module, TR assembly control module control linkage TR assembly; Communication module is for receiving and the steering order of buffered signal processor transmission, signal processing module is for reading and resolve the steering order of communication module buffer memory, and the information after resolving is sent to and joins phase computing module, the work of phase computing module is joined in control, join the signal of phase computing module for sending according to signal processing module, carry out the calculating of amount of phase shift and amplitude fading amount, and result of calculation is sent to TR assembly control module, TR assembly control module is used for the result of calculation according to joining phase computing module, and control TR assembly completes cloth phase;
Ripple control machine operationally, first by communication module Received signal strength processor send steering order and buffer memory, signal processing module reads the steering order of communication module buffer memory and resolves, information after parsing is sent to and joins phase computing module, join the information that phase computing module sends according to signal processing module, carry out the calculating of amount of phase shift and amplitude fading amount, after calculating, result of calculation is sent to TR assembly control module, TR assembly control module completes cloth phase according to the result of calculation control TR assembly of joining phase computing module.
Described communication module adopts ethernet module and/or UART module, the output terminal of the input end connection signal processor of ethernet module, the input/output terminal of the input/output terminal connection signal processing module of ethernet module, the output terminal of the input end connection signal processor of UART module, the input/output terminal of the input/output terminal connection signal processing module of UART module.
Described UART module comprises UART byte receiving element, FIFO buffer cell and UART byte transmitting element, the input end of UART byte receiving element comprises reset signal input end, receive clock input end, reception serial data stream input end and communication protocol and arranges word input end, and the output terminal of UART byte receiving element comprises byte interrupt identification output terminal and 8 bit parallels receive data output end;
The input end of FIFO buffer cell comprises reset signal input end, receive clock input end, byte interrupt identification input end, 8 bit parallels reception data input pin and DSP read signal input ends, and output terminal comprises the full look-at-me output terminal of FIFO and cache control instruction output terminal;
The input end of UART byte transmitting element comprises reset signal input end, tranmitting data register input end, 8 bit parallels send data input pins, communication protocol arranges word input end, outputs signal as sending serial data stream;
The byte interrupt identification output terminal of UART byte receiving element connects the byte interrupt identification input end of FIFO buffer cell, 8 bit parallels of UART byte receiving element receive 8 bit parallels reception data input pins of data output end connection FIFO buffer cell, the cache control instruction output terminal of FIFO buffer cell connects 8 bit parallels transmission data input pins of UART byte transmitting element, the input end of the output terminal connection signal processing module of UART byte transmitting element, 8 bit parallels of UART byte transmitting element send the output terminal of data input pins also connection signal processing module.
There are 4 ROM look-up tables described phase computing module inside of joining, be respectively frequency signal look-up table, ripple position signal look-up table, receive first phase look-up table and launch first phase look-up table, the content stored in frequency signal look-up table is the frequency number information of aerial array, and frequency signal look-up table take Frequency point as lookup table index; The information stored in the signal look-up table of ripple position is the ripple item information of aerial array, ripple position signal look-up table with ripple item for lookup table index; Receive the initial phase value that the information stored in first phase look-up table is each receiving cable, receive first phase look-up table with the frequency number of current antenna array element for line index, be numbered column index with current antenna array element; Launch the original phase information that the information stored in first phase look-up table is each transmission channel, launch phase look-up table with the frequency number of current antenna array element for line index, be numbered column index with current antenna array element.
Described signal processing module adopts the input/output terminal of DSP, DSP to connect the input/output terminal of communication module by EMIF bus.
Also comprise power module, described power module comprises a slice LTM8023 chip, a slice TPS70445 chip, two panels LTM8023 chip, two panels LTM8023 chip, a slice LTM8023 chip and 6 LTM4613 chips, described a slice LTM8023 chip is connected with signal processing module respectively with a slice TPS70445 chip, two panels LTM8023 chip respectively with join phase computing module and be connected, two panels LTM8023 chip is connected with ethernet module respectively, and a slice LTM8023 chip is connected with TR assembly respectively with 6 LTM4613 chips.
Also energy supply control module is provided with, energy supply control module control linkage power module in described FPGA module.
Ripple control machine system, comprise n platform ripple control machine, wherein, the output terminal of the communication module of First ripple control machine connects the input end of the communication module of second ripple control machine, and the output terminal of the communication module of second ripple control machine connects the input end of the communication module of the 3rd ripple control machine, by that analogy, the output terminal of the communication module of (n-1)th ripple control machine connects the input end of n-th ripple control machine, n=2,3 ...
Utilize and above-mentionedly the ripple control machine of cascade can carry out the method for wave beam control, comprise the following steps successively:
(1) communication module Received signal strength processor send steering order and buffer memory, produce DSP interrupt after buffer memory;
(2) signal processing module response interrupt service routine, reads the steering order of buffer memory in communication module by EMIF bus and resolves; If steering order is online-order, signal processing module adopts EMIF bus mode that the failure message of the online answer signal of ripple control machine and TR assembly is write communication module, by the online answer signal of communication module to signal processor passback ripple control machine and the failure message of TR assembly; If steering order is for joining phase parameter instruction, signal processing module extracts frequency number, ripple item information in steering order, and joins phase computing module with the write of EMIF bus mode, starts and joins phase computation process;
(3) join the calculating that phase computing module carries out amount of phase shift and amplitude fading amount, and result of calculation is sent to TR assembly control module.
In described step (3), the computation process of joining the inner amount of phase shift of phase computing module and amplitude fading amount is as follows:
A, the frequency number information of aerial array and ripple item information are carried out quantizing and amplifying pre-service successively, respectively stored in frequency signal look-up table and ripple position signal look-up table; Measure the initial phase of each receiving cable and the initial phase of each transmission channel successively, the original phase information of the initial phase of each receiving cable recorded and transmission channel is carried out quantizing and amplifying pre-service successively, respectively stored in reception first phase look-up table and transmitting first phase table;
B, the frequency number extracted according to signal processing module and ripple item information, search frequency signal look-up table and ripple position signal look-up table respectively, obtain frequency information pre-computation value and the ripple position information pre-computation value of current antenna array element;
C, the frequency information pre-computation value obtained in step b is multiplied with ripple position information pre-computation value after, then be multiplied with the numbering i of current antenna array element, the ideal obtaining current antenna array element i joins phase phase place;
D, with ongoing frequency number for line index, with current antenna array element numbering i for column index, search and receive first phase look-up table, obtain the reception initial phase of current antenna array element;
E, the ideal of the current antenna array element i obtained by step c joins phase phase place, the reception initial phase of the current antenna unit that a upper antenna array unit computing residual error E1 and steps d obtain carries out additional calculation successively, round up calculating and delivery calculating, obtaining current number is that phase code initial value is joined in the reception of the antenna array unit of i, be that the reception of the antenna array unit of i is joined phase code initial value and to be moved to right Q position by current number, obtaining current number is that phase code is joined in the reception of the antenna array unit of i, Q represents system data enlargement factor parameter, the value of Q is frequency signal data enlargement factor parameter a and ripple position signal data enlargement factor parameter b sum,
F, the reception of current antenna array element obtained by step e are joined phase code and to be moved to left Q position, and join phase code initial value with the reception of current antenna array element that obtains in step e and subtract each other, and obtain the computing residual error E1 of current antenna unit;
G, with ongoing frequency number for line index, with current antenna array element numbering i column index, search and launch first phase look-up table, obtain the transmitting initial phase of current antenna array element;
The transmitting initial phase that h, the ideal of current antenna array element i obtained by step c join the current antenna array element that phase phase place, a upper antenna array unit computing residual error E2 and step g obtain carries out additional calculation successively, round up calculating and delivery calculate, obtaining current number is that phase code initial value is joined in the transmitting of the antenna array unit of i, be that the transmitting of the antenna array unit of i is joined phase code initial value and to be moved to right Q position by current number, obtaining current number is that phase code is joined in the transmitting of the antenna array unit of i;
I, the transmitting of current antenna array element obtained by step h are joined phase code and to be moved to left Q position, and the transmitting of the current antenna array element obtained with step h is joined phase code initial value and subtracted each other, and obtains the computing residual error E2 of active cell;
J, the reception obtained by step e are joined transmitting that phase code and step h obtain and are joined phase code and send to TR assembly control module.
The present invention adopts ethernet module and UART module communication, ethernet module communication is adopted when ripple control machine high-speed communication, UART module communication is adopted when ripple control machine low-speed communication, select corresponding communication module according to different traffic rates during use, can meet not homophase battle array control system to the requirement of traffic rate; Signal processing module can complete the high speed processing of steering order and parsing that send signal processor, calculates amount of phase shift and the amplitude fading amount of each array element in real time, and controls to join the calculating that phase computing module carries out amount of phase shift and amplitude fading amount; Join the real-time calculating that phase computing module can realize amount of phase shift to all Frequency points of each array element, ripple site and amplitude fading amount, eliminate external high-capacity FLASH, circuit structure is simplified greatly, control flexibly; Joining phase computing module adopts iteration to join phase computing method, and calculating expends time in short, and computational accuracy is high; Modules of the present invention adopts different electrical power to power simultaneously, and FPGA inside is provided with energy supply control module, accurately can control powering on and power down order of modules power supply; TR assembly adopt multiple feed, energy supply control module can accurately each power supply of control TR assembly power on and power down order, meet TR assembly to each power supply electrifying, power down order requirement.
In addition, the present invention can realize the cascade of multiple stage ripple control machine, and whole system cabling is simple, and transmission speed is fast, can shorten the operation time of joining phase computing module, and have extensibility, can realize the control of larger phased array beam.
Accompanying drawing explanation
Fig. 1 is circuit theory diagrams of the present invention;
Fig. 2 is the circuit theory diagrams of UART byte receiving element of the present invention;
Fig. 3 is the circuit theory diagrams of FIFO buffer cell of the present invention;
Fig. 4 is the circuit theory diagrams of UART byte transmitting element of the present invention;
Fig. 5 is the theory diagram of FPGA module of the present invention;
Fig. 6 is the circuit theory diagrams of DSP module of the present invention;
Fig. 7 is the circuit theory diagrams of power module of the present invention;
Fig. 8 is the theory diagram of ripple control machine system of the present invention;
Fig. 9 is process flow diagram of joining the computing method of phase computing module of the present invention.
Embodiment
As shown in Figures 1 to 7, the present invention includes FPGA module and signal processing module, FPGA module comprises communication module, join phase computing module and TR assembly control module, communication module adopts ethernet module and/or UART module, UART module adopts MAX3078 chip, ethernet module adopts W5300 chip, ethernet module communication is adopted when ripple control machine high-speed communication, UART module communication is adopted when ripple control machine low-speed communication, communication module is selected according to different traffic rates during use, can meet not homophase battle array control system to the requirement of traffic rate, the output terminal of the input end connection signal processor of communication module, the input/output terminal of communication module passes through the input/output terminal of EMIF bus connection signal processing module, the output terminal of signal processing module connects the input end of joining phase computing module, join phase computing module and adopt EP2S60F484I4 chip, the output terminal of joining phase computing module connects the input end of TR assembly control module, TR assembly control module control linkage TR assembly, communication module is for receiving the steering order sent with buffer memory signal processor, signal processing module adopts the DSP of TMS320C6713B model, signal processing module is for reading and resolve the steering order of communication module buffer memory, and the information after resolving is sent to and joins phase computing module, the work of phase computing module is joined in control, join the signal of phase computing module for sending according to signal processing module, carry out the calculating of amount of phase shift and amplitude fading amount, and result of calculation is sent to TR assembly control module, realize the real-time calculating to each antenna array unit of TR assembly amount of phase shift and amplitude fading amount under present frequency point and ripple site, TR assembly control module is used for the amount of phase shift of each antenna array unit and amplitude fading amount being carried out combining according to TR component communication protocol format and being distributed to TR assembly, control TR assembly completes cloth phase, TR assembly and signal processor are the existing apparatus in wireless transmitting system.
UART module adopts MAX3078 chip, comprise UART byte receiving element, FIFO buffer cell and UART byte transmitting element, the input end of UART byte receiving element comprises reset signal input end, receive clock input end, reception serial data stream input end and communication protocol arrange word input end, reset signal is used for initialization UART byte receiving element, UART internal clock frequencies is 1.152MHz, it is 10 times of communication baud rate, for realizing 115200 baud rate asynchronous communications, the input signal receiving serial data stream input end is the asynchronous serial data that signal processor sends, communication protocol arranges word input end for arranging asynchronous communications protocol, in the present embodiment, asynchronous communications protocol arranges 8 for data bit, 1 start bit, 1 position of rest, no parity position, the output terminal of UART byte receiving element comprises byte interrupt identification output terminal and 8 bit parallels receive data output end.To be changed after 8 bit parallels count up to into by serial data when UART byte receiving element completes, the output signal of byte interrupt identification output terminal transfers high level to; After UART byte receiving element enters data transition status, the output signal of byte interrupt identification output terminal transfers low level to.
The input end of FIFO buffer cell comprises reset signal input end, receive clock input end, byte interrupt identification input end, 8 bit parallels reception data input pin and DSP read signal input ends, output terminal comprises the full look-at-me output terminal of FIFO and cache control instruction output terminal, the byte interrupt identification output terminal of UART byte receiving element connects the byte interrupt identification input end of FIFO buffer cell, and 8 bit parallels of UART byte receiving element receive 8 bit parallels reception data input pins of data output end connection FIFO buffer cell.When the input signal that FIFO buffer cell detects byte interrupt identification input end is high level, FIFO buffer cell carries out write operation, when FIFO buffer cell receives frame data of communication protocol definition, produces the full look-at-me of FIFO; When asynchronous communication process exception, FIFO buffer cell is not complete when receiving a frame control data, and FIFO buffer cell produces the full look-at-me of FIFO by time-out meter, avoids because of one time that garble causes Continued communication error in data.The full look-at-me of FIFO is directly as the look-at-me of DSP, and trigger the operation disruption program that DSP reads FIFO buffer cell, DSP read signal is negative pulse, and often produce a DSP read signal, FIFO buffer cell carries out a secondary data and pushes.
UART byte transmitting element be used for 8 bit parallel data to be converted to baud rate 115200,8 bit data position, 1 start bit, 1 position of rest, no parity position asynchronous serial data stream export.The input end of UART byte transmitting element comprises reset signal input end, tranmitting data register input end, 8 bit parallels send data input pins, communication protocol arranges word input end, outputs signal as sending serial data stream.The cache control instruction output terminal of FIFO buffer cell connects 8 bit parallels transmission data input pins of UART byte transmitting element, the output terminal of UART byte transmitting element connects the input end of DSP, and 8 bit parallels transmission data input pins of UART byte transmitting element also connect the output terminal of DSP.
Join phase computing module inside and be provided with 4 ROM look-up tables, be respectively frequency signal look-up table, ripple position signal look-up table, receive first phase look-up table and launch first phase look-up table, the content that frequency signal look-up table stores is the frequency number information of aerial array, and expression formula is round (-k/In × 2
a× f), wherein round represents the function that rounds up, and k represents aerial array distributed constant, the value of k is relevant to aerial array distribution parameter, and the data mode of k is floating type constant, and In represents phase shifter minimum step amount, in 6 bit digital formula phase shifters, In gets 360/2
6, namely 5.625; A represents frequency signal data enlargement factor parameter, and f represents frequency, and unit is GHz.If operating frequency of antenna is counted as n, then frequency signal look-up table storage dimensions is n, and frequency signal look-up table is an one-dimension array table, take Frequency point as lookup table index;
The content that ripple position signal look-up table stores is the ripple item information of aerial array, and expression formula is round (Sin (θ) × 2
b), wherein round represents the function that rounds up, and Sin () represents sine function, and θ represents the sensing angle of antenna ripple position correspondence, and b represents ripple position signal data enlargement factor parameter.If Antenna Operation ripple figure place is m, then frequency signal look-up table storage dimensions is m; Ripple position signal look-up table is an one-dimension array table, with ripple item for lookup table index;
The content receiving the storage of first phase look-up table is the initial phase value of each receiving cable, and expression formula is round (initial phase/In × 2
q).Wherein round represents the function that rounds up, and In represents phase shifter minimum step amount, and in 6 bit digital formula phase shifters, In gets 360/2
6, namely 5.625, Q represent system data enlargement factor parameter, and the value of Q is frequency signal data enlargement factor parameter a and ripple position signal data enlargement factor parameter b sum.Each antenna element receiving cable has different initial phase at different frequencies, if antenna receiving cable number is Num_r, frequency of operation is counted as n, then receiving first phase look-up table storage dimensions is Num_r × n, wherein, Num represents number, and r represents reception, n=1,2 ...Receiving first phase look-up table is a two-dimensional array table, with Antenna Operation frequency for line index parameter, with antenna channels unit number for column index parameter.Under searching certain Frequency point, certain antenna element receives just phase time, and index value is that present frequency point is multiplied by Num_r+i, and wherein i represents current antenna unit channel number;
The content of launching the storage of first phase look-up table is the initial phase value of each transmission channel, and expression formula is round (initial phase/In × 2
q), wherein round represents the function that rounds up, and In represents phase shifter minimum step amount, and in 5 bit digital formula phase shifters, In gets 360/2
5, namely 11.25; Q represents system data enlargement factor parameter, and the value of Q is frequency signal data enlargement factor parameter a and ripple position signal data enlargement factor parameter b sum.Each antenna element transmission channel has different initial phase at different frequencies, if antenna transmission port number is Num_t, frequency of operation is counted as n, then launching first phase look-up table storage dimensions is Num_t × n, wherein, Num represents number, and t represents transmitting, n=1,2 ...Launching first phase look-up table is a two-dimensional array table, with Antenna Operation frequency for line index parameter, with antenna channels unit number for column index parameter.Under searching certain Frequency point, certain antenna element launches first phase, and its index value is present frequency point × Num_t+i, and wherein i represents current antenna unit channel number.
The present invention also comprises power module, power module comprises 1 LTM8023 chip, a slice TPS70445 chip, two panels LTM8023 chip, two panels LTM8023 chip, a slice LTM8023 chip and 6 LTM4613 chips, a slice LTM8023 chip is connected with signal processing module respectively with TPS70445 chip, two panels LTM8023 chip respectively with join phase computing module and be connected, two panels LTM8023 chip is connected with ethernet module respectively, and a slice LTM8023 chip is connected with TR assembly respectively with 6 LTM4613 chips.Also be provided with energy supply control module in FPGA, energy supply control module is connected with power module, for controlling powering on and power down of modules power supply.
As shown in Figure 8, when antenna array unit increases, adopt ripple control machine system to realize wave beam to control, ripple control machine system comprises some ripple control machines, adopt three ripple control machines in the present embodiment, the output terminal of the communication module of First ripple control machine connects the input end of the communication module of second ripple control machine, and the output terminal of the communication module of second ripple control machine connects the input end of the communication module of the 3rd ripple control machine.Signal processor by communication module to First ripple control machine sending controling instruction, after First ripple control machine receives steering order, second ripple control machine is sent to immediately by communication module, by that analogy, all ripple control machines are after receiving steering order, start to carry out amount of phase shift and amplitude fading amount and calculating, and result of calculation is sent to corresponding TR assembly, finally input TR assembly by unified latch pulse, make all TR assemblies cloth phase simultaneously, the generation of latch pulse and latch pulse input TR assembly, to complete the process of cloth phase for prior art, repeat no more.When antenna array unit increases, adopt the ripple control machine system of multiple stage ripple control machine series connection to carry out wave beam control, whole system cabling is simple, transmission speed is fast, the operation time of joining phase computing module can be shortened, and there is extensibility, the control of larger phased array beam can be realized.
Utilize ripple control machine of the present invention to carry out the method for wave beam control, comprise the following steps successively:
(1) communication module Received signal strength processor send steering order and buffer memory, produce DSP interrupt after buffer memory;
(2) signal processing module response interrupt service routine, reads the steering order of buffer memory in communication module by EMIF bus and resolves; If steering order is online-order, signal processing module adopts EMIF bus mode that the failure message of the online answer signal of ripple control machine and TR assembly is write communication module, by the online answer signal of communication module to signal processor passback ripple control machine and the failure message of TR assembly; If steering order is for joining phase parameter instruction, signal processing module extracts frequency number, ripple item information in steering order, and joins phase computing module with the write of EMIF bus mode, starts and joins phase computation process;
(3) join the calculating that phase computing module carries out amount of phase shift and amplitude fading amount, and result of calculation is sent to TR assembly control module.
The computation process of amount of phase shift and amplitude fading amount is prior art, but existing computing method are long for computing time, computational accuracy is not high, and for the defect of prior art, the present invention proposes the method utilizing process of iteration to carry out amount of phase shift and the calculation of amplitude fading gauge especially.
Amount of phase shift and amplitude fading gauge are calculated abbreviation and are joined and calculate mutually, calculate replacement mutually below with joining.
Join phase computing module and join phase algorithm by algorithm optimal implementation iteration, the mathematic(al) representation that iteration joins phase algorithm is:
c(i)＝mod{int(p
1/In),360/In}，i∈(1,2,…,N)
Wherein:
p＝mod{|-k×i×k××sin(θ)-p
0(i)+e
i-1|,360}
Int is round operational symbol; Mod is delivery complementation operational symbol; θ is orientation angle; F is frequency, and unit is GHz; p
0i () is the first phase of i unit phase shifter, p is the i-th unit amount of phase shift result of calculation intermediate value, and subscript 0 is only differentiation effect, and non-variables, i=1,2, K is bay distributed constant; e
i - 1for the quantization error that a upper phase-shifting unit produces, subscript i=1,2, p
1for normalizing to the phase shift value of the i-th unit phase shifter of 0-360 degree; C (i) be the i-th unit phase shifter join phase code; In is phase shifter minimum step amount, i.e. the quantification benchmark of phase-shift system, if phase-shift system adopts 4 bit phase shifter, then and In=360/2
4=22.5; According to 6 bit phase shifter, then In=360/2
6=5.625.Which kind of quantification benchmark phase-shift system adopts determined according to system index requirement by antenna system.
It is a kind of based on trigonometric function operation, multiplication, division, addition, delivery and the floating-point iterative algorithm that rounds up that iteration joins phase algorithm, for elevator system performance, floating-point operation mode is converted to the integer arithmetic mode comparatively easily realized, simplify the computings such as trigonometric function, multiplication, division, delivery simultaneously as far as possible, reduce calculating process complexity.Iteration joins the key step calculated mutually to be had:
1. by iteration, the real-coded GA of joining in phase algorithm is converted to integer data.
A, the real-coded GA related in algorithm carried out except In computing;
B, will except after In computing gained real-coded GA amplify 2
qdoubly, Q represents system data enlargement factor parameter, and the value of Q is frequency signal data enlargement factor parameter a and ripple position signal data enlargement factor parameter b sum;
C, will 2 be amplified
qreal-coded GA doubly carries out the process that rounds up, and is converted to integer data;
2. use look-up table simplified operation process, will confirmable multiplication and division operation values and sin operation values carry out except In quantification and 2 in advance
qstored in joining in phase computing module after doubly amplifying, dispensing complicated trigonometric function operation and reducing multiplication and division operation link, reducing system complexity, improving algorithm speed;
3., based on data quantification and data encoding principle, simplification iteration joins the complex calculation in phase algorithm further.Because carried out before real-coded GA is converted into integer data except In quantizes, and symbol integer number is had to store with complement form joining in phase computing module, can accordingly by simple logical and realization condition formula
Computing.Joining the binary code and (2 of the P value after only amplification need being quantized in phase computing module
360/In× 2
q-1) binary code carries out logical and operation, i.e. the computing of realizability condition formula P1.Like this then the branch dispensed in computing judges and plus and minus calculation, and mod computing is converted to logical and operation, significantly reduces system operations complexity.
As shown in Figure 9, phase computation process is joined in the present invention as follows:
A, the frequency number information of aerial array and ripple item information are carried out quantizing and amplifying pre-service successively, respectively stored in frequency signal look-up table and ripple position signal look-up table; Measure the initial phase of each receiving cable and the initial phase of each transmission channel successively, the original phase information of the initial phase of each receiving cable recorded and transmission channel is carried out quantizing and amplifying pre-service successively, respectively stored in reception first phase look-up table and transmitting first phase table;
B, the frequency number extracted according to signal processing module and ripple item information, search frequency signal look-up table and ripple position signal look-up table respectively, obtain frequency information pre-computation value and the ripple position information pre-computation value of current antenna array element;
C, the frequency information pre-computation value obtained in step b is multiplied with ripple position information pre-computation value after, then be multiplied with the numbering i of current antenna array element, the ideal obtaining current antenna array element i joins phase phase place;
D, with ongoing frequency number for line index, with current antenna array element numbering i for column index, search and receive first phase look-up table, obtain the reception initial phase of current antenna array element;
E, the ideal of the current antenna array element i obtained by step c joins phase phase place, the reception initial phase of the current antenna unit that a upper antenna array unit computing residual error E1 and steps d obtain carries out additional calculation successively, round up calculating and delivery calculating, obtaining current number is that phase code initial value is joined in the reception of the antenna array unit of i, be that the reception of the antenna array unit of i is joined phase code initial value and to be moved to right Q position by current number, obtaining current number is that phase code is joined in the reception of the antenna array unit of i, Q represents system data enlargement factor parameter, the value of Q is frequency signal data enlargement factor parameter a and ripple position signal data enlargement factor parameter b sum,
F, the reception of current antenna array element obtained by step e are joined phase code and to be moved to left Q position, and join phase code initial value with the reception of current antenna array element that obtains in step e and subtract each other, and obtain the computing residual error E1 of current antenna unit;
G, with ongoing frequency number for line index, with current antenna array element numbering i column index, search and launch first phase look-up table, obtain the transmitting initial phase of current antenna array element;
The transmitting initial phase that h, the ideal of current antenna array element i obtained by step c join the current antenna array element that phase phase place, a upper antenna array unit computing residual error E2 and step g obtain carries out additional calculation successively, round up calculating and delivery calculate, obtaining current number is that phase code initial value is joined in the transmitting of the antenna array unit of i, be that the transmitting of the antenna array unit of i is joined phase code initial value and to be moved to right Q position by current number, obtaining current number is that phase code is joined in the transmitting of the antenna array unit of i;
I, the transmitting of current antenna array element obtained by step h are joined phase code and to be moved to left Q position, and the transmitting of the current antenna array element obtained with step h is joined phase code initial value and subtracted each other, and obtains the computing residual error E2 of active cell;
J, the reception obtained by step e are joined transmitting that phase code and step h obtain and are joined phase code and send to TR assembly control module.
The phase yardage of joining carrying out N number of phase-shifting unit is calculated, and required time is N/f
n, wherein, f
nfor the counting clock frequency of counter, N=1,2 ...For 20MHZ elapsed time clock frequency, complete the reception of a phase-shifting unit, send the phase of joining of joining phase code and be only 50ns computing time, computing time is short; When expansion multiple 2
qlarger, approximation error noise is less, less to the Accuracy of algorithm, when expansion multiple is 2
48time, the method for the invention and MATLAB floating-point operation result completely the same, illustrate beam-steering methods of the present invention not only computing time short, and there is very high computational accuracy.
Claims (10)
1. one kind can the ripple control machine of cascade, it is characterized in that: comprise FPGA module and signal processing module, described FPGA module comprises communication module, joins phase computing module and TR assembly control module, the output terminal of the input end connection signal processor of communication module, the input/output terminal of the input/output terminal connection signal processing module of communication module, the output terminal of signal processing module connects the input end of joining phase computing module, the output terminal of joining phase computing module connects the input end of TR assembly control module, TR assembly control module control linkage TR assembly; Communication module is for receiving and the steering order of buffered signal processor transmission, signal processing module is for reading and resolve the steering order of communication module buffer memory, and the information after resolving is sent to and joins phase computing module, the work of phase computing module is joined in control, join the signal of phase computing module for sending according to signal processing module, carry out the calculating of amount of phase shift and amplitude fading amount, and result of calculation is sent to TR assembly control module, TR assembly control module is used for the result of calculation according to joining phase computing module, and control TR assembly completes cloth phase;
Ripple control machine operationally, first by communication module Received signal strength processor send steering order and buffer memory, signal processing module reads the steering order of communication module buffer memory and resolves, information after parsing is sent to and joins phase computing module, join the information that phase computing module sends according to signal processing module, carry out the calculating of amount of phase shift and amplitude fading amount, after calculating, result of calculation is sent to TR assembly control module, TR assembly control module completes cloth phase according to the result of calculation control TR assembly of joining phase computing module.
2. a kind of as claimed in claim 1 can the ripple control machine of cascade, it is characterized in that: described communication module adopts ethernet module and/or UART module, the output terminal of the input end connection signal processor of ethernet module, the input/output terminal of the input/output terminal connection signal processing module of ethernet module, the output terminal of the input end connection signal processor of UART module, the input/output terminal of the input/output terminal connection signal processing module of UART module.
3. a kind of as claimed in claim 2 can the ripple control machine of cascade, it is characterized in that: described UART module comprises UART byte receiving element, FIFO buffer cell and UART byte transmitting element, the input end of UART byte receiving element comprises reset signal input end, receive clock input end, reception serial data stream input end and communication protocol and arranges word input end, and the output terminal of UART byte receiving element comprises byte interrupt identification output terminal and 8 bit parallels receive data output end;
The input end of FIFO buffer cell comprises reset signal input end, receive clock input end, byte interrupt identification input end, 8 bit parallels reception data input pin and DSP read signal input ends, output terminal comprises the full look-at-me output terminal of FIFO and cache control instruction output terminal;
The input end of UART byte transmitting element comprises reset signal input end, tranmitting data register input end, 8 bit parallels send data input pins, communication protocol arranges word input end, outputs signal as sending serial data stream;
The byte interrupt identification output terminal of UART byte receiving element connects the byte interrupt identification input end of FIFO buffer cell, 8 bit parallels of UART byte receiving element receive 8 bit parallels reception data input pins of data output end connection FIFO buffer cell, the cache control instruction output terminal of FIFO buffer cell connects 8 bit parallels transmission data input pins of UART byte transmitting element, the input end of the output terminal connection signal processing module of UART byte transmitting element, 8 bit parallels of UART byte transmitting element send the output terminal of data input pins also connection signal processing module.
4. a kind of as claimed in claim 1 can the ripple control machine of cascade, it is characterized in that: described in join phase computing module inside and have 4 ROM look-up tables, be respectively frequency signal look-up table, ripple position signal look-up table, receive first phase look-up table and launch first phase look-up table, the content stored in frequency signal look-up table is the frequency number information of aerial array, and frequency signal look-up table take Frequency point as lookup table index; The information stored in the signal look-up table of ripple position is the ripple item information of aerial array, ripple position signal look-up table with ripple item for lookup table index; Receive the initial phase value that the information stored in first phase look-up table is each receiving cable, receive first phase look-up table with the frequency number of current antenna array element for line index, be numbered column index with current antenna array element; Launch the original phase information that the information stored in first phase look-up table is each transmission channel, launch phase look-up table with the frequency number of current antenna array element for line index, be numbered column index with current antenna array element.
5. a kind of as described in claim 1 or 4 can the ripple control machine of cascade, it is characterized in that: described signal processing module adopts the input/output terminal of DSP, DSP to connect the input/output terminal of communication module by EMIF bus.
6. a kind of as claimed in claim 5 can the ripple control machine of cascade, it is characterized in that: also comprise power module, described power module comprises a slice LTM8023 chip, a slice TPS70445 chip, two panels LTM8023 chip, two panels LTM8023 chip, a slice LTM8023 chip and 6 LTM4613 chips, described a slice LTM8023 chip is connected with signal processing module respectively with a slice TPS70445 chip, two panels LTM8023 chip respectively with join phase computing module and be connected, two panels LTM8023 chip is connected with ethernet module respectively, a slice LTM8023 chip is connected with TR assembly respectively with 6 LTM4613 chips.
7. a kind of as claimed in claim 1 can the ripple control machine of cascade, it is characterized in that: in described FPGA module, be also provided with energy supply control module, energy supply control module control linkage power module.
8. one kind utilize described in claim 1 to any one of claim 7 can cascade ripple control machine composition ripple control machine system, it is characterized in that: comprise n platform ripple control machine, wherein, the output terminal of the communication module of First ripple control machine connects the input end of the communication module of second ripple control machine, the output terminal of the communication module of second ripple control machine connects the input end of the communication module of the 3rd ripple control machine, by that analogy, the output terminal of the communication module of (n-1)th ripple control machine connects the input end of n-th ripple control machine, n=2,3 ...
9. utilize and the ripple control machine of cascade can carry out the method for wave beam control described in claim 1 or 7, it is characterized in that, comprise the following steps successively:
(1) communication module Received signal strength processor send steering order and buffer memory, produce DSP interrupt after buffer memory;
(2) signal processing module response interrupt service routine, reads the steering order of buffer memory in communication module by EMIF bus and resolves; If steering order is online-order, signal processing module adopts EMIF bus mode that the failure message of the online answer signal of ripple control machine and TR assembly is write communication module, by the online answer signal of communication module to signal processor passback ripple control machine and the failure message of TR assembly; If steering order is for joining phase parameter instruction, signal processing module extracts frequency number, ripple item information in steering order, and joins phase computing module with the write of EMIF bus mode, starts and joins phase computation process;
(3) join the calculating that phase computing module carries out amount of phase shift and amplitude fading amount, and result of calculation is sent to TR assembly control module.
10. beam-steering methods as claimed in claim 9, is characterized in that, in described step (3), the computation process of joining the inner amount of phase shift of phase computing module and amplitude fading amount is as follows:
A, the frequency number information of aerial array and ripple item information are carried out quantizing and amplifying pre-service successively, respectively stored in frequency signal look-up table and ripple position signal look-up table; Measure the initial phase of each receiving cable and the initial phase of each transmission channel successively, the original phase information of the initial phase of each receiving cable recorded and transmission channel is carried out quantizing and amplifying pre-service successively, respectively stored in reception first phase look-up table and transmitting first phase table;
B, the frequency number extracted according to signal processing module and ripple item information, search frequency signal look-up table and ripple position signal look-up table respectively, obtain frequency information pre-computation value and the ripple position information pre-computation value of current antenna array element;
C, the frequency information pre-computation value obtained in step b is multiplied with ripple position information pre-computation value after, then be multiplied with the numbering i of current antenna array element, the ideal obtaining current antenna array element i joins phase phase place;
D, with ongoing frequency number for line index, with current antenna array element numbering i for column index, search and receive first phase look-up table, obtain the reception initial phase of current antenna array element;
E, the ideal of the current antenna array element i obtained by step c joins phase phase place, the reception initial phase of the current antenna unit that a upper antenna array unit computing residual error E1 and steps d obtain carries out additional calculation successively, round up calculating and delivery calculating, obtaining current number is that phase code initial value is joined in the reception of the antenna array unit of i, be that the reception of the antenna array unit of i is joined phase code initial value and to be moved to right Q position by current number, obtaining current number is that phase code is joined in the reception of the antenna array unit of i, Q represents system data enlargement factor parameter, the value of Q is frequency signal data enlargement factor parameter a and ripple position signal data enlargement factor parameter b sum,
F, the reception of current antenna array element obtained by step e are joined phase code and to be moved to left Q position, and join phase code initial value with the reception of current antenna array element that obtains in step e and subtract each other, and obtain the computing residual error E1 of current antenna unit;
G, with ongoing frequency number for line index, with current antenna array element numbering i column index, search and launch first phase look-up table, obtain the transmitting initial phase of current antenna array element;
The transmitting initial phase that h, the ideal of current antenna array element i obtained by step c join the current antenna array element that phase phase place, a upper antenna array unit computing residual error E2 and step g obtain carries out additional calculation successively, round up calculating and delivery calculate, obtaining current number is that phase code initial value is joined in the transmitting of the antenna array unit of i, be that the transmitting of the antenna array unit of i is joined phase code initial value and to be moved to right Q position by current number, obtaining current number is that phase code is joined in the transmitting of the antenna array unit of i;
I, the transmitting of current antenna array element obtained by step h are joined phase code and to be moved to left Q position, and the transmitting of the current antenna array element obtained with step h is joined phase code initial value and subtracted each other, and obtains the computing residual error E2 of active cell;
J, the reception obtained by step e are joined transmitting that phase code and step h obtain and are joined phase code and send to TR assembly control module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510929091.1A CN105404208B (en) | 2015-12-12 | 2015-12-12 | One kind can cascade wave control machine, wave control machine system and beam-steering methods |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510929091.1A CN105404208B (en) | 2015-12-12 | 2015-12-12 | One kind can cascade wave control machine, wave control machine system and beam-steering methods |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105404208A true CN105404208A (en) | 2016-03-16 |
| CN105404208B CN105404208B (en) | 2018-06-29 |
Family
ID=55469756
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510929091.1A Expired - Fee Related CN105404208B (en) | 2015-12-12 | 2015-12-12 | One kind can cascade wave control machine, wave control machine system and beam-steering methods |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105404208B (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107238816A (en) * | 2017-06-02 | 2017-10-10 | 江苏万邦微电子有限公司 | A kind of multi-functional submatrix beam-forming network of phased-array radar |
| CN105404208B (en) * | 2015-12-12 | 2018-06-29 | 中国电子科技集团公司第二十七研究所 | One kind can cascade wave control machine, wave control machine system and beam-steering methods |
| CN109932964A (en) * | 2019-04-13 | 2019-06-25 | 上海亿算科技有限公司 | A kind of calculation power chip and calculation power chip system of connecting |
| CN110068809A (en) * | 2019-05-06 | 2019-07-30 | 成都泰格微电子研究所有限责任公司 | A kind of wave control processing module for phased-array radar |
| CN110661100A (en) * | 2019-10-08 | 2020-01-07 | 上海无线电设备研究所 | Phased array antenna beam control device and method |
| CN110703247A (en) * | 2019-10-30 | 2020-01-17 | 中国科学院电子学研究所 | Wave position information detection method, wave position information detection device and storage medium |
| CN112596030A (en) * | 2020-12-04 | 2021-04-02 | 南京理工大学 | Wave control method and system based on X-band unmanned aerial vehicle airborne SAR |
| CN115267685A (en) * | 2022-09-23 | 2022-11-01 | 江苏万邦微电子有限公司 | Built-in microwave signal state data readback TR component wave control module |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105404208B (en) * | 2015-12-12 | 2018-06-29 | 中国电子科技集团公司第二十七研究所 | One kind can cascade wave control machine, wave control machine system and beam-steering methods |
-
2015
- 2015-12-12 CN CN201510929091.1A patent/CN105404208B/en not_active Expired - Fee Related
Non-Patent Citations (1)
| Title |
|---|
| No relevant documents disclosed * |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105404208B (en) * | 2015-12-12 | 2018-06-29 | 中国电子科技集团公司第二十七研究所 | One kind can cascade wave control machine, wave control machine system and beam-steering methods |
| CN107238816A (en) * | 2017-06-02 | 2017-10-10 | 江苏万邦微电子有限公司 | A kind of multi-functional submatrix beam-forming network of phased-array radar |
| CN109932964A (en) * | 2019-04-13 | 2019-06-25 | 上海亿算科技有限公司 | A kind of calculation power chip and calculation power chip system of connecting |
| CN110068809A (en) * | 2019-05-06 | 2019-07-30 | 成都泰格微电子研究所有限责任公司 | A kind of wave control processing module for phased-array radar |
| CN110661100A (en) * | 2019-10-08 | 2020-01-07 | 上海无线电设备研究所 | Phased array antenna beam control device and method |
| CN110661100B (en) * | 2019-10-08 | 2021-04-02 | 上海无线电设备研究所 | Phased array antenna beam control device and method |
| CN110703247A (en) * | 2019-10-30 | 2020-01-17 | 中国科学院电子学研究所 | Wave position information detection method, wave position information detection device and storage medium |
| CN112596030A (en) * | 2020-12-04 | 2021-04-02 | 南京理工大学 | Wave control method and system based on X-band unmanned aerial vehicle airborne SAR |
| CN112596030B (en) * | 2020-12-04 | 2023-12-01 | 南京理工大学 | Wave control method and system based on X-band unmanned aerial vehicle SAR |
| CN115267685A (en) * | 2022-09-23 | 2022-11-01 | 江苏万邦微电子有限公司 | Built-in microwave signal state data readback TR component wave control module |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105404208B (en) | 2018-06-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105404208A (en) | Cascadable wave control machine, wave control machine system and wave beam control method | |
| CN100394808C (en) | Feedback techinque of wireless system with several transmitting and receiving antennas | |
| CN102508215B (en) | Double-channel active and passive radar integrated simulator | |
| CN103051343B (en) | Feedback receiver for antenna tuner calculations and method for tuning antenna tuner | |
| CN102710316A (en) | All-digital satellite signal simulated source | |
| CN102804609A (en) | Parallel execution of trellis-based methods | |
| CN109298403B (en) | High-speed signal processing and beam control device and method | |
| US20220239371A1 (en) | Methods, devices, apparatuses, and medium for optical communication | |
| CN105891791B (en) | Multiple Target Signals generation method and radio frequency multi-target signal | |
| CN1983882B (en) | Radio-frequency front, system and method for measuring antenna feedback voltage resident wave ratio | |
| CN113625231A (en) | Phased array radar wave control system based on FPGA and self-checking method | |
| CN106603108A (en) | Transceiver and work method thereof | |
| CN104993888A (en) | System for testing bit error rate of high-speed serial chip and method for implementing same | |
| CN108365850A (en) | Coding method, code device and communication device | |
| CN102170327A (en) | Super forward error correction hardware decoding method and apparatus thereof | |
| CN102891685B (en) | Cardiopulmonary bypass in beating heart redundancy check computing circuit based on FPGA | |
| CN103543440B (en) | Based on the digital beam froming apparatus and method of FPGA programmable delay circuit | |
| Song et al. | Reliable wide-area backscatter via channel polarization | |
| CN101887130A (en) | Programmable navigational satellite spread spectrum sequence generator | |
| CN108736935A (en) | A kind of general down and out options method for extensive mimo system signal detection | |
| CN202068407U (en) | Vector antenna tuner | |
| CN104754249A (en) | Signal processing system for underwater imaging sonar | |
| CN101815348B (en) | Device and method for calculating digital signal power | |
| US6279139B1 (en) | Transmission system | |
| CN102664707B (en) | Method for determining logarithm likelihood ratio, Turbo encoding method and device thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180629 Termination date: 20201212 |