CN105391058A - Regional power grid anti-error network topology analysis method - Google Patents

Abstract

The invention discloses a network topology analysis method for error prevention in regional power grids, which includes the following steps: the first step is to analyze the wiring connection of the substation, and analyze how many calculation nodes the bus section of the substation is connected by the closed switch; the second step is to analyze the system Network analysis, connecting the topological nodes of the entire system by branches, and analyzing how many subsystems the system is divided into; the third step is the analysis of the measurement system, dividing the measurement system by subsystem, and checking the observability of each subsystem . The invention directly connects the connected grid equipment together, forms the network model required for calculation through equivalent processing of various grid equipment, and realizes the sharing of graphics and models based on the substation SVG graphics and CIM data model obtained from the monitoring system .

Description

A network topology analysis method for error prevention in regional power grid

technical field

The invention relates to a network error prevention topology analysis technology.

Background technique

The main primary operation equipment of the regional power grid includes generators, transformers, lines, busbars, parallel capacitor banks, etc. All kinds of power grid equipment are connected together through switches and switches to form a power grid. Changing the status of switches and switches can form different operations. Way. In order to be able to analyze and calculate in various operating modes, and to realize the anti-misjudgment of complex operation modes such as load shedding, ring closing/unlocking, mother-inverting, and bypassing under special operating modes, it is necessary to carry out calculations based on graphical connection relationships and model nodes. topological analysis.

Contents of the invention

The technical problem to be solved by the present invention is to provide a network topology analysis method for preventing errors in regional power grids. By analyzing the real-time status of switches and switches, the connected grid equipment is directly connected together, and various grid equipment is passed through Equivalent processing forms the network model required for calculation, so that the anti-misjudgment is not limited to the anti-misjudgment of conventional circuit breakers, isolating switches, grounding switches and ground wires, but also meets load shedding, ring closing/opening, Judgment of complex operation methods such as mother-inversion and sub-generation.

In order to solve the above-mentioned technical problems, the present invention adopts the following technical solutions: a network topology analysis method for regional power grid error prevention, including the following steps:

The first step is the connection analysis of the substation, analyzing how many calculation nodes the bus section of the substation is connected by the closed switch;

The second step is system network analysis, which connects the topological nodes of the entire system by branches and analyzes how many subsystems the system is divided into;

The third step is the measurement system analysis, which divides the measurement system by subsystem and checks the observability of each subsystem.

Furthermore, the basic algorithm of substation connection analysis adopts the stack principle, and the process of searching for the connection nodes contained in a certain bus by using the stack principle is as follows:

1) Each connection node and each switch are set with an unsearched mark;

2) Starting from a certain connection node, place this node on the first layer of the stack;

3) Push into the stack: Find the unsearched connection node of the connected unsearched closed switch by retrieving the switch element, place it in the next stack, and set the switch and the connection node as searched flags;

4) Back stack: If there is no unsearched closed switch at a certain connection node, or there is no unsearched connected node at the opposite end of the unsearched closed switch, then return one layer of stack;

5) Back to the starting node: the search process ends when the stack continues to be unstacked, and the search process of a bus is completed.

The fourth step is to search out the operation-related switches, isolation switches, and grounding switches from the SVG graphics and CIM models of the substation, including the graphic element information and layer information of various equipment, and perform various electrical operations. Discrimination of island, ground island, and connected branches, so that the anti-mistake topology can work correctly.

The grid error prevention network topology analysis method of the present invention directly connects the connected grid equipment together, and forms the network model required for calculation through equivalent processing of various grid equipment, and based on the substation SVG obtained from the monitoring system Graph and CIM data models realize graph model sharing.

Description of drawings

The present invention will be further described below in conjunction with accompanying drawing and specific embodiment:

Figure 1 is a schematic diagram of a general network model;

Figure 2 is a schematic diagram of substation wiring analysis;

Fig. 3 is a schematic diagram of the process of searching for connection nodes contained in a certain bus using the stack principle.

detailed description

Each power grid device has one or more terminals (Terminals) connected to other devices. These terminals are generally represented by an integer in the graphical description and are called nodes (Node). Nodes are collectively referred to as connectivity nodes before topology analysis. The connection node is the criterion for judging the connection between devices (connected through 0 impedance), such as the connection between the switch and the line, the switch and the switch, and the connection between the switch and the bus. The number of connected nodes is a large number, which is the basic description of the power grid and the basic input of topology analysis. The number of connected nodes is relatively constant. Topological node (Topological node) is composed of multiple connection nodes. It is a model node generated after topology analysis. It is connected together through closed switches and switches. It is the result of topology analysis. It is generally called a bus node (Bus). The number will change as the mode of operation changes.

Due to various reasons (mainly power grid accidents), a power grid may be split into multiple parts (subnets) to operate independently, and each independent subnet (Subnet) is called an electrical island (Topological island). Electrical islands are divided into live islands and dead islands according to the presence or absence of power injection, and grid calculations should be able to calculate each live island.

Switchgear is the most important power grid equipment in topology analysis, and its state change will change the structure of the network and the power grid model after topology analysis. The switchgear is a two-port device, and when the switch state is closed, it is generally called a zero-impedance branch. The main types of switchgear are: jumper, isolating switch (knife switch), circuit breaker (switch), fuse (fuse), load switch (only normal load current can be switched on and off).

An effective way to create a network description is to use the component's node description as part of the graphical device description. A component is a multi-port component, which is connected to the bus, ground and other equipment (such as lines, generators, etc.).

The description of information used in topology analysis such as connection nodes, topology nodes, and electrical islands in topology analysis is summarized as follows:

◆Each grid device has one or more endpoints;

◆Each endpoint belongs to a connection node;

◆A connection node is a member of a topological node, and a topological node is composed of multiple connection nodes.

A topology node is a member of an electrical island, and an electrical island consists of multiple nodes and branches. There are a large number of connected nodes in the network description, and it is very important to number the connected nodes accurately and quickly. It is the most ideal choice to realize the automation of connection node numbering according to some principles. Generally, the automation of numbering can be basically realized by using the 3-digit information of factory station number, component node number and component geometric coordinates.

As shown in Figure 1, the model of the general network (referring to the results after topology analysis), there are only two basic elements in the model of the general network: nodes and branches, and an electrical island in Figure 1 contains 10 nodes and 12 branches network of.

In the general network description, the node has potential and injection quantity, and the corresponding description in the power system includes bus voltage (amplitude and phase angle) and bus power injection (active power injection, reactive power injection). The general description of the branch includes power flow and impedance. In the power system, it corresponds to the power flow (active power flow, reactive power flow) and the impedance or equivalent impedance of the equipment.

Network topology analysis is a common function block, the main function is to model the network physics into a mathematical model for calculation according to the real-time switch status. Network topology analysis is the premise of various application software, used in various network analysis, such as state estimation, power flow calculation, voltage and reactive power optimization, fault analysis and dispatcher simulation training, etc.

The task of topology analysis is to process the change of switch information in real time, automatically divide the number of nodes used in the calculation of power plants and substations, form new network connections, and then distribute data such as measurement and injection data to provide new connections for related applications. information and data online.

Changes in the real-time switching status of the power system may be the removal or input of generators or loads; the calculation nodes corresponding to the bus section of the substation may change; it may also cause grid opening, loop closing, splitting, and paralleling. The real-time topology analysis of power system is characterized by a large number of complex logic operations accurately and quickly.

The first step of the network topology analysis is the connection analysis of the substation. The function is to analyze how many calculation nodes the bus section of the substation is connected by the closed switch. The result of substation connection analysis is to divide each substation into several nodes, which can also be called node analysis. That is to say, this step is to analyze the connection nodes on the graph system into discrete topological nodes.

As shown in Fig. 2 and Fig. 3, taking a double-and-a-half wiring plant as an example, the process of the plant using the stack method to complete the topology node search is explained.

The basic algorithm of this step adopts the "stack" principle---the search logic of last in first out. The process of searching for the connection nodes contained in a bus (topological node) using the stack principle is as follows:

1) Each connection node and each switch are set with an unsearched mark;

2) Starting from a certain connection node (such as the first connection node of the CBA1 switch), place this node on the first layer of the stack;

3) Push into the stack: by searching the switch element, find the unsearched connection node of the connected unsearched closed switch, and place it in the next stack (and set the switch and the connection node to the searched flag)

4) Back stack: If there is no unsearched closed switch at a certain connection node, or there is no unsearched connected node at the opposite end of the unsearched closed switch, then return one layer of stack;

5) Returning to the starting node (ie, the first stack): the search process ends when the stack continues to be withdrawn, and the search process of a bus (topological node) is completed.

The second step of network topology analysis is system network analysis. The task is to connect the topological nodes of the entire system by branches and analyze how many subsystems (electrical islands) the system is divided into. The result of the system network analysis is to divide the topological nodes with electrical connections into a subsystem. Under normal conditions where the system is not disintegrated, the entire network is a subsystem.

The second step is the same as the analysis process of the first step above, except that the connection node is replaced by a topological node, and the switching element is replaced by a double-ended branch, and the specific process is ignored.

The third step of network topology analysis is the measurement system analysis. The task is to divide the measurement system by subsystem and check the observability of each subsystem. The analysis results of the measurement system will meet the data requirements of the actual power system state estimation.

The number of switches in the actual network may reach hundreds to thousands. In order to meet the real-time requirements, network topology analysis should not only ensure reliable analysis of various complex connections, but also reduce the amount of calculation as much as possible.

Returning the calculation results to the corresponding data attribute fields of the original components is another process (reverse process) of topology analysis. According to the information formed during the forward search, the calculation results are correctly assigned to the external power grid description, and the assigned data will be directly applied to the human-machine interface.

The network topology analysis is characterized by the need for a large number of complex logic operations. In order to reduce the calculation workload and increase the calculation speed, we have adopted the following technologies: use the stack principle to analyze the substation connection and system connection analysis. In order to improve the online analysis speed, use Procedural skills such as assigning numbers and positive and negative association tables are used to avoid scanning searches.

In addition, there are two ways of network topology analysis: real-time and research. Network topology analysis can be started periodically or at any time.

The fourth step of network topology analysis is graphic analysis. Obtain substation SVG graphics and CIM data models from the monitoring system, use drawing tools to perform secondary modeling to complete the anti-error equipment model, and implement the current graphic-based equipment based on the topology anti-error rule language. Real-time anti-misjudgment of status.

Claims (2)

1. the anti-error network topology analytical method of area power grid, is characterized in that comprising the steps:

The first step is the Topology Analysis Based of transformer station, and the bus section, busbar section analyzing transformer station is connected into how much calculating node by Closing Switch;

Second step is grid analysis, and the topological node of whole system is tied by branch road, and analytical system is divided into how many subsystems;

3rd step is system for measuring quantity analysis, by system subdivision measurement system, and checks the observability of each subsystem.

2. the anti-error network topology analytical method of a kind of area power grid according to claim 1, is characterized in that: the rudimentary algorithm of the Topology Analysis Based of transformer station adopts stack mechanism, utilizes stack mechanism to search for the process of connected node contained by a certain bus as follows:

1) each connected node and each switch are put with non-search sign;

2) by a certain connected node, this node is placed in storehouse ground floor;

3) push on: by search switch element, find the connected node do not searched for of the Closing Switch of not searching for be connected, be placed in lower layer stack, and this switch and connected node are put search sign;

4) stack is moved back: a certain connected node without the Closing Switch of not searching for, or does not search for Closing Switch opposite end without not searching for connected node, then move back layer stack;

5) return to the node that sets out: when continuing to move back stack, terminate search procedure, complete the search procedure of a bus.