CN105390441B - A kind of method of through-hole pattern in improvement low dielectric coefficient medium layer - Google Patents
A kind of method of through-hole pattern in improvement low dielectric coefficient medium layer Download PDFInfo
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- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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Abstract
The invention belongs to semiconductor integrated circuit manufacturing process technology fields, disclose a kind of method for improving through-hole pattern in low dielectric coefficient medium layer, the following steps are included: providing semiconductor substrate first, and etching stop layer, compound medium layer and antireflection dielectric layer are sequentially formed on its surface；Then compound lithography layer is formed on the surface of antireflection dielectric layer；Then antagonistic reflex dielectric layer and compound medium layer carry out the etching of partial through holes；Surface plasma processing is carried out followed by the inner wall of the partial through holes to formation；Finally continue the etching of subsequent through-hole, completes whole through-hole structure.The present invention carries out plasma treatment after partial through holes structure is formed, to its inner wall surface, makes modified the first oxide layer for forming preset thickness in its surface, to improve etch resistance energy, and maintains established through-hole pattern, facilitates the whole pattern for improving through-hole.
Description
Technical field
The invention belongs to semiconductor integrated circuit manufacturing process technology fields, are related to a kind of improvement low dielectric coefficient medium layer
The method of middle through-hole pattern.
Background technique
With the continuous development of integrated circuit technique, after entering deep-submicron characteristic size, by road after semiconductor devices
Interconnection bring RC retardation ratio has become one of an important factor for influencing device performance, and which limit mentioning for integrated circuit frequency performance
It is high.To break through this limitation, constantly there is new interconnection material to be applied in semiconductor postchannel process, such as the copper of low-resistivity
The combination of metal and medium with low dielectric constant can be effectively improved the performance of interconnection line.About copper interconnection technology research and open
Hair has a decades so far to gradually reduce capacitor C constantly has new medium with low dielectric constant material to enter application field, by
This needs to carry out targetedly process optimization and new process development to a variety of different dielectric materials.
In the development process of various dielectric materials, by the adjustment of material structure and composition, drop dielectric constant gradually
It is low.Compared with traditional silica material, advanced low-k materials quality is more loose, wherein there are also holes, furthermore usually also
Other impurities element such as carbon is mixed to further decrease dielectric constant.It is tired that the above-mentioned change of dielectric material brings certain technology
Difficulty, such as dependency structure are easy collapse-deformation, metallic atom and are easier to diffusion in the medium.For technique realization, in rear road work
In skill, dual-damascene structure is quite mature integrated approach, and basic structure is groove and through-hole, and through-hole plays different interconnection layers
Between connection effect, pattern has close relationship to the electric property of subsequent metal fill process and device.In low dielectric
After the investment application of constant dielectric material, since the property of material itself makes the through-hole pattern of etching process control more difficult, appearance
Excessive lateral etching is easily caused in side wall, forms the through-hole pattern of bowing (bowing).To find out its cause, mainly etched
Constantly there are some ions laterally to bombard established throughhole portions in journey, increases aperture constantly.
Conventional dielectric etch gas is carbon fluorine class, can pass through regulating gas type, flow and other related process
Parameter, to control the yield of byproduct of reaction (polymer), to influence the pattern of formed through-hole.Patent No.
7838432 United States Patent (USP) proposes a kind of etch topography control means using negative bias voltage, high by-product, but this method
The main desired process results of adjustment realization by process conditions, the more complicated difficulty of process exploitation process, and not especially
It is developed for advanced low-k materials.Therefore, it is urgent to provide a kind of improvement low dielectric coefficient medium layers by those skilled in the art
The method of middle through-hole pattern, simplification of flowsheet reduce production cost.
Summary of the invention
In view of the above problems, in order to overcome the deficiencies of the prior art, improving low dielectric the purpose of the present invention is to provide a kind of
The method of through-hole pattern in constant dielectric layer, the surface after can etching to partial through holes are modified processing, enhance its corrosion stability
Can, to realize the improvement to through-hole entirety pattern, simplification of flowsheet reduces production cost.
In order to solve the above-mentioned technical problems, the present invention provides through-hole patterns in a kind of improvement low dielectric coefficient medium layer
Method, comprising the following steps:
Step S01, provides semiconductor substrate, and its surface sequentially form etching stop layer, compound medium layer and
Antireflection dielectric layer；
Step S02 forms compound lithography layer on the surface of the antireflection dielectric layer；
Step S03 carries out the etching of partial through holes to the antireflection dielectric layer and compound medium layer；
Step S04 carries out surface plasma processing to the inner wall of the partial through holes of formation, so that the partial through holes is interior
First oxide layer of wall surface formation preset thickness；
Step S05 continues the etching of subsequent through-hole, to form whole through-hole structure.
Preferably, in the step S01, using plasma enhancing chemical vapor deposition process forms the etching stopping
Layer, compound medium layer and antireflection dielectric layer.
Preferably, in the step S01, the material of the etching stop layer is in silicon nitride, silicon carbide or carbonitride of silicium
One kind or combinations thereof；The compound medium layer successively includes the second oxide layer, the first low dielectric coefficient medium layer from the bottom up
And second low dielectric coefficient medium layer；The material of the antireflection dielectric layer is silicon oxynitride.
Preferably, in the step S03, the etching stopping of the partial through holes is in first low dielectric coefficient medium layer
In, etching depth of the partial through holes in the first low dielectric coefficient medium layer isFirst low Jie
The material of constant dielectric layer is black diamond BD II, and the material of the second low dielectric coefficient medium layer is black diamond BDI.
Preferably, in the step S02, the step of forming compound lithography layer, includes:
Carbon spin-coating material layer is formed in the antireflection dielectric layer surface；
Siliceous anti-reflecting layer is formed in the carbon spin-on material layer surface；
In the siliceous anti-reflecting layer surface coating photoresist layer；
The photoresist layer is patterned, so as to form via hole image on the photoresist layer.
Preferably, in the step S03, the etching gas of the siliceous anti-reflecting layer is CF4And CHF3Combination, institute
The etching gas for stating carbon spin-coating material layer is CO, CO2Or combinations thereof, the etching gas of the antireflection dielectric layer is CF4And
CHF3Combination, the etching gas of first low dielectric coefficient medium layer and the second low dielectric coefficient medium layer is C4F8、N2
And the combination of Ar.
Preferably, in the step S04, the gas for carrying out surface plasma processing to the inner wall of the partial through holes is O2
And combination or the H of Ar2And N2Combination.
Preferably, the technological parameter of surface plasma processing is carried out to the inner wall of the partial through holes are as follows: O2Flow be
The flow of 100~150sccm, Ar are 50~70sccm, and the chamber pressure of plasma treatment is 50~70mtorr, the source 60MHz function
Rate range is 800~900W, and 2MHz bias power ranges are 200~300W, and plasma processing time is 50~80 seconds.
Preferably, the technological parameter of surface plasma processing is carried out to the inner wall of the partial through holes are as follows: H2Flow be
120~180sccm, N2Flow be 40~60sccm, chamber pressure 30~50mtorr, the 60MHz source power of plasma treatment
Range is 700~900W, and 2MHz bias power ranges are 200~300W, and plasma processing time is 60~120 seconds.
Preferably, in the step S05, the etching gas of the subsequent through-hole is C4F8、N2And the combination of Ar.
The present invention provides a kind of methods of through-hole pattern in improvement low dielectric coefficient medium layer, in partial through holes structure shape
Cheng Hou carries out plasma treatment to its inner wall surface, makes modified the first oxide layer for forming preset thickness in its surface, to improve
Etch resistance energy, and established through-hole pattern is maintained, facilitate the whole pattern for improving through-hole；Manufacturing process letter of the present invention
It is single, production cost is reduced, and preparation method and traditional CMOS technology are completely compatible.
Detailed description of the invention
It to describe the technical solutions in the embodiments of the present invention more clearly, below will be to needed in the embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1 is the flow diagram of through-hole pattern method in improvement low dielectric coefficient medium layer proposed by the present invention；
Fig. 2 a-2e is that the cross-section structure of each processing step through-hole in formation low dielectric coefficient medium layer proposed by the present invention shows
It is intended to.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to implementation of the invention
Mode is described in further detail.Those skilled in the art can understand easily the present invention by content disclosed by this specification
Other advantages and effect.The present invention can also be embodied or applied by other different embodiments, this explanation
Every details in book can also based on different viewpoints and application, without departing from the spirit of the present invention carry out various modifications or
Change.
Above and other technical characteristic and beneficial effect, will in conjunction with the embodiments and attached drawing is to low Jie of improvement proposed by the present invention
The method of through-hole pattern is described in detail in constant dielectric layer.Fig. 1 is improvement medium with low dielectric constant proposed by the present invention
The flow diagram of through-hole pattern method in layer；Fig. 2 a-2e is each work in formation low dielectric coefficient medium layer proposed by the present invention
The schematic diagram of the section structure of skill step through-hole.
Embodiment one
Referring to Fig. 1, the present invention provides a kind of methods of through-hole pattern in improvement low dielectric coefficient medium layer, including with
Lower step:
Step S01 provides semiconductor substrate 100, and sequentially forms etching stop layer 200, complex media on its surface
Layer 300 and antireflection dielectric layer 400.
A referring to figure 2., specifically, plasma enhanced chemical vapor deposition technique can be used and form etching in this step
Stop-layer 200, compound medium layer 300 and antireflection dielectric layer 400.Wherein, the material of etching stop layer 200 be silicon nitride,
One of silicon carbide or carbonitride of silicium or combinations thereof；Compound medium layer 300 from the bottom up successively include the second oxide layer 330,
First low dielectric coefficient medium layer 310 and the second low dielectric coefficient medium layer 320；The material of antireflection dielectric layer 400 is preferred
For silicon oxynitride.
The present embodiment etching stop layer 200 is preferably carbonitride of silicium (NDC) single thin film, using plasma enhancing chemistry
Vapor deposition (PECVD) technique is formed, with a thickness ofPreferablyCompound medium layer 300 be oxide layer,
The combinations of materials such as various low dielectric coefficient medium layers form, and in the present embodiment, are followed successively by the second oxide layer 330 from bottom to top
(TEOS), with a thickness ofPreferablyFor preventing in etching stop layer 200 nitrogen to the first low dielectric
The diffusion of constant dielectric layer 310；Be followed by the first low dielectric coefficient medium layer 310 material be preferably black diamond BD II (k~
2.55), with a thickness ofPreferablyThe material of second low dielectric coefficient medium layer 320 is preferably black
Diamond BDI (k~2.7), with a thickness ofPreferablyAntireflection dielectric layer 400 is preferably silicon oxynitride
(SiON) film, with a thickness ofPreferably
Preceding road technique is completed on semiconductor base 100 in this step, i.e., it is active to define device on a semiconductor substrate
Area simultaneously forms isolation structure, then forms gate structure and source, drain region.In addition, having formed contact hole and on semiconductor base
One metal layer, or N layers of interconnection architecture have been formed, this road is then N+1 layers of interconnection media layer.
Step S02 forms compound lithography layer 500 on the surface of antireflection dielectric layer 400.
B referring to figure 2., in this step, the step of forming compound lithography layer 500 includes: first in antireflection dielectric layer 400
Surface forms carbon spin-coating material layer 530；Then siliceous anti-reflecting layer 510 is formed on 530 surface of carbon spin-coating material layer；Then containing
510 surface coating photoresist layer 520 of silicon anti-reflecting layer；Photoresist layer 520 is finally patterned, so as to be formed on photoresist layer 520
Via hole image.
Different selections based on integrated technique, may include covering above antireflection dielectric layer 400 through patterned metallic hard
Mold layer (hard mask), such as TiN material do not give mark because property related to the present invention is little in figure.According to lithographic line width
Difference, compound lithography layer 500 can be two-layer structure (bottom anti-reflection layer BARC+ photoresist) or three-decker.The present embodiment
Photoetching relevant layers use three-decker, i.e., first one layer of spin coatingCarbon spin-coating material layer (spin-on carbon) 530,
Then it depositsSiliceous anti-reflecting layer (Si-ARC) 510, then applyArF photoresist 520 and make graphical.
The compound lithography layer 500 expands the adjustable process window in etching process to line width using carbon spin-coating material layer 530.This reality
It applies in example, the lithographic line width of via hole image is 45~55nm, is selected excellent for 50nm.
Step S03, antagonistic reflex dielectric layer 400 and compound medium layer 500 carry out the etching of partial through holes.
C referring to figure 2. in this step, is mask with the photoresist layer 520 with via hole image, etches each under it
Layer structure.The etching stopping of partial through holes is in the first low dielectric coefficient medium layer 310, and partial through holes are in the first low-k
Etching depth in dielectric layer 310 is(measuring from top to bottom).
Wherein, siliceous anti-reflecting layer 510 is etched first, and the etching gas of siliceous anti-reflecting layer 510 is CF4And CHF3's
Combination, specially CF4Flow be 90~110sccm, preferably 100sccm；CHF390~110sccm of flow, preferably
100sccm；100~120mtorr of chamber pressure, preferably 110mtorr；60MHz source power range is 700~900W, preferably
For 800W；2MHz bias power ranges be 80~120W, preferably 100W, etch period depending on thickness and etch rate,
Preferably 50 seconds.
Then carbon spin-coating material layer 530 is etched, the etching gas of carbon spin-coating material layer 530 is CO, CO2 or combinations thereof, sheet
Embodiment is pure gas CO2Flow be 150~250sccm, preferably 200sccm；Chamber pressure 10~20mtorr, it is excellent
It is selected as 15mtorr；60MHz source power range is 500~700W, preferably 600W；2MHz bias power, etch period are not added
Preferably 50 seconds.
Next etching antireflection dielectric layer 400, the etching gas of antireflection dielectric layer 400 are the group of CF4 and CHF3
It closes, specially CF4Flow be 70~90sccm, preferably 80sccm；CHF3Flow be 110~130sccm, preferably
120sccm；Chamber pressure is 90~110mtorr, preferably 100mtorr；60MHz source power range is 700~900W, preferably
For 800W；2MHz bias power ranges are 150~250W, and preferably 200W, etch period is preferably 27 seconds.
Followed by the second low dielectric coefficient medium layer 320 of etching and the first low dielectric coefficient medium layer 310, second low Jie
The etching gas of constant dielectric layer 320 and the first low dielectric coefficient medium layer 310 is C4F8、N2And the combination of Ar.Specifically
For C4F8Flow be 13~17sccm, preferably 15sccm；N2Flow be 150~250sccm, preferably 200sccm；Ar
Flow be 500~700sccm, preferably 600sccm；25~30mtorr of chamber pressure, preferably 28mtorr；The source 60MHz
Power bracket is 300~500W, preferably 400W；2MHz bias power ranges are 800~1200W, preferably 1000W, etching
Time is preferably 18 seconds according to required etching depth.
It is worth noting that process above parameter can be adjusted according to actual effect, etched in above-mentioned partial through holes
Cheng Hou, due to consumption of the superficial film in etching process, uppermost photoresist layer 520, siliceous anti-reflecting layer 510 are substantially
Depleted, the through-hole structure eventually formed is as shown in Figure 2 c.
Step S04 carries out surface plasma processing to the inner wall of the partial through holes of formation, so that the inner wall table of partial through holes
First oxide layer 340 of face formation preset thickness.
D referring to figure 2., in this step, the gas for carrying out surface plasma processing to the inner wall of partial through holes is O2And
The combination of Ar or H2And N2Combination, can remove the second low dielectric coefficient medium layer 320 and the first low dielectric coefficient medium layer
The carbon of 310 superficial layers is allowed to be changed into material i.e. the first oxide layer 340 of SixOy type.
Wherein, the technological parameter of surface plasma processing is carried out to the inner walls of partial through holes are as follows: the flow of O2 is 100~
150sccm, preferably 120sccm；The flow of Ar is 50~70sccm, preferably 60sccm；The chamber pressure of plasma treatment
For 50~70mtorr, preferably 60mtorr；60MHz source power range is 800~900W, preferably 850W；2MHz biases function
Rate range is 200~300W, and preferably 250W, plasma processing time is 50~80 seconds, preferably 60 seconds.
Alternatively, carrying out the technological parameter of surface plasma processing to the inner wall of the partial through holes are as follows: the flow of H2 is 120
~180sccm, preferably 150sccm；The flow of N2 is 40~60sccm, preferably 50sccm；The chamber pressure of plasma treatment
Strong 30~50mtorr, preferably 40mtorr；60MHz source power range is 700~900W, preferably 800W；2MHz biases function
Rate range is 200~300W, and preferably 250W, plasma processing time is 60~120 seconds, preferably 80 seconds.The condition can make
Second low dielectric coefficient medium layer, 320 surfaceIt is changed into oxide layer, and 310 surface of the first low dielectric coefficient medium layer is then
HaveIt is changed into oxide layer.Due to 310 to the second low dielectric coefficient medium layer of the first low dielectric coefficient medium layer, 320 structure
More loose, therefore, the thickness of the first oxide layer of surface 340 of the first low dielectric coefficient medium layer 310 is somewhat larger.
Step S05 continues the etching of subsequent through-hole, to form whole through-hole structure.
E referring to figure 2., in this step, the etching gas of subsequent through-hole is C4F8、N2And the combination of Ar, specially C4F8
Flow be 13~17sccm, preferably 15sccm；N2Flow be 150~250sccm, preferably 200sccm；The flow of Ar
For 500~700sccm, preferably 600sccm；20~28mtorr of chamber pressure, preferably 24mtorr；60MHz source power model
It encloses for 300~500W, preferably 400W；2MHz bias power ranges are 800~1200W, preferably 1000W, and etch period is excellent
It is selected as 14 seconds.Since aforementioned surfaces processing forms the side wall protection of the first oxide layer 340, the through-hole upper half in this road etching
Divide and maintain original pattern substantially, the whole pattern of through-hole is presented smooth consistent, etching process terminates at etching stop layer 200
It is interior.
It should be noted that above-mentioned all steps include that surface treatment needs to complete in same board, it can be single
Technique is carried out in chamber or different chamber, but whole process cannot expose atmosphere, otherwise can cause contamination and surface state
It is uncontrollable.
Embodiment two
Embodiment is surface-treated first is that being inserted into a step during via etch, may etch intersection in two steps
Slope has a small amount of variation.If device hardware allows, it can be spaced in etching and carry out corona treatment.For same film
Layer structure, after being etched to the second low dielectric coefficient medium layer 320, alternately etching and surface treatment step, such as first carve
Erosion 8 seconds/be then surface-treated 6 seconds, is repeated 4 times quarter to via bottoms.Whole smooth through-hole pattern, the reality can be obtained in this way
The mode of applying can also shorten the monolithic technology time to a certain extent, improve yield.
In conclusion the present invention provides a kind of methods of through-hole pattern in improvement low dielectric coefficient medium layer, in part
After through-hole structure is formed, plasma treatment is carried out to its inner wall surface, makes modified the first oxidation for forming preset thickness in its surface
Layer, to improve etch resistance energy, and maintains established through-hole pattern, facilitates the whole pattern for improving through-hole；The present invention
Manufacturing process is simple, reduces production cost, and preparation method and traditional CMOS technology are completely compatible.
Several preferred embodiments of the invention have shown and described in above description, but as previously described, it should be understood that the present invention
Be not limited to forms disclosed herein, should not be regarded as an exclusion of other examples, and can be used for various other combinations,
Modification and environment, and the above teachings or related fields of technology or knowledge can be passed through within that scope of the inventive concept describe herein
It is modified.And changes and modifications made by those skilled in the art do not depart from the spirit and scope of the present invention, then it all should be in this hair
In the protection scope of bright appended claims.
Claims (9)
1. a kind of method for improving through-hole pattern in low dielectric coefficient medium layer, which comprises the following steps:
Step S01 provides semiconductor substrate, and sequentially forms etching stop layer, compound medium layer and anti-reflective on its surface
Penetrate dielectric layer；
Step S02 forms compound lithography layer on the surface of the antireflection dielectric layer；
Step S03 carries out the etching of partial through holes to the antireflection dielectric layer and compound medium layer；
Step S04 carries out surface plasma processing to the inner wall of the partial through holes of formation, so that the inner wall table of the partial through holes
First oxide layer of face formation preset thickness；Wherein, the gas of the plasma treatment is O2And combination or the H of Ar2And N2
Combination, can remove compound medium layer low dielectric coefficient medium layer surface carbon, be allowed to be changed into the first oxide layer；
Step S05 continues the etching of subsequent through-hole, to form whole through-hole structure.
2. the method according to claim 1 for improving through-hole pattern in low dielectric coefficient medium layer, which is characterized in that described
In step S01, using plasma enhancing chemical vapor deposition process forms the etching stop layer, compound medium layer and resists
Reflecting medium layer.
3. the method according to claim 1 for improving through-hole pattern in low dielectric coefficient medium layer, which is characterized in that described
In step S01, the material of the etching stop layer is one of silicon nitride, silicon carbide or carbonitride of silicium or combinations thereof；It is described
Compound medium layer successively includes that the second oxide layer, the first low dielectric coefficient medium layer and the second low-k are situated between from the bottom up
Matter layer；The material of the antireflection dielectric layer is silicon oxynitride.
4. the method according to claim 3 for improving through-hole pattern in low dielectric coefficient medium layer, which is characterized in that described
In step S03, the etching stopping of the partial through holes is in first low dielectric coefficient medium layer, and the partial through holes are
Etching depth in one low dielectric coefficient medium layer isThe material of first low dielectric coefficient medium layer is
Black diamond BD II, the material of the second low dielectric coefficient medium layer are black diamond BDI.
5. the method according to claim 3 for improving through-hole pattern in low dielectric coefficient medium layer, which is characterized in that described
In step S02, the step of forming compound lithography layer, includes:
Carbon spin-coating material layer is formed in the antireflection dielectric layer surface；
Siliceous anti-reflecting layer is formed in the carbon spin-on material layer surface；
In the siliceous anti-reflecting layer surface coating photoresist layer；
The photoresist layer is patterned, so as to form via hole image on the photoresist layer.
6. the method according to claim 5 for improving through-hole pattern in low dielectric coefficient medium layer, which is characterized in that described
In step S03, the etching gas of the siliceous anti-reflecting layer is CF4And CHF3Combination, the etching of the carbon spin-coating material layer
Gas is CO, CO2Or combinations thereof, the etching gas of the antireflection dielectric layer is CF4And CHF3Combination, described first is low
The etching gas of dielectric coefficient medium layer and the second low dielectric coefficient medium layer is C4F8、N2And the combination of Ar.
7. the method according to claim 1 for improving through-hole pattern in low dielectric coefficient medium layer, which is characterized in that institute
The inner wall for stating partial through holes carries out the technological parameter of surface plasma processing are as follows: O2Flow be 100~150sccm, the stream of Ar
Amount is 50~70sccm, and the chamber pressure of plasma treatment is 50~70mtorr, and 60MHz source power range is 800~900W,
2MHz bias power ranges are 200~300W, and plasma processing time is 50~80 seconds.
8. the method according to claim 1 for improving through-hole pattern in low dielectric coefficient medium layer, which is characterized in that institute
The inner wall for stating partial through holes carries out the technological parameter of surface plasma processing are as follows: H2Flow be 120~180sccm, N2Flow
For 40~60sccm, chamber pressure 30~50mtorr, 60MHz the source power range of plasma treatment is 700~900W, 2MHz
Bias power ranges are 200~300W, and plasma processing time is 60~120 seconds.
9. the method according to claim 1 for improving through-hole pattern in low dielectric coefficient medium layer, which is characterized in that described
In step S05, the etching gas of the subsequent through-hole is C4F8、N2And the combination of Ar.
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