CN105390434A - Semiconductor device, manufacturing method therefor, and electronic device - Google Patents
Semiconductor device, manufacturing method therefor, and electronic device Download PDFInfo
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- CN105390434A CN105390434A CN201410453163.5A CN201410453163A CN105390434A CN 105390434 A CN105390434 A CN 105390434A CN 201410453163 A CN201410453163 A CN 201410453163A CN 105390434 A CN105390434 A CN 105390434A
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- insulating barrier
- bottom wafers
- wafer
- semiconductor device
- salient point
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Abstract
The invention relates to a semiconductor device, a manufacturing method therefor, and an electronic device. The method comprises the steps: S1, providing a bottom wafer; S2, forming an insulating layer on the bottom wafer, and forming a plurality of interconnection through holes in the insulating layer, so as to connect the bottom wafer; S3, providing a top wafer, and forming a plurality of convex points, matched with the interconnection through holes, on the top wafer; S4, enabling the interconnection through holes to be connected with the convex points, so as to form a flip chip. The method is advantageous in that (1) the method reduces the technology of one-time Bump, and reduces the technological cost; (2) the method reduces one wafer serving as an interlayer (Interposer) and the interlayer technology, and increases the output; (3) the method takes organic matters as insulating materials, reduces the risks of electric leakage, and improves the capability of breakdown resistance.
Description
Technical field
The present invention relates to semiconductor applications, particularly, the present invention relates to a kind of semiconductor device and preparation method thereof, electronic installation.
Background technology
At consumer electronics field, multifunctional equipment is more and more subject to liking of consumer, compared to the simple equipment of function, multifunctional equipment manufacturing process will be more complicated, such as need the chip of integrated multiple difference in functionality in circuit version, thus there is 3D integrated circuit (integratedcircuit, IC) technology, 3D integrated circuit (integratedcircuit, IC) a kind of system-level integrated morphology is defined as, multiple chip is stacking in vertical plane direction, thus saving space, multiple pin can be drawn as required in the marginal portion of each chip, utilize these pins as required, by interconnected by metal wire for the chip needing to be connected to each other, but still there is a lot of deficiency in aforesaid way, such as stacked chips quantity is more, and the annexation more complicated between chip, can need to utilize many metal line, final wire laying mode is more chaotic, and volume can be caused to increase.
Therefore, at present at described 3D integrated circuit (integratedcircuit, IC) silicon through hole (ThroughSiliconVia is mostly adopted in technology, TSV), silicon through hole is a kind of perpendicular interconnection penetrating Silicon Wafer or chip, the preparation method of TSV can hole (via) with etching or laser mode on Silicon Wafer, then with electric conducting material as the materials such as copper, polysilicon, tungsten fill up, thus it is interconnected to realize between different silicon chip.
Usually select the 3rd wafer (Wafer) as intermediary layer (Interposer) in wafer current engaging process, by flipchip bump technique (Bump), three wafer (Wafer) are linked together, carries out Signal transmissions.But described method not only increases the number of the step of technique, improves product cost, and reduce output (Throughput), have impact on shipment amount.
Therefore need to be improved further, to eliminate the problems referred to above current described method.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
The present invention, in order to overcome current existing problems, provides a kind of preparation method of semiconductor device, comprising:
Step S1: bottom wafers is provided;
Step S2: form insulating barrier in described bottom wafers, and in described insulating barrier, form some through-hole interconnections, to connect described bottom wafers;
Step S3: provide top wafer, described top wafer is formed the salient point that some and described through-hole interconnection matches;
Step S4: be connected with described salient point by described through-hole interconnection, to form flip-chip.
Alternatively, the described bottom wafers in described step S1 comprises storage wafer.
Alternatively, the described insulating barrier in described step S2 selects organic insulating material.
Alternatively, the described insulating barrier in described step S2 selects polyimides.
Alternatively, in described step S2, the method forming described insulating barrier comprises: in described bottom wafers, form insulation coating, then cure, to form described insulating barrier.
Alternatively, described step S2 comprises:
Step S21: form insulating barrier in described bottom wafers, to cover described bottom wafers;
Step S22: insulating barrier described in patterning, to form some openings, exposes described bottom wafers;
Step S23: filled conductive material layer in said opening, to form described through-hole interconnection.
Alternatively, described step S23 comprises:
Step S231: the Seed Layer of plated metal Cu in said opening;
Step S232: form Ni metal in said opening by the method for Cu electroplating, to fill described opening.
Alternatively, described top wafer comprises application-specific integrated circuit (ASIC).
Present invention also offers a kind of semiconductor device, comprising:
Bottom wafers;
Insulating barrier, is positioned at the top of described bottom wafers;
Through-hole interconnection, is arranged in described insulating barrier, and is connected with described bottom wafers;
Top wafer, is positioned at the top of described insulating barrier, and wherein, described top wafer is formed with salient point, and described salient point is connected with described through-hole interconnection.
Alternatively, described insulating barrier comprises polyimides.
Alternatively, described bottom wafers comprises storage wafer;
Described top wafer comprises application-specific integrated circuit (ASIC).
Present invention also offers a kind of electronic installation, comprise above-mentioned semiconductor device.
The present invention is in order to solve problems of the prior art, provide a kind of preparation method of semiconductor device, technological process is changed to realize the structure of silicon through hole intermediary layer in described method, wafer of the prior art is replaced as insulating material by selecting organic substance, not only reduce the risk of electric leakage, but also decrease a wafer.
The invention has the advantages that:
(1) decrease salient point (Bump) technique, reduce process costs.
(2) decrease a slice as the wafer of intermediary layer (Interposer) and intermediary layer technique, add shipment amount.
(3) use organic substance as insulating material, reduce the risk of electric leakage, improve breakdown characteristics.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining device of the present invention and principle.In the accompanying drawings,
Fig. 1 a-1d is the preparation process generalized section of semiconductor device in prior art;
Fig. 2 a-2f is the preparation process generalized section of semiconductor device in an embodiment of the present invention;
Fig. 3 is preparation technology's flow chart of semiconductor device in an embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
Should be understood that, the present invention can implement in different forms, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiments will expose thoroughly with complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, in order to clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or layer time, its can directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, or the element that can exist between two parties or layer.On the contrary, when element be called as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer time, then there is not element between two parties or layer.Although it should be understood that and term first, second, third, etc. can be used to describe various element, parts, district, floor and/or part, these elements, parts, district, floor and/or part should not limited by these terms.These terms be only used for differentiation element, parts, district, floor or part and another element, parts, district, floor or part.Therefore, do not departing under the present invention's instruction, the first element discussed below, parts, district, floor or part can be expressed as the second element, parts, district, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " below ", " ... under ", " ... on ", " above " etc., here can be used thus the relation of the element of shown in description figure or feature and other element or feature for convenience of description.It should be understood that except the orientation shown in figure, spatial relationship term intention also comprises the different orientation of the device in using and operating.Such as, if the device upset in accompanying drawing, then, be described as " below other element " or " under it " or " under it " element or feature will be oriented to other element or feature " on ".Therefore, exemplary term " ... below " and " ... under " upper and lower two orientations can be comprised.Device can additionally orientation (90-degree rotation or other orientation) and as used herein spatial description language correspondingly explained.
The object of term is only to describe specific embodiment and not as restriction of the present invention as used herein.When this uses, " one ", " one " and " described/to be somebody's turn to do " of singulative is also intended to comprise plural form, unless context is known point out other mode.It is also to be understood that term " composition " and/or " comprising ", when using in this specification, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other feature, integer, step, operation, element, the existence of parts and/or group or interpolation.When this uses, term "and/or" comprises any of relevant Listed Items and all combinations.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, to explain technical scheme of the present invention.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
The preparation method of current semiconductor device as is shown in figs. la to ld, wherein, first provides the first wafer 101, and performs salient point generating process (Bump), to form some joint salient points 10 on described first wafer 101, as shown in Figure 1a.
Then the second wafer 102 is provided, same execution salient point generating process (Bump), to form some joint salient points 11 on described second wafer 102, as shown in Figure 1 b.
3rd wafer 103 being provided, in wherein said 3rd wafer 103, being formed with some silicon through holes 104 (TSV), connecting for realizing, as illustrated in figure 1 c.
Or select the 3rd wafer 103 as intermediary layer (Interposer), by flipchip bump technique (Bump), the first wafer 101, second wafer 102 and the 3rd wafer 103 are linked together, carries out Signal transmissions, as shown in Figure 1 d.But described method not only increases the number of the step of technique, improves product cost, and reduce output (Throughput), have impact on shipment amount.
Therefore need to be improved further current described method, to eliminate this problem.
Embodiment 1
The present invention, in order to solve problems of the prior art, provides a kind of preparation method of semiconductor device, is described further described method below in conjunction with accompanying drawing 2a-2f.
First, perform step 201 and bottom wafers 201 is provided.
Particularly, as shown in Figure 2 a, wherein said bottom wafers 201 for storing (memory) wafer, such as, can be formed with various memory device or unit in described bottom wafers.
Alternatively, other active or passive device can also be formed with in described bottom wafers, be not limited to a certain, do not repeat them here.
Perform step 202, described bottom wafers 201 forms insulating barrier 202.
Particularly, as shown in Figure 2 b, in described bottom wafers 201, insulating barrier 202 is formed in this step, to cover described bottom wafers 201 completely, alternatively, described insulating barrier 202 selects organic insulating material, not only can reduce the risk of electric leakage, can also breakdown characteristics be improved.
Alternatively, described insulating barrier 202 can select polyimides.
Further, the method forming described insulating barrier 202 can comprise: in described bottom wafers 201, form insulation coating, then cure, be cured, to form described insulating barrier 202, but the method forming described insulating barrier 202 is also not limited to this example.
Perform step 203, insulating barrier 202 described in patterning, to form some openings, exposes described bottom wafers 201.
Particularly, as shown in Figure 2 c, first formed on described insulating barrier 202 in this step and there is the mask layer of described opening, then with described mask layer for insulating barrier described in mask etch 202, so that described opening is transferred in described insulating barrier 202.
Alternatively, deep ion reaction etching can be selected in the step of the described insulating barrier 202 of etching, to form described opening, but also be not limited to described method.Particularly, in described deep reaction ion etching (DRIE) step, gas hexa-fluoride (SF is selected
6) as process gas, apply radio-frequency power supply, make hexa-fluoride react air inlet and form high ionization, controlling operating pressure in described etching step is 20mTorr-8Torr, frequently power is 600W, 13.5MHz, and direct current (DC) bias can continuous control in-500V-1000V.
Perform step 204, in said opening filled conductive material layer, to form described through-hole interconnection 20.
Particularly, as shown in Figure 2 d, filled conductive material layer in said opening in this step, to form described through-hole interconnection 20, is used for connecting described bottom wafers 201, realizes encapsulation in subsequent steps.
Wherein, the metal that described electric conducting material can select this area conventional or other materials, be not limited to a certain, alternatively, select metallic copper to form described through-hole interconnection in this step.
Particularly, the Seed Layer of plated metal copper first in said opening in this step, the deposition process of described Seed Layer can select chemical vapour deposition (CVD) (CVD) method, physical vapour deposition (PVD) (PVD) method or ald (ALD) method etc.
Then the method for Cu electroplating (ECP) is selected to form described metallic copper, as preferably, additive can also be used when electroplating, described additive is smooth dose (LEVELER), accelerator (ACCELERATORE) and inhibitor (SUPPRESSOR).
As preferably, forming the step that can also comprise annealing after described metallic copper is formed further, annealing can carry out 2-4 hour at 80-160 DEG C, to impel copper crystallization again, crystal grain of growing up, reduces resistance and improves stability.
Then metallic copper material described in planarization is to described insulating barrier 202, to form described through-hole interconnection 20, as shown in Figure 2 d.
In the process, directly be connected between described bottom wafers 201 and described through-hole interconnection, and in prior art, be generally salient point (bump) technique, therefore described method reduces salient point (bump) technique relative to conventional method, can reduce process costs further.
Perform step 205, top wafer 203 is provided, described top wafer 203 is formed with the salient point 204 that some and described through-hole interconnection matches.
Particularly, as shown in Figure 2 e, described top wafer 203 can comprise application-specific integrated circuit (ASIC) (ASIC) etc. in this step.
Wherein, described top wafer 203 is formed with the salient point 204 that some and described through-hole interconnection matches, the technique forming described salient point 204 can be salient point (Bump) technique.
Alternatively, the method forming described salient point can comprise polyimide pattern preparation, parent metal deposition, photoresist deposition and pattern preparation, plating, photoresist and remove photoresist and parent metal etching, and the step such as stream again, but be also not limited to cited method, other alternative methods that ability is conventional can also be selected, do not repeat them here.
Wherein, the position of described salient point 204 and described through-hole interconnection 20 one_to_one corresponding, be integrated to ensure to engage in subsequent steps.
Perform step 206, described through-hole interconnection 20 is connected with described salient point 204, to form flip-chip.
Particularly, as shown in figure 2f, in this step described through-hole interconnection 20 and described salient point 204 are aimed at joint and be integrated, to complete encapsulation, the method that wherein said joint method can select this area conventional, is not limited to a certain.
The present invention is in order to solve problems of the prior art, provide a kind of preparation method of semiconductor device, technological process is changed to realize the structure of silicon through hole intermediary layer in described method, such as by selecting organic substance to replace wafer of the prior art as insulating material, not only reduce the risk of electric leakage, but also decrease a wafer.
The invention has the advantages that:
(1) decrease salient point (Bump) technique, reduce process costs.
(2) decrease a slice as the wafer of intermediary layer (Interposer) and intermediary layer technique, add shipment amount.
(3) use organic substance as insulating material, reduce the risk of electric leakage, improve breakdown characteristics.
Fig. 3 is preparation technology's flow chart of semiconductor device in an embodiment of the present invention, comprises the following steps:
Step S1: bottom wafers is provided;
Step S2: form insulating barrier in described bottom wafers, and in described insulating barrier, form some through-hole interconnections, to connect described bottom wafers;
Step S3: provide top wafer, described top wafer is formed the salient point that some and described through-hole interconnection matches;
Step S4: be connected with described salient point by described through-hole interconnection, to form flip-chip.
Embodiment 2
Present invention also offers a kind of semiconductor device, comprising:
Bottom wafers 201;
Insulating barrier 202, is positioned at the top of described bottom wafers;
Through-hole interconnection 20, is arranged in described insulating barrier, and is connected with described bottom wafers;
Top wafer 203, is positioned at the top of described insulating barrier, and wherein, described top wafer is formed with salient point 204, and described salient point is connected with described through-hole interconnection.
Wherein, described bottom wafers 201 for storing wafer, such as, can be formed with various memory device or unit in described bottom wafers.Alternatively, various active or passive device can also be formed with in described bottom wafers, be not limited to a certain, do not repeat them here.
Described insulating barrier 202 selects organic insulating material, not only can reduce the risk of electric leakage, can also improve breakdown characteristics.Alternatively, described insulating barrier 202 can select polyimides.
Directly be connected between bottom wafers 201 and described through-hole interconnection described in described semiconductor device, and in prior art, be generally salient point (bump) technique, therefore described method reduces salient point (bump) technique relative to conventional method, can reduce process costs further.
Described top wafer comprises application-specific integrated circuit (ASIC).
Semiconductor device of the present invention can select method preparation described in embodiment 1 alternatively, selects organic insulator as intermediary layer (Interposer), add shipment amount, reduce the risk of electric leakage, improve breakdown characteristics in described device.
Embodiment 3
Present invention also offers a kind of electronic installation, comprise the semiconductor device described in embodiment 2.Wherein, semiconductor device is the semiconductor device described in embodiment 2, or the semiconductor device that the preparation method according to embodiment 1 obtains.
The electronic installation of the present embodiment, can be mobile phone, panel computer, notebook computer, net book, game machine, television set, VCD, DVD, navigator, camera, video camera, recording pen, any electronic product such as MP3, MP4, PSP or equipment, also can be any intermediate products comprising described semiconductor device.The electronic installation of the embodiment of the present invention, owing to employing above-mentioned semiconductor device, thus has better performance.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (12)
1. a preparation method for semiconductor device, comprising:
Step S1: bottom wafers is provided;
Step S2: form insulating barrier in described bottom wafers, and in described insulating barrier, form some through-hole interconnections, to connect described bottom wafers;
Step S3: provide top wafer, described top wafer is formed the salient point that some and described through-hole interconnection matches;
Step S4: be connected with described salient point by described through-hole interconnection, to form flip-chip.
2. method according to claim 1, is characterized in that, the described bottom wafers in described step S1 comprises storage wafer.
3. method according to claim 1, is characterized in that, the described insulating barrier in described step S2 selects organic insulating material.
4. the method according to claim 1 or 3, is characterized in that, the described insulating barrier in described step S2 selects polyimides.
5. method according to claim 1, is characterized in that, in described step S2, the method forming described insulating barrier comprises: in described bottom wafers, form insulation coating, then cure, to form described insulating barrier.
6. method according to claim 1, is characterized in that, described step S2 comprises:
Step S21: form insulating barrier in described bottom wafers, to cover described bottom wafers;
Step S22: insulating barrier described in patterning, to form some openings, exposes described bottom wafers;
Step S23: filled conductive material layer in said opening, to form described through-hole interconnection.
7. method according to claim 6, is characterized in that, described step S23 comprises:
Step S231: the Seed Layer of plated metal Cu in said opening;
Step S232: form Ni metal in said opening by the method for Cu electroplating, to fill described opening.
8. method according to claim 1, is characterized in that, described top wafer comprises application-specific integrated circuit (ASIC).
9. a semiconductor device, comprising:
Bottom wafers;
Insulating barrier, is positioned at the top of described bottom wafers;
Through-hole interconnection, is arranged in described insulating barrier, and is connected with described bottom wafers;
Top wafer, is positioned at the top of described insulating barrier, and wherein, described top wafer is formed with salient point, and described salient point is connected with described through-hole interconnection.
10. device according to claim 9, is characterized in that, described insulating barrier comprises polyimides.
11. devices according to claim 9, is characterized in that, described bottom wafers comprises storage wafer;
Described top wafer comprises application-specific integrated circuit (ASIC).
12. 1 kinds of electronic installations, comprise the semiconductor device that one of claim 9 to 11 is described.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410453163.5A CN105390434A (en) | 2014-09-05 | 2014-09-05 | Semiconductor device, manufacturing method therefor, and electronic device |
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| CN201410453163.5A CN105390434A (en) | 2014-09-05 | 2014-09-05 | Semiconductor device, manufacturing method therefor, and electronic device |
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| CN105390434A true CN105390434A (en) | 2016-03-09 |
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| CN201410453163.5A Pending CN105390434A (en) | 2014-09-05 | 2014-09-05 | Semiconductor device, manufacturing method therefor, and electronic device |
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Cited By (1)
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| CN110648932A (en) * | 2019-11-28 | 2020-01-03 | 长江存储科技有限责任公司 | Semiconductor chip and manufacturing method thereof |
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