CN105375993A - Eye diagram construction display device - Google Patents
Eye diagram construction display device Download PDFInfo
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- CN105375993A CN105375993A CN201410442193.6A CN201410442193A CN105375993A CN 105375993 A CN105375993 A CN 105375993A CN 201410442193 A CN201410442193 A CN 201410442193A CN 105375993 A CN105375993 A CN 105375993A
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- equalizer
- display unit
- electrically connected
- eye pattern
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Abstract
The invention discloses an eye diagram construction display device. The device comprises an amplifier, a first equalizer, an addition unit, a second equalizer, an error rate check unit, a frequency replying unit, a frequency synthesizer, a processing unit and a display unit. The first equalizer is electrically connected to the amplifier. The addition unit is electrically connected to the first equalizer. The second equalizer is electrically connected to the addition unit. The error rate check unit is electrically connected to the addition unit. The frequency replying unit is electrically connected to the addition unit and the error rate check unit. The frequency synthesizer is electrically connected to the frequency replying unit. The processing unit is electrically connected to the addition unit, the error rate check unit and the frequency replying unit. The display unit is electrically connected to the processing unit.
Description
Technical field
The present invention relates to a kind of display unit, particularly relate to a kind of eye pattern construction display unit.
Background technology
Chip (such as integrated circuit) is one of most important hardware in the middle of modern electronics; Different chips is in order to exchange information with one another (comprising data, message and instruction etc.), and chip contains transfer circuit and receiving circuit; The transfer circuit of one chip transmits the receiving circuit of information to another chip.
When receiving circuit receives signal, receiving circuit can restore information in the middle of the signal received.And such as Ethernet, fiber optic network, XAUI(10GigabitMediaIndependentInterface), PCI-E(PeripheralComponentInterconnectExpress) and SATA(SerialAdvancedTechnologyAttachment) be all the common interface standard of Modern High-Speed chip.
Correctly can restore information in the middle of the signal received in order to ensure receiving circuit, monitor that the eye pattern of the signal received by receiving circuit is very useful; Therefore, correctly monitor that the eye pattern of the signal received by receiving circuit has become the key of modern chips design.But the eye pattern construction display unit of current correlation technique has design complicated and the shortcoming that price is very expensive.
Summary of the invention
In view of this, for improving the shortcoming of above-mentioned prior art, main purpose of the present invention is to provide a kind of eye pattern construction display unit.
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of eye pattern construction display unit, be applied to a data crossfire (datastream), this eye pattern construction display unit comprises: an amplifier, this data crossfire of this amplifier accepts; One first equalizer, this first equalizer is electrically connected to this amplifier; One adder unit, this adder unit is electrically connected to this first equalizer; One second equalizer, this second equalizer is electrically connected to this adder unit; One error rate checks unit, and this error rate is checked unit and is electrically connected to this adder unit; One frequency restoration unit, this frequency restoration unit is electrically connected to this adder unit and this error rate checks unit; One frequency synthesizer (clocksynthesizer), this frequency synthesizer is electrically connected to this frequency restoration unit; One processing unit, this processing unit is electrically connected to this adder unit, this error rate checks unit and this frequency restoration unit; And a display unit, this display unit is electrically connected to this processing unit.
Moreover eye pattern construction display unit as above, wherein this amplifier can be such as but the present invention is not defined as a variable gain amplifier (variablegainamplifier).
Moreover eye pattern construction display unit as above, wherein this first equalizer can be such as but the present invention is not defined as a feed forward equalizer (feedforwardequalizer).
Moreover, eye pattern construction display unit as above, wherein this second equalizer can be such as but the present invention be not defined as one decision-making feedback equalizer (decisionfeedbackequalizer).
Moreover eye pattern construction display unit as above, wherein this adder unit can be such as but the present invention is not defined as an adder.
Moreover eye pattern construction display unit as above, wherein this error rate is checked unit and to be can be such as but the present invention is not defined as an error rate collating circuit.
Moreover eye pattern construction display unit as above, wherein this frequency restoration unit can be such as but the present invention is not defined as a frequency restoration circuit.
Moreover eye pattern construction display unit as above, wherein this display unit can be such as but the present invention is not defined as a display.
Moreover eye pattern construction display unit as above, wherein this processing unit can be such as but the present invention is not defined as a microprocessor or a microcontroller.
Eye pattern construction display unit provided by the present invention, has simplicity of design and the advantage of low cost.
Accompanying drawing explanation
Fig. 1 is the eye pattern construction display unit calcspar of the present invention.
Fig. 2 is the partial schematic diagram of one of the eye serial signal of the present invention embodiment.
Fig. 3 is one of eye pattern signal of the present invention embodiment schematic diagram.
[primary clustering symbol description]
Eye pattern construction display unit 10
Data stream 20
Amplifier 102
First equalizer 104
Adder unit 106
Second equalizer 108
The error rate checks unit 110
Frequency restoration unit 112
Frequency synthesizer 114
Processing unit 116
Display unit 118
Amplification data crossfire 120
First equalizing signal 122
Second equalizing signal 124
Add up equalizing signal 126
Frequency synthesized signal 128
Frequency restoration signal 130
Bit error rate signal 132
Eye pattern signal 134.
Embodiment
Below in conjunction with accompanying drawing and embodiments of the invention, eye pattern construction display unit of the present invention is described in further detail.
Please refer to Fig. 1, it is the eye pattern construction display unit calcspar of the present invention.One eye pattern construction display unit 10 is applied to a data crossfire 20(datastream); This eye pattern construction display unit 10 comprises amplifier 102,1 first equalizer 104, adder unit 106,1 second equalizer 108, error rate and checks unit 110, frequency restoration unit 112, frequency synthesizer 114(clocksynthesizer), processing unit 116 and a display unit 118.
This amplifier 102 receives this data crossfire 20; This first equalizer 104 is electrically connected to this amplifier 102; This adder unit 106 is electrically connected to this first equalizer 104; This second equalizer 108 is electrically connected to this adder unit 106; This error rate is checked unit 110 and is electrically connected to this adder unit 106.
This frequency restoration unit 112 is electrically connected to this adder unit 106 and this error rate checks unit 110; This frequency synthesizer 114 is electrically connected to this frequency restoration unit 112; This processing unit 116 is electrically connected to this adder unit 106, this error rate checks unit 110 and this frequency restoration unit 112; This display unit 118 is electrically connected to this processing unit 116.
This amplifier 102 can be such as but the present invention is not defined as a variable gain amplifier (variablegainamplifier); This first equalizer 104 can be such as but the present invention is not defined as a feed forward equalizer (feedforwardequalizer); This second equalizer 108 can be such as but the present invention is not defined as decision-making back coupling equalizer (decisionfeedbackequalizer); This adder unit 106 can be such as but the present invention is not defined as an adder.
This error rate is checked unit 110 and to be can be such as but the present invention is not defined as an error rate collating circuit; This frequency restoration unit 112 can be such as but the present invention is not defined as a frequency restoration circuit; This display unit 118 can be such as but the present invention is not defined as a display; This processing unit 116 can be such as but the present invention is not defined as a microprocessor or a microcontroller.
After this amplifier 102 receives this data crossfire 20, this amplifier 102 amplifies this data crossfire 20 to obtain an amplification data crossfire 120 in variable gain mode; This amplifier 102 transmits this amplification data crossfire 120 to this first equalizer 104.
After this first equalizer 104 receives this amplification data crossfire 120, this first equalizer 104 processes this amplification data crossfire 120 to obtain one first equating signal 122; This first equalizer 104 transmits this first equating signal 122 to this adder unit 106.
This second equalizer 108 transmits one second equating signal 124 to this adder unit 106; After this adder unit 106 receives this first equating signal 122 and this second equating signal 124, this adder unit 106 adds up this first equating signal 122 with this second equating signal 124 to obtain a summed equalized signal 126; This adder unit 106 transmits this summed equalized signal 126 to this error rate and checks unit 110, this frequency restoration unit 112 and this processing unit 116.
This frequency synthesizer 114 transmits a frequency synthesized signal 128 to this frequency restoration unit 112; After this frequency restoration unit 112 receives this summed equalized signal 126 and this frequency synthesized signal 128, this frequency restoration unit 112 produces a frequency restoration signal 130; This frequency restoration unit 112 transmits this frequency restoration signal 130 to this error rate and checks unit 110 and this processing unit 116.
Check after unit 110 receives this summed equalized signal 126 and this frequency restoration signal 130 in this error rate, this error rate is checked unit 110 and is checked the error rate of this summed equalized signal 126 to obtain a bit error rate signal 132; This error rate is checked unit 110 and is transmitted this bit error rate signal 132 to this processing unit 116.
After this processing unit 116 receives this summed equalized signal 126, this frequency restoration signal 130 and this bit error rate signal 132, this processing unit 116 processes this summed equalized signal 126, this frequency restoration signal 130 with this bit error rate signal 132 to obtain serial signal at a glance; This serial signal comprises most eye signals; Please refer to Fig. 2, it is the partial schematic diagram of one of the eye serial signal of the present invention embodiment.
This processing unit 116 takes out the half of the eye signal on the eye signal of a centre of this serial signal and the both sides of the eye signal of this centre, to obtain an eye pattern signal 134; This processing unit 116 scans (histogramscanning), bilinearity interpolation (bilinearinterpolation) and two cube interpolation (bicubicinterpolation) with rectangular bar statistical chart and processes this eye pattern signal 134; This processing unit 116 amplifies this eye pattern signal 134; This processing unit 116 transmits this eye pattern signal 134 to this display unit 118.
After this display unit 118 receives this eye pattern signal 134, this display unit 118 shows this eye pattern signal 134.Please refer to Fig. 3, it is one of eye pattern signal of the present invention embodiment schematic diagram.
The invention has the advantages that and provide a kind of simplicity of design and the eye pattern construction display unit of low cost.
The above, be only preferred embodiment of the present invention, be not intended to limit protection scope of the present invention.
Claims (10)
1. an eye pattern construction display unit, is applied to a data crossfire, it is characterized in that, this eye pattern construction display unit comprises:
One amplifier, this data crossfire of this amplifier accepts;
One first equalizer, this first equalizer is electrically connected to this amplifier;
One adder unit, this adder unit is electrically connected to this first equalizer;
One second equalizer, this second equalizer is electrically connected to this adder unit;
One error rate checks unit, and this error rate is checked unit and is electrically connected to this adder unit;
One frequency restoration unit, this frequency restoration unit is electrically connected to this adder unit and this error rate checks unit;
One frequency synthesizer, this frequency synthesizer is electrically connected to this frequency restoration unit;
One processing unit, this processing unit is electrically connected to this adder unit, this error rate checks unit and this frequency restoration unit; And
One display unit, this display unit is electrically connected to this processing unit.
2. eye pattern construction display unit as claimed in claim 1, it is characterized in that, wherein this amplifier is a variable gain amplifier.
3. eye pattern construction display unit as claimed in claim 2, it is characterized in that, wherein this first equalizer is a feed forward equalizer.
4. eye pattern construction display unit as claimed in claim 3, is characterized in that, wherein this second equalizer is that equalizer is feedback in a decision-making.
5. eye pattern construction display unit as claimed in claim 4, it is characterized in that, wherein this adder unit is an adder.
6. eye pattern construction display unit as claimed in claim 5, it is characterized in that, wherein this error rate checks unit is an error rate collating circuit.
7. eye pattern construction display unit as claimed in claim 6, it is characterized in that, wherein this frequency restoration unit is a frequency restoration circuit.
8. eye pattern construction display unit as claimed in claim 7, it is characterized in that, wherein this display unit is a display.
9. eye pattern construction display unit as claimed in claim 8, it is characterized in that, wherein this processing unit is a microprocessor.
10. eye pattern construction display unit as claimed in claim 8, it is characterized in that, wherein this processing unit is a microcontroller.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410442193.6A CN105375993B (en) | 2014-09-02 | 2014-09-02 | Eye pattern construction display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410442193.6A CN105375993B (en) | 2014-09-02 | 2014-09-02 | Eye pattern construction display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105375993A true CN105375993A (en) | 2016-03-02 |
| CN105375993B CN105375993B (en) | 2018-07-10 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410442193.6A Expired - Fee Related CN105375993B (en) | 2014-09-02 | 2014-09-02 | Eye pattern construction display device |
Country Status (1)
| Country | Link |
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| CN (1) | CN105375993B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6584163B1 (en) * | 1998-06-01 | 2003-06-24 | Agere Systems Inc. | Shared data and clock recovery for packetized data |
| CN1647425A (en) * | 2002-04-17 | 2005-07-27 | 汤姆森特许公司 | Equalizer/forward error correction automatic mode selector |
| US20090316772A1 (en) * | 2008-06-20 | 2009-12-24 | Fujitsu Limited | Multidimensional Asymmetric Bang-Bang Control |
| US8406285B1 (en) * | 2008-09-04 | 2013-03-26 | Marvell Israel (Misl) Ltd. | Tuning algorithm for feed forward equalizer in a serial data channel with decision feedback equalizer |
-
2014
- 2014-09-02 CN CN201410442193.6A patent/CN105375993B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6584163B1 (en) * | 1998-06-01 | 2003-06-24 | Agere Systems Inc. | Shared data and clock recovery for packetized data |
| CN1647425A (en) * | 2002-04-17 | 2005-07-27 | 汤姆森特许公司 | Equalizer/forward error correction automatic mode selector |
| US20090316772A1 (en) * | 2008-06-20 | 2009-12-24 | Fujitsu Limited | Multidimensional Asymmetric Bang-Bang Control |
| US8406285B1 (en) * | 2008-09-04 | 2013-03-26 | Marvell Israel (Misl) Ltd. | Tuning algorithm for feed forward equalizer in a serial data channel with decision feedback equalizer |
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| Publication number | Publication date |
|---|---|
| CN105375993B (en) | 2018-07-10 |
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| CF01 | Termination of patent right due to non-payment of annual fee |