CN105374821A - Memory chip package module - Google Patents
Memory chip package module Download PDFInfo
- Publication number
- CN105374821A CN105374821A CN201410477541.3A CN201410477541A CN105374821A CN 105374821 A CN105374821 A CN 105374821A CN 201410477541 A CN201410477541 A CN 201410477541A CN 105374821 A CN105374821 A CN 105374821A
- Authority
- CN
- China
- Prior art keywords
- memory chip
- memory
- chip
- those
- active surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000084 colloidal system Substances 0.000 claims abstract description 23
- 238000012856 packing Methods 0.000 claims description 22
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000004806 packaging method and process Methods 0.000 abstract 2
- 239000008393 encapsulating agent Substances 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 13
- 239000000463 material Substances 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000012447 hatching Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
- H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
- H01L2924/15156—Side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Semiconductor Memories (AREA)
- Dram (AREA)
Abstract
The invention discloses a memory chip packaging module which comprises a circuit substrate, a plurality of first memory chips and a first packaging colloid. The circuit substrate is provided with a first surface, a second surface opposite to the first surface, a plurality of first grooves positioned on the first surface and a plurality of first contacts positioned in the first grooves. The first memory chips are respectively positioned in the first grooves, wherein each first memory chip is electrically connected to the corresponding first contact through at least one first bonding wire. The first encapsulant is filled in the first grooves and at least covers the first memory chips and the parts electrically connected with the first contacts.
Description
Technical field
The present invention relates to a kind of module encapsulation construction, and particularly relate to a kind of memory package structure.
Background technology
With regard to dynamic random access memory (DynamicRandomAccessMemory, DRAM) chip, because the pin count needed for it is few, and internal wiring is simple, therefore its weld pad can be designed to central distribution type (centraltype), with the wiring of common sparing.Specifically, dynamic random access memory chip can engage the mode such as (wirebonding) or flip-chip bonded (flipchipbonding) and be electrically connected to carrier (carrier) via routing, such as lead frame (leadframe) or substrate (substrate) etc.
Engage the dynamic random access memory chip encapsulating structure of kenel for existing routing, dynamic random access memory chip first can be pasted to carrier, then is electrically connected to carrier in the mode that routing engages.Afterwards, with the part that packing colloid (moldingcompound) coated dynamic random access memory chip and dynamic random access memory chip are electrically connected with carrier, the part for preventing dynamic random access memory chip and dynamic random access memory chip to be electrically connected with carrier is subject to the impact of extraneous aqueous vapor and the pollution of assorted dirt.So far, dynamic random access memory chip encapsulating structure roughly completes, wherein dynamic random access memory chip encapsulating structure is by surface mount technology (SurfaceMountTechnology, SMT) fix on a printed circuit, with obtained existing dynamic randon access chip encapsulation module.
Due to before the existing dynamic randon access chip encapsulation module of making, need the making first carrying out individually dynamic random access memory chip encapsulating structure, wherein dynamic random access memory chip need be pasted to carrier, to be electrically connected to printed circuit board (PCB) by carrier, the integral thickness of dynamic randon access chip encapsulation module, manufacturing cost and manufacturing man-hours therefore effectively cannot be reduced.
Summary of the invention
The object of the present invention is to provide a kind of memory chip package module, it reduces manufacturing cost and manufacturing man-hours because of the simplification of manufacture craft, and can meet the demand of slimming.
For reaching above-mentioned purpose, the present invention proposes a kind of memory chip package module, and it comprises circuit base plate, multiple first memory chip and the first packing colloid.Circuit base plate have first surface, relative to first surface second surface, be positioned at multiple first groove on first surface and be positioned at multiple first contacts of these the first grooves.These first memory chips lay respectively in these first grooves, and wherein each first memory chip is electrically connected to the first corresponding contact by least one first bonding wire.First packing colloid is filled in these first grooves, and the part that these first memory chips at least coated are electrically connected with these first contacts.
In one embodiment of this invention, each above-mentioned first memory chip has active surface, relative to the chip back of active surface and the chip side surface of connection active surface and chip back.
In one embodiment of this invention, each above-mentioned first memory chip is connected to circuit base plate with chip back, and makes active surface be exposed to first surface, and first surface is higher than the active surface of each first memory chip.
In one embodiment of this invention, the active surface of the first above-mentioned packing colloid these first bonding wires coated, these first contacts and each first memory chip and chip side surface.
In one embodiment of this invention, plural first memory chip is mutually stacking to form first memory chipset, and be connected to circuit base plate with the chip back of the wherein one of these first memory chips, and make the active surface of each first memory chip be exposed to first surface, and first surface is higher than the active surface of each first memory chip.
In one embodiment of this invention, the first above-mentioned groove is through to second surface from first surface.
In one embodiment of this invention, above-mentioned first memory chip is connected to circuit base plate with active surface, and makes chip back be exposed to first surface or second surface.
In one embodiment of this invention, above-mentioned first surface is higher than the chip back of each first memory chip.
In one embodiment of this invention, above-mentioned second surface is higher than the chip back of each first memory chip.
In one embodiment of this invention, above-mentioned memory chip package module also comprises multiple second memory chip and the second packing colloid.Circuit base plate also has multiple second groove be positioned on second surface and multiple second contacts being positioned at these the second grooves.These second memory chips lay respectively in these second grooves, and are electrically connected to the second corresponding contact by least one second bonding wire.Second packing colloid is filled in these second grooves, and the part that these second memory chips at least coated are electrically connected with these second contacts.
In one embodiment of this invention, each above-mentioned second memory chip has active surface, relative to the chip back of active surface and the chip side surface of connection active surface and chip back.
In one embodiment of this invention, each above-mentioned second memory chip is connected to circuit base plate with chip back, and makes active surface be exposed to second surface, and second surface is higher than the active surface of each second memory chip.
In one embodiment of this invention, the active surface of the second above-mentioned packing colloid these second bonding wires coated, these second contacts and each second memory chip and chip side surface.
In one embodiment of this invention, plural second memory chip is mutually stacking to form second memory chipset, and be connected to this circuit base plate with the chip back of the wherein one of these second memory chips, and make the active surface of each second memory chip be exposed to second surface, and second surface is higher than the active surface of each second memory chip.
In one embodiment of this invention, the first above-mentioned groove position is on the first surface right against the second groove position on a second surface respectively.
Based on above-mentioned, because memory chip package module of the present invention is embedded in circuit base plate by memory chip, and the mode utilizing bonding wire to engage with routing is directly electrically connected memory chip and circuit base plate, therefore when without the need to additionally arranging carrier using as the medium be electrically connected between memory chip with circuit base plate, not only effectively can reduce the integral thickness of memory chip package module, also can significantly save manufacturing cost and manufacturing man-hours.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and the accompanying drawing appended by coordinating is described in detail below.
Accompanying drawing explanation
Figure 1A is the local schematic top plan view of the memory chip package module of one embodiment of the invention;
Figure 1B is the partial cutaway schematic of memory chip package module along I-I hatching line of Figure 1A;
Fig. 2 is the partial cutaway schematic of the memory chip package module of another embodiment of the present invention;
Fig. 3 is the partial cutaway schematic of the memory chip package module of another embodiment of the present invention;
Fig. 4 is the partial cutaway schematic of the memory chip package module of another embodiment of the present invention;
Fig. 5 is the partial cutaway schematic of the memory chip package module of another embodiment of the present invention;
Fig. 6 is the partial cutaway schematic of the memory chip package module of another embodiment of the present invention;
Fig. 7 is the partial cutaway schematic of the memory chip package module of another embodiment of the present invention;
Fig. 8 is the partial cutaway schematic of the memory chip package module of another embodiment of the present invention.
Symbol description
12: first memory chipset
16: second memory chipset
100,100A ~ 100G: memory chip package module
110,110b, 110c, 110e, 110f, 110g: circuit base plate
111: first surface
112: second surface
113, the 113e, 113f, 113g: first groove
114: the first contacts
115: the second grooves
116: the second contacts
120: first memory chip
121,161: weld pad
122,162: active surface
123,163: chip back
124,164: chip side surface
130: the first packing colloids
140: the first bonding wires
160: second memory chip
170: the second packing colloids
180: the second bonding wires
Embodiment
Figure 1A is the local schematic top plan view of the memory chip package module of one embodiment of the invention.Figure 1B is the partial cutaway schematic of memory chip package module along I-I hatching line of Figure 1A.Please refer to Figure 1A and Figure 1B, in the present embodiment, memory chip package module 100 is such as dynamic random access memory chip package module, and it comprises circuit base plate 110, multiple first memory chip 120 and the first packing colloid 130.Typically, circuit base plate 110 is such as printed circuit board (PCB) (printedcircuitboard, PCB), it has first surface 111, the second surface 112 relative to first surface 111, multiple first contacts 114 of being positioned at multiple first groove 113 on first surface 111 and being positioned at these the first grooves 113.
First groove 113 can be to be formed on circuit base plate 110 by modes such as any processing, and the material of the first contact 114 is such as gold, copper, nickel or other metal materials, and be electrically connected with the patterned line layer (not shown) of circuit base plate 110.Herein, the weld pad 121 of first memory chip 120 is such as central distribution type, and in other embodiments, and the weld pad 121 of first memory chip 120 also can be around profile (peripheraltype), and the present invention is not limited this.Specifically, each first memory chip 120 is positioned at the first corresponding groove 113, and is electrically connected to the first corresponding contact 114 by the mode that at least one first bonding wire 140 (Figure 1B illustrates two the first bonding wires 140 with signal) engages with routing.It should be noted that, because each first memory chip 120 is first contacts 114 be electrically connected in first groove 113 at its place, therefore the first bonding wire 140 can't cross over the top in first surface 111.
Each first memory chip 120 has active surface 122, relative to the chip back 123 of active surface 122 and the chip side surface 124 of connection active surface 122 and chip back 123, wherein weld pad 121 is positioned on the active surface 122 of each first memory chip 120.Herein, each first memory chip 120 is connected to circuit base plate 110 with its chip back 123, such as be pasted to the bottom of the first corresponding groove 113, make active surface 122 be exposed to first surface 111 towards the opening of the first groove 113, and first surface 111 is higher than the active surface 122 of each first memory chip 120.
On the other hand, the first packing colloid 130 is filled in these first grooves 113, and the part that these first memory chips 120 at least coated are electrically connected with these first contacts 114.More particularly, active surface 122 and the chip side surface 124 of the first packing colloid 130 these first bonding wires 140 coated, these first contacts 114 and each first memory chip 120, part for preventing first memory chip 120 and first memory chip 120 to be electrically connected with the first contact 114 is subject to the impact of extraneous aqueous vapor and the pollution of assorted dirt, thus improves its useful life and reliability.In general, the material of the first packing colloid 130 can be epoxy resin or other suitable macromolecular materials.
In brief, due to each first memory chip 120 can in be embedded in circuit base plate 110, and utilize the first bonding wire 140 to be directly electrically connected first memory chip 120 and circuit base plate 110 in the mode that routing engages, therefore when without the need to additionally arranging carrier using as the medium be electrically connected between first memory chip 120 with circuit base plate 110, not only effectively can reduce the integral thickness of memory chip package module 100, also can significantly save manufacturing cost and manufacturing man-hours.
Below will enumerate other embodiments using as explanation.Should be noted that at this, following embodiment continues to use element numbers and the partial content of previous embodiment, wherein adopts identical label to represent identical or approximate element, and eliminates the explanation of constructed content.Explanation about clipped can with reference to previous embodiment, and it is no longer repeated for following embodiment.
Fig. 2 is the partial cutaway schematic of the memory chip package module of another embodiment of the present invention.Please refer to Fig. 2, memory chip package module 100A is roughly similar to memory chip package module 100, but the two Main Differences part is: in the present embodiment, can be provided with at least two first memory chips 120 (Fig. 2 illustrates two first memory chips 120 with signal) in any one first groove 113, the first memory chip 120 being wherein positioned at same first groove 113 can be mutually stacking to form first memory chipset 12.
Typically, the first memory chip 120 being in top in first memory chipset 12 is such as the active surface 122 connecting in first memory chipset 12 the first memory chip 120 being in below with its chip back 123, and the chip back 123 being in the first memory chip 120 of top is completely not overlapping with the active surface 122 of the first memory chip 120 being in below, to expose part and the weld pad 121 of the active surface 122 of the first memory chip 120 being in below.On the other hand, first memory chipset 12 is that the chip back 123 of first memory chip 120 being in below is connected to circuit base plate 110, and make the active surface 122 of each first memory chip 120 be exposed to first surface 111, and first surface 111 is higher than the active surface 122 of each first memory chip 120.
Fig. 3 is the partial cutaway schematic of the memory chip package module of another embodiment of the present invention.Please refer to Fig. 3, memory chip package module 100B is roughly similar to memory chip package module 100, but the two Main Differences part is: in the present embodiment, memory chip package module 100B also comprises multiple second memory chip 160 and the second packing colloid 170, and wherein circuit base plate 110b also has multiple second groove 115 be positioned on second surface 112 and multiple second contacts 116 being positioned at these the second grooves 115.Second groove 115 can be to be formed on circuit base plate 110b by the mode such as laser processing or machining, and the material of the second contact 116 is such as gold, copper, nickel or other metal materials, and be electrically connected with the patterned line layer (not shown) of circuit base plate 110b.
Herein, the weld pad 161 of second memory chip 160 is such as central distribution type, and in other embodiments, and the weld pad 161 of second memory chip 160 also can be around profile (peripheraltype), and the present invention is not limited this.Specifically, each second memory chip 160 is positioned at the second corresponding groove 115, and is electrically connected to the second corresponding contact 116 by the mode that at least one second bonding wire 180 (Fig. 3 illustrates two the second bonding wires 180 with signal) engages with routing.It should be noted that, because each second memory chip 160 is second contacts 116 be electrically connected in second groove 115 at its place, therefore the second bonding wire 180 can't cross over the top in second surface 112.
Each second memory chip 160 has active surface 162, relative to the chip back 163 of active surface 162 and the chip side surface 164 of connection active surface 162 and chip back 163, wherein weld pad 161 is positioned on the active surface 162 of each second memory chip 160.Herein, each second memory chip 160 is connected to circuit base plate 110b with its chip back 163, such as be pasted to the bottom of the second corresponding groove 115, make active surface 162 be exposed to second surface 112 towards the opening of the second groove 115, and second surface 112 is higher than the active surface 162 of each second memory chip 160.
On the other hand, the second packing colloid 170 is filled in these second grooves 115, and the part that these second memory chips 160 at least coated are electrically connected with these second contacts 116.More particularly, active surface 162 and the chip side surface 164 of the second packing colloid 170 these second bonding wires 180 coated, these second contacts 116 and each second memory chip 160, part for preventing second memory chip 160 and second memory chip 160 to be electrically connected with the second contact 116 is subject to the impact of extraneous aqueous vapor and the pollution of assorted dirt, thus improves its useful life and reliability.In general, the material of the second packing colloid 170 can be epoxy resin or other suitable macromolecular materials.
In brief, due to each first memory chip 120 and each second memory chip 160 can in be embedded in circuit base plate 110b, and utilize the first bonding wire 140 and the second bonding wire 180 to be directly electrically connected first memory chip 120 and circuit base plate 110b and second memory chip 160 and circuit base plate 110b in the mode that routing engages respectively, therefore when without the need to additionally arrange carrier using as the medium be electrically connected between first memory chip 120 with circuit base plate 110b and be electrically connected between second memory chip 160 with circuit base plate 110b medium, not only effectively can reduce the integral thickness of memory chip package module 100B, also manufacturing cost and manufacturing man-hours can significantly be saved.
On the other hand, although the circuit base plate 110b of the present embodiment is right against the second position of groove 115 on second surface 112 with the first position of groove 113 on first surface 111 to explain respectively, but in other embodiments, first groove 113 and the second groove 115 also can be staggered on circuit base plate 110b, and the present invention is not limited this.
Fig. 4 is the partial cutaway schematic of the memory chip package module of another embodiment of the present invention.Please refer to Fig. 4, memory chip package module 100C is roughly similar to memory chip package module 100B, but the two Main Differences part is: in the present embodiment, can be provided with at least two second memory chips 160 (Fig. 4 illustrates two second memory chips 160 with signal) in any one second groove 115, the second memory chip 160 being wherein positioned at same second groove 115 can be mutually stacking to form second memory chipset 16.
Typically, the second memory chip 160 being in top in second memory chipset 16 is such as the active surface 162 connecting in second memory chipset 16 the second memory chip 160 being in below with its chip back 163, and the chip back 163 being in the second memory chip 160 of top is completely not overlapping with the active surface 162 of the second memory chip 160 being in below, to expose part and the weld pad 161 of the active surface 162 of the second memory chip 160 being in below.On the other hand, second memory chipset 16 is that the chip back 163 of second memory chip 160 being in below is connected to circuit base plate 110c, and make the active surface 162 of each second memory chip 160 be exposed to second surface 112, and second surface 112 is higher than the active surface 162 of each second memory chip 160.
Fig. 5 is the partial cutaway schematic of the memory chip package module of another embodiment of the present invention.Please refer to Fig. 5, memory chip package module 100A and memory chip package module 100C is integrated by memory chip package module 100D, that is be all provided with first memory chipset 12 in each first groove 113, and be all provided with second memory chipset 16 in each second groove 115.In the embodiment do not illustrated, also optionally in the first groove 113 of part and in the second groove 115 of part, first memory chipset 12 and second memory chipset 16 is respectively arranged with, and in other the first groove 113 and other the second groove 115 be respectively arranged with single first memory chip 120 and single second memory chip 160, look closely actual design demand and adjust to some extent.
Fig. 6 is the partial cutaway schematic of the memory chip package module of another embodiment of the present invention.Please refer to Fig. 6, memory chip package module 100E is roughly similar to memory chip package module 100, but the two Main Differences part is: in the present embodiment, first groove 113e is through to second surface 112 from first surface 111, wherein each first memory chip 120 is connected to circuit base plate 110e with active surface 122, and make chip back 123 be exposed to second surface 112, and second surface 112 is higher than the chip back 123 of each first memory chip 120.
Fig. 7 is the partial cutaway schematic of the memory chip package module of another embodiment of the present invention.Please refer to Fig. 7, memory chip package module 100F is roughly similar to memory chip package module 100E, but the two Main Differences part is: in the present embodiment, each first memory chip 120 being positioned at the first groove 113f is connected to circuit base plate 110f with active surface 122, and make chip back 123 be exposed to first surface 111, and first surface 111 is higher than the chip back 123 of each first memory chip 120.
Fig. 8 is the partial cutaway schematic of the memory chip package module of another embodiment of the present invention.Please refer to Fig. 8, memory chip package module 100E and memory chip package module 100F is integrated by memory chip package module 100G, also be arranged in the first corresponding groove 113g by first memory chip 120, and being connected to circuit base plate 110g with active surface 122, the chip back 123 making the chip back 123 of the first memory chip 120 of part be exposed to first surface 111 and other first memory chip 120 is exposed to second surface 112.
In sum, because memory chip package module of the present invention is embedded in circuit base plate by memory chip, and the mode utilizing bonding wire to engage with routing is directly electrically connected memory chip and circuit base plate, therefore when without the need to additionally arranging carrier using as the medium be electrically connected between memory chip with circuit base plate, not only effectively can reduce the integral thickness of memory chip package module, also can significantly save manufacturing cost and manufacturing man-hours.
Although disclose the present invention in conjunction with above embodiment; but itself and be not used to limit the present invention; have in any art and usually know the knowledgeable; without departing from the spirit and scope of the present invention; a little change and retouching can be done, therefore being as the criterion of should defining with the claim of enclosing of protection scope of the present invention.
Claims (17)
1. a memory chip package module, comprising:
Circuit base plate, have first surface, relative to this first surface second surface, be positioned at multiple first groove on this first surface and be positioned at multiple first contacts of those the first grooves;
Multiple first memory chip, lays respectively in those first grooves, and wherein respectively this first memory chip is electrically connected to this corresponding first contact by least one first bonding wire; And
First packing colloid, is filled in those first grooves, and the part that those first memory chips at least coated are electrically connected with those first contacts.
2. memory chip package module as claimed in claim 1, wherein respectively this first memory chip have active surface, relative to this active surface a chip back and to connect this active surface surperficial with a chip side of this chip back.
3. memory chip package module as claimed in claim 2, wherein respectively this first memory chip is connected to this circuit base plate with this chip back, and make this active surface be exposed to this first surface, and this first surface is higher than this active surface of each this first memory chip.
4. memory chip package module as claimed in claim 3, wherein this active surface of this first packing colloid those first bonding wires coated, those first contacts and each this first memory chip is surperficial with this chip side.
5. memory chip package module according to claim 2, wherein those first memory chips plural are mutually stacking to form a first memory chipset, and be connected to this circuit base plate with this chip back of the wherein one of those first memory chips, and make the active surface of respectively this first memory chip be exposed to this first surface, and this first surface is higher than this active surface of each this first memory chip.
6. memory chip package module as claimed in claim 1, wherein those first grooves are through to this second surface from this first surface.
7. memory chip package module as claimed in claim 1, wherein respectively this first memory chip have active surface, relative to this active surface a chip back and to connect this active surface surperficial with a chip side of this chip back.
8. memory chip package module as claimed in claim 7, wherein respectively this first memory chip is connected to this circuit base plate with this active surface, and makes this chip back be exposed to this first surface or this second surface.
9. memory chip package module as claimed in claim 8, wherein this first surface is higher than this chip back of each this first memory chip.
10. memory chip package module as claimed in claim 8, wherein this second surface is higher than this chip back of each this first memory chip.
11. memory chip package modules as claimed in claim 8, wherein this first packing colloid those first bonding wires coated, those first contacts and respectively this active surface of this first memory chip and this chip side surface.
12. memory chip package modules as claimed in claim 1, also comprise:
Multiple second memory chip, wherein this circuit base plate also has multiple second groove be positioned on second surface and multiple second contacts being positioned at those the second grooves, those second memory chips lay respectively in those second grooves, and are electrically connected to this corresponding second contact by least one second bonding wire; And
Second packing colloid, is filled in those second grooves, and the part that those second memory chips at least coated are electrically connected with those second contacts.
13. memory chip package modules as claimed in claim 12, wherein respectively this second memory chip have an active surface, relative to this active surface a chip back and connect a chip side surface of this active surface and this chip back.
14. memory chip package modules as claimed in claim 13, wherein respectively this second memory chip is connected to this circuit base plate with this chip back, and make this active surface be exposed to this second surface, and this second surface is higher than this active surface of each this second memory chip.
15. memory chip package modules as claimed in claim 14, wherein this second packing colloid those second bonding wires coated, those second contacts and respectively this active surface of this second memory chip and this chip side surface.
16. memory chip package modules as claimed in claim 13, wherein those second memory chips plural are mutually stacking to form a second memory chipset, and be connected to this circuit base plate with this chip back of the wherein one of those second memory chips, and make this active surface of respectively this second memory chip be exposed to this second surface, and this second surface is higher than this active surface of each this second memory chip.
17. memory chip package modules as claimed in claim 13, wherein those the first groove positions are on the first surface right against those the second groove positions on the second surface respectively.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103129678 | 2014-08-28 | ||
| TW103129678A TW201608696A (en) | 2014-08-28 | 2014-08-28 | Memory chip package module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105374821A true CN105374821A (en) | 2016-03-02 |
Family
ID=55376854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410477541.3A Pending CN105374821A (en) | 2014-08-28 | 2014-09-18 | Memory chip package module |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN105374821A (en) |
| TW (1) | TW201608696A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09107067A (en) * | 1995-10-09 | 1997-04-22 | Hitachi Ltd | Semiconductor device |
| TW200721400A (en) * | 2005-09-29 | 2007-06-01 | United Test & Assembly Ct Lt | Cavity chip package |
| US20070225852A1 (en) * | 2006-03-23 | 2007-09-27 | Hong Tan K | Method of Packaging Integrated Circuit Devices Using Preformed Carrier |
| TW200818435A (en) * | 2006-08-28 | 2008-04-16 | Micron Technology Inc | Metal core foldover package structures, systems including same and methods of fabrication |
| CN101872757A (en) * | 2009-04-24 | 2010-10-27 | 南茂科技股份有限公司 | Recess chip packaging structure and laminated packaging structure using same |
-
2014
- 2014-08-28 TW TW103129678A patent/TW201608696A/en unknown
- 2014-09-18 CN CN201410477541.3A patent/CN105374821A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09107067A (en) * | 1995-10-09 | 1997-04-22 | Hitachi Ltd | Semiconductor device |
| TW200721400A (en) * | 2005-09-29 | 2007-06-01 | United Test & Assembly Ct Lt | Cavity chip package |
| US20070225852A1 (en) * | 2006-03-23 | 2007-09-27 | Hong Tan K | Method of Packaging Integrated Circuit Devices Using Preformed Carrier |
| TW200818435A (en) * | 2006-08-28 | 2008-04-16 | Micron Technology Inc | Metal core foldover package structures, systems including same and methods of fabrication |
| CN101872757A (en) * | 2009-04-24 | 2010-10-27 | 南茂科技股份有限公司 | Recess chip packaging structure and laminated packaging structure using same |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201608696A (en) | 2016-03-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10032747B2 (en) | Light emitting diode package structure and manufacturing method thereof | |
| US7732908B2 (en) | Semiconductor device and semiconductor memory device | |
| US7205651B2 (en) | Thermally enhanced stacked die package and fabrication method | |
| CN106601692B (en) | Semiconductor package, method of manufacturing the same, and semiconductor module | |
| US9543279B2 (en) | Method of manufacturing a single light-emitting structure | |
| US8994170B2 (en) | Microelectronic unit and package with positional reversal | |
| CN102315135A (en) | Chip package and manufacturing process thereof | |
| US9466592B2 (en) | Multi-chips in system level and wafer level package structure | |
| US10269718B2 (en) | Rectangular semiconductor package and a method of manufacturing the same | |
| KR20110055985A (en) | Stack package | |
| US9318354B2 (en) | Semiconductor package and fabrication method thereof | |
| CN105374821A (en) | Memory chip package module | |
| CN104008982A (en) | Chip packaging process and chip package | |
| CN103904552A (en) | Laser chip packaging structure for projection | |
| US20070267756A1 (en) | Integrated circuit package and multi-layer lead frame utilized | |
| US10153221B1 (en) | Face down dual sided chip scale memory package | |
| US11876067B2 (en) | Semiconductor package and method of manufacturing the same | |
| US20150333238A1 (en) | Package structure and method of fabricating the same | |
| KR20100050981A (en) | Semiconductor package and stack package using the same | |
| US20220270997A1 (en) | Semiconductor package | |
| US7781898B2 (en) | IC package reducing wiring layers on substrate and its chip carrier | |
| KR20110030090A (en) | Semiconductor package and method for fabricating thereof | |
| KR20060128376A (en) | Chip stack package | |
| CN111293107A (en) | Semiconductor packaging structure | |
| KR20080101209A (en) | Stack semiconductor package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20160302 |