CN105373456B - Reduce the internal storage testing method of cache hit rate - Google Patents
Reduce the internal storage testing method of cache hit rate Download PDFInfo
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- CN105373456B CN105373456B CN201510808418.XA CN201510808418A CN105373456B CN 105373456 B CN105373456 B CN 105373456B CN 201510808418 A CN201510808418 A CN 201510808418A CN 105373456 B CN105373456 B CN 105373456B
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Abstract
The present invention provides a kind of internal storage testing method for reducing cache hit rate, including：Memory to be measured is divided into the memory sections of several default sizes；It is several testing procedures by preset memory test algorithm partition；Several testing procedures are performed successively to several memory sections；Wherein, between each memory sections execution any two continuously testing procedure, a testing procedure at least is performed to another memory sections.The present invention to different memory sections by performing testing procedure successively, and realizing caching can not continue to form effective concern section so that buffer status is being shaken always, reduces cache hit rate, so as to improve the validity of memory test；And further by monitoring and counting execution time and the cache hit of the memory test algorithm performs process, it is divided according to the testing procedure of statistical result memory optimization testing algorithm, so as to take into account the efficiency and validity that consider memory test, optimize the internal storage testing method.
Description
Technical field
The present invention relates to memory test technical field more particularly to a kind of internal storage testing methods for reducing cache hit rate.
Background technology
The validity of memory test is always to weigh a very important standard of test quality, for integration testing rank
It is even more so for the diag programs of section.Processor now is all with multi-level buffer (cache), and every level cache is big
Small all to increase with advances in technology and gradually, intel processors high-end at present are all divided into 3 grades of cachings, and third substantially
Grade cache size has reached 4M or even bigger.Therefore in the test of memory how effectively and ensure to greatest extent each time
The problem of read-write operation really operates memory rather than falls into multi-level buffer, this is one critically important.At present on the market
Diag programs are not made effective optimization for this problem and are targetedly handled, therefore the validity tested can be by
Certain influence.
Invention content
The brief overview about the present invention is given below, in order to provide the basic reason about certain aspects of the invention
Solution.It should be appreciated that this general introduction is not the exhaustive general introduction about the present invention.It is not intended to determine the key of the present invention
Or pith, nor is it intended to limit the scope of the present invention.Its purpose only provides certain concepts in simplified form, with
This is as the preamble in greater detail discussed later.
The present invention provides a kind of internal storage testing method for reducing cache hit rate, ensures to read and write behaviour each time to greatest extent
It does exercises and accomplishes memory rather than multi-level buffer, so as to improve the validity of memory test.
The present invention provides a kind of internal storage testing method for reducing cache hit rate, including：
Memory to be measured is divided into the memory sections of several default sizes；
It is several testing procedures by preset memory test algorithm partition；
Several testing procedures are performed successively to several memory sections；
Wherein, between each memory sections execution any two continuously testing procedure, at least to another
The memory sections perform a testing procedure.
The internal storage testing method that many embodiments of the present invention provide to different memory sections by performing test step successively
Suddenly, realizing caching can not continue to form effective concern section so that buffer status is being shaken always, reduces cache hit
Rate, so as to improve the validity of memory test；
Some embodiments of the invention provide internal storage testing method by performing each step successively to all memory sections,
The sequence of fixed testing procedure maintains the efficiency of test while keeping reducing cache hit rate；
The internal storage testing method that some embodiments of the invention provide is by monitoring and counting the memory test algorithm performs
The execution time of process and cache hit are divided according to the testing procedure of statistical result memory optimization testing algorithm, so as to take into account
Consider the efficiency and validity of memory test, advanced optimize the internal storage testing method.
Description of the drawings
Below with reference to the accompanying drawings illustrate embodiments of the invention, the above of the present invention and its can be more readily understood that
Its objects, features and advantages.Component in attached drawing is intended merely to show the principle of the present invention.In the accompanying drawings, it is identical or similar
Technical characteristic or component will be represented using same or similar reference numeral.
Fig. 1 is the flow chart of the internal storage testing method of reduction cache hit rate that one embodiment of the invention provides.
Fig. 2 is the flow chart of a preferred embodiment of internal storage testing method shown in Fig. 1.
Fig. 3 is the flow chart of another preferred embodiment of internal storage testing method shown in Fig. 1.
Specific embodiment
Illustrate the embodiment of the present invention with reference to the accompanying drawings.It is retouched in the attached drawing of the present invention or a kind of embodiment
The elements and features stated can be combined with the elements and features shown in one or more other attached drawings or embodiment.It should
When note that for purposes of clarity, being omitted known to unrelated to the invention, those of ordinary skill in the art in attached drawing and explanation
Component and processing expression and description.
Fig. 1 is the flow chart of the internal storage testing method of reduction cache hit rate that one embodiment of the invention provides.
As shown in Figure 1, in the present embodiment, the internal storage testing method packet provided by the present invention for reducing cache hit rate
It includes：
S10：Memory to be measured is divided into the memory sections of several default sizes；
S30：It is several testing procedures by preset memory test algorithm partition；
S50：Several testing procedures are performed successively to several memory sections；
Wherein, between each memory sections execution any two continuously testing procedure, at least to another
The memory sections perform a testing procedure.
Specifically, in the present embodiment, the default size of memory sections is 4M, by taking memory size 16M to be measured as an example, step
Memory to be measured is divided into memory sections 1, memory sections 2, memory sections 3 and memory sections 4 by S10；
Preset memory test algorithm partition is testing procedure a, testing procedure b and testing procedure c by step S30；
Step S50 performs testing procedure a-c successively to memory sections 1-4, and ensures to perform each memory sections arbitrary
Between two continuous testing procedures, at least another memory sections are performed with a testing procedure, such as：
Testing procedure a is performed to memory sections 1；
Testing procedure a is performed to memory sections 2；
Testing procedure a is performed to memory sections 3；
Testing procedure b is performed to memory sections 1；
Testing procedure b is performed to memory sections 2；
Testing procedure a is performed to memory sections 4；
Testing procedure c is performed to memory sections 1；
Testing procedure b is performed to memory sections 3；
Testing procedure b is performed to memory sections 4；
Testing procedure c is performed to memory sections 2；
Testing procedure c is performed to memory sections 3；
Testing procedure c is performed to memory sections 4；
Ensure that the next testing procedure of execution is different memory sections so that caching can not give more sustained attention same
Memory sections.
Therefore, in the present embodiment, internal storage testing method provided by the invention is by successively holding different memory sections
Row testing procedure, realizing caching can not continue to form effective concern section so that buffer status is being shaken always, reduces
Cache hit rate, so as to improve the validity of memory test.
Fig. 2 is the flow chart of a preferred embodiment of internal storage testing method shown in Fig. 1.
As shown in Fig. 2, in a preferred embodiment, in step s 50, when each memory sections have performed previous survey
After try is rapid, then latter testing procedure is performed to several memory sections.
Specifically, relative to a upper embodiment, in the present embodiment, processor has been performed both by test to memory sections 1-4
After step a, then testing procedure b is performed to memory sections 1-4 respectively, testing procedure c finally is performed to memory sections 1-4 respectively.
The present embodiment maintains the effect tested by the sequence of fixed testing procedure while keeping reducing cache hit rate
Rate.
In the application of actual memory test, apparent drop can be played using internal storage testing method provided in this embodiment
The effect of low cache hit rate：
Under the premise of using similary memory test algorithm, the cache hit rate of common memory test method is in 0.5-0.9
Between；And the cache hit rate of internal storage testing method provided in this embodiment is between 0.1-0.2.
Fig. 3 is the flow chart of another preferred embodiment of internal storage testing method shown in Fig. 1.
As shown in figure 3, in a preferred embodiment, internal storage testing method provided by the present invention is gone back after step S50
Including：
S70：Execution time and the cache hit of the memory test algorithm performs process are monitored and counted, is tied according to statistics
The testing procedure that fruit optimizes the memory test algorithm divides.
Specifically, in a certain range, what the testing procedure of memory test algorithm divided is thinner, and caching is more difficult to continue shape
Into effective concern section, cache hit rate is lower, and the validity of memory test is higher；But the meanwhile survey of memory test algorithm
Try divides thinner suddenly, then testing procedure is more, and the execution time is longer, and testing efficiency is lower.
Therefore internal storage testing method provided by the present invention can further find one by step S70 and take into account validity
With the equalization point of testing efficiency, internal storage testing method is advanced optimized.
In a preferred embodiment, the default size is used the three-level cache size of processor by test.
In a preferred embodiment, the processor is multi-core processor.
Specifically, usually there is the consistency problem of caching in multi-core processor, and the consistency problem of the caching is lucky
Can be that caching is difficult to continue to form effective concern section, buffer status is kept to shake always, reducing cache hit rate
Multi-ensuring is provided.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
The present invention is described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that：It still may be used
To modify to the technical solution recorded in foregoing embodiments or carry out equivalent replacement to which part technical characteristic；
And these modification or replace, various embodiments of the present invention technical solution that it does not separate the essence of the corresponding technical solution spirit and
Range.
Claims (3)
1. a kind of internal storage testing method for reducing cache hit rate, which is characterized in that including：
Memory to be measured is divided into the memory sections of several default sizes；
It is several testing procedures by preset memory test algorithm partition；
Several testing procedures are performed successively to several memory sections；
Wherein, between each memory sections execution any two continuously testing procedure, at least to another described
Memory sections perform a testing procedure；
The default size is used the three-level cache size of processor by test；
Described performed successively to several memory sections is further included after several testing procedures：
Execution time and the cache hit of the memory test algorithm performs process are monitored and counted, institute is optimized according to statistical result
The testing procedure for stating memory test algorithm divides.
2. internal storage testing method according to claim 1, which is characterized in that when each memory sections performed it is previous
After testing procedure, then latter testing procedure is performed to several memory sections.
3. internal storage testing method according to claim 1, which is characterized in that the processor is multi-core processor.
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| CN106970862B (en) * | 2017-04-11 | 2020-06-16 | 武汉斗鱼网络科技有限公司 | Memory jitter automatic test method and device |
| CN111739577B (en) * | 2020-07-20 | 2020-11-20 | 成都智明达电子股份有限公司 | DSP-based efficient DDR test method |
| CN113254321B (en) * | 2021-06-07 | 2023-01-24 | 上海恒为智能科技有限公司 | Method and system for evaluating memory access performance of processor |
| CN115576872B (en) * | 2022-11-18 | 2023-03-24 | 北京红山微电子技术有限公司 | Access detection method and device for multi-level cache |
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| US6240532B1 (en) * | 1998-04-06 | 2001-05-29 | Rise Technology Company | Programmable hit and write policy for cache memory test |
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| CN104123224A (en) * | 2014-07-09 | 2014-10-29 | 浪潮电子信息产业股份有限公司 | Simple memory test method based on IA-64 framework |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6442666B1 (en) * | 1999-01-28 | 2002-08-27 | Infineon Technologies Ag | Techniques for improving memory access in a virtual memory system |
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| US6240532B1 (en) * | 1998-04-06 | 2001-05-29 | Rise Technology Company | Programmable hit and write policy for cache memory test |
| CN101957781A (en) * | 2009-07-13 | 2011-01-26 | 英业达股份有限公司 | Remote aid memory testing method |
| CN103902448A (en) * | 2012-12-28 | 2014-07-02 | 中国科学院深圳先进技术研究院 | Multi-core processor soft error pressure test program generating system and method |
| CN104123224A (en) * | 2014-07-09 | 2014-10-29 | 浪潮电子信息产业股份有限公司 | Simple memory test method based on IA-64 framework |
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