CN105355606B - A kind of novel system grade encapsulation - Google Patents
A kind of novel system grade encapsulation Download PDFInfo
- Publication number
- CN105355606B CN105355606B CN201510633468.9A CN201510633468A CN105355606B CN 105355606 B CN105355606 B CN 105355606B CN 201510633468 A CN201510633468 A CN 201510633468A CN 105355606 B CN105355606 B CN 105355606B
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- substrate
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- mosfet chip
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Abstract
The embodiment of the invention discloses a kind of encapsulation of novel system grade.The encapsulation includes: substrate, high-end MOSFET chip, the first metal end, low side MOSFET chip, broken line type sheet metal, IC chip, at least one passive device.The present invention is by, in broken line type sheet metal two sides, realizing protection of the broken line type sheet metal to the electromagnetic interference of passive device for the passive device setting in encapsulated circuit.Meanwhile IC chip is disposed on the substrate by metal ball upside-down mounting, forms most short circuit, lowers resistance.Two MOSFET chips are disposed on the substrate using superposition mould process stacking, reduce the size of system encapsulation.
Description
Technical field
The present embodiments relate to semiconductor packagings more particularly to a kind of novel system grade to encapsulate.
Background technique
As shown in Figure 1, for by 2 N-type Metal Oxide Semiconductor Field Effect Transistor (Metal-Oxide-
Semiconductor Field-Effect Transistor, MOSFET) connection formed power switching device circuit diagram,
The drain D 1 of middle and high end (High Side, HS) MOSFET connects the end voltage input (Vin), and source S 1 connects low side (Low
Side, LS) MOSFET drain D 2, and the source S 2 of low side MOSFET then connect ground wire (Gnd) end.In general, being cut in the power
A bypass circuit capacitor C is also arranged in parallel between the both ends Vin-Gnd of parallel operation, the setting of the capacitor is for suppressing power
The impulse of voltage when switch starts, to promote the performance of the power switching device.Further, as shown in Fig. 2, high-end
The both ends of the grid G 2 of the grid G 1 and low side MOSFET of MOSFET are connected in parallel a power controller (Power Integrated
Circuit, PIC), then form a DC-DC (DC-DC) converter.
In current semiconductor packaging, DC-DC converter encapsulating structure constantly by each component integration packaging,
So that the semiconductor packages moves towards micromation.Therefore, the density of component is also continuously increased therewith on semiconductor, to make
Electromagnetic interference increases between obtaining component, and system radiating is badly in need of improving.
Summary of the invention
The embodiment of the present invention provides a kind of novel system grade encapsulation, to realize shielding electromagnetic interference, while improving system and dissipating
The thermal efficiency.
The embodiment of the invention provides a kind of encapsulation of novel system grade, which includes:
Substrate, for carrying the component in encapsulating structure；
MOSFET chip, in substrate surface, the high-end drain electrode in bottom is electrical by substrate wiring and Input voltage terminal for setting
Connection；
The first metal end, one end of the first metal end are connected with substrate circuit, and the other end is arranged high-end
MOSFET chip surface, for connecting the high-end source electrode of high-end MOSFET chip；
Low side MOSFET chip is set to the first metal end sublist face, and the bottom of low side MOSFET chip is low side drain electrode,
The low side drain electrode is contacted by the high-end source electrode at the top of the first metal end and high-end MOSFET chip；
Broken line type sheet metal, the horizontal end of the broken line type sheet metal include the second metal terminal, and the second metal terminal connects
Low side source electrode at the top of low side MOSFET chip is connect, end is erected and is electrically connected with substrate ground terminal；
IC chip is set to substrate surface, by substrate circuit respectively with high-end MOSFET chip and low side MOSFET core
The grid of piece is connected, and is used for power control；
At least one passive device, for broken line type sheet metal two sides substrate circuit to be arranged according to the corresponding demand of circuit
Corresponding position constitutes complete DC-DC power switching circuitry.
Further, the broken line type sheet metal is T-type sheet metal.
Further, the horizontal end of T-type sheet metal covers the surface in the direction containing component of entire encapsulating structure.
Further, the broken line type sheet metal is L-type sheet metal.
Further, the encapsulation further include: rectangular metal plate covers the top of inductance component in circuit.
Further, the IC chip is connect using lead key closing process with substrate circuit.
Further, the IC chip is connect using controlled collapsible chip connec-tion with substrate circuit.
Further, the IC chip is connect with substrate circuit by metal ball.
Further, the MOSFET chip is disposed on the substrate using superposition mould process.
The present invention is by, in broken line type sheet metal two sides, realizing broken line type metal for the passive device setting in encapsulated circuit
Protection of the piece to the electromagnetic interference of passive device.Meanwhile IC chip is disposed on the substrate by metal ball upside-down mounting, forms most short electricity
Resistance is lowered on road.Two MOSFET chips are disposed on the substrate using superposition mould process stacking, reduce system encapsulation
Size.
Detailed description of the invention
Fig. 1 is the circuit diagram of power switching device in the prior art；
Fig. 2 is the circuit diagram of the DC-DC converter in the embodiment of the present invention；
Fig. 3 A is the top view of one of embodiment of the present invention one novel system encapsulating structure；Fig. 3 B is along in Fig. 3 A
The direction A-A encapsulating structure planing surface figure；Fig. 3 C is the encapsulating structure planing surface figure along the direction B-B in Fig. 3 A；
Fig. 4 A is the top view of one of embodiment of the present invention two novel system encapsulating structure；Fig. 4 B is along in Fig. 4 A
The direction A-A encapsulating structure planing surface figure；Fig. 4 C is the encapsulating structure planing surface figure along the direction B-B in Fig. 4 A.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limiting the invention.It also should be noted that in order to just
Only the parts related to the present invention are shown in description, attached drawing rather than entire infrastructure.
Embodiment one
Fig. 3 A is the top view of one of embodiment of the present invention one novel system encapsulating structure, the system in the present embodiment
Encapsulation is applicable to DC-DC converter, and system encapsulation includes: substrate 1, high-end MOSFET chip 2, the first metal end 3, low
Hold MOSFET chip 6, broken line type sheet metal 7, IC chip 10 and at least one passive device 8.
Wherein, substrate 1 is with the substrate for being printed with circuit, which can be printed wiring board, be also possible to one
It is covered with the substrate of lead frame.
High-end MOSFET chip 2, on substrate 1, the high-end drain electrode in bottom is routed by substrate and Input voltage terminal for setting
It is electrically connected.There are many connection types of the high-end MOSFET chip 2 and substrate 1, can be through plain conductor 4 and substrate 1
Connection can also be fixed and be electrically connected by conducting resinl 5.The connection type of component and substrate circuit, excellent in the present embodiment
Choosing is when wanted connecting component is located at substrate 1 when the top of connecting pin, and selection conducting resinl 5 connects；Otherwise, plain conductor is selected
4 connections.
The first metal end 3, setting are showed in high-end MOSFET chip 2, and one end is connected with substrate circuit, other end setting
On high-end 2 surface of MOSFET chip, for connecting the high-end source electrode of high-end MOSFET chip 2.The first metal end 3 can be
Arbitrary shape, preferably L-type, wherein the shorter one end of L-type the first metal end can be connected by conducting resinl 5 and substrate circuit
It connects, longer one end can be electrically connected by conducting resinl 5 and high-end MOSFET chip 2.
The setting of low side MOSFET chip 6 is low side drain electrode, institute in 3 surface of first terminal, the bottom of low side MOSFET chip 6
Low side drain electrode is stated to contact by the first metal end 3 and the high-end source electrode at high-end 2 top of MOSFET chip.Low side MOSFET core
The connection type of piece 6 and high-end MOSFET chip 2 can be any way, such as can be connected by conducting wire level, this implementation
Example is preferably that low side MOSFET chip 6 is arranged on high-end MOSFET chip 2 by 3 stacking of the first metal end, to subtract
Small semiconductor package size.
Broken line type sheet metal 7, the horizontal end of the broken line type sheet metal 7 include the second metal terminal 9, the second metal terminal
9 connection 6 top low side source electrodes of low side MOSFET chip erect end and are electrically connected with substrate ground wire.The shape of the broken line type sheet metal 9
It can be the various shapes such as arc, the present embodiment is preferably T-type, and the horizontal end of the T-type sheet metal can be by entire encapsulating structure
The surface in the direction containing component covers.So that the passive device of the T-type sheet metal two sides is arranged in not to be influenced by electromagnetic interference,
The encapsulation simultaneously can improve radiating efficiency by the horizontal end of T-type sheet metal that its surface covers.
IC chip 10, is set to substrate surface, by substrate circuit respectively with high-end MOSFET chip 2 and low side MOSFET
The grid of chip 6 is connected, and is used for power control.Wherein, which is set to 1 surface based fashion of substrate, and lead can be used
Bonding technology is connect with substrate circuit, controlled collapsible chip connec-tion can also be used to connect with substrate circuit.To form most short circuit, drop
Low resistance, the present embodiment realize the company of IC chip 10 and substrate circuit preferably through metal ball 11 using controlled collapsible chip connec-tion
It connects, which can be achieved a fixed connection with substrate circuit and the connecting portion of IC chip 10 by conducting resinl 5.
At least one passive device 8 has been constituted for the corresponding position of substrate circuit to be arranged according to the corresponding demand of circuit
Whole DC-DC power switching circuitry.Wherein, it is influenced to avoid passive device 8 not by electromagnetic interference, the present embodiment preferably should
The two sides at the perpendicular end of T-type sheet metal 7 are arranged in one or more passive devices 8.
A kind of working principle of novel system encapsulating structure: the bottom of high-end MOSFET chip 2 on substrate 1 is set
High-end drain electrode is electrically connected by substrate wiring with Input voltage terminal.Low side MOSFET chip 6 passes through sub 3 heaps of the first metal end
It is folded to be arranged on high-end MOSFET chip 2, the bottom low side drain electrode of low side MOSFET chip 6 by the first metal end 3 and
The high-end source electrode series winding at high-end 2 top of MOSFET chip.6 top low side source electrode of low side MOSFET chip, passes through T-type sheet metal 7
Perpendicular end is electrically connected to form access with substrate ground terminal.For the control for realizing power, IC chip 10 is set using 11 upside-down mounting of metal ball
It is placed in 1 surface of substrate, is connected respectively with the grid of high-end MOSFET chip 2 and low side MOSFET chip 6 by substrate circuit.For
The impulse of voltage when suppressing power switch starts, circuit also add one or more passive devices such as capacitor and inductance 8, setting
In the two sides at the perpendicular end of T-type sheet metal 7.To constitute complete DC-DC power switching circuit.
The technical solution of the present embodiment, by the way that at least one passive device to be arranged in the two sides at the perpendicular end of T-type sheet metal, and
The horizontal end of T-type sheet metal covers the surface in the direction containing component of entire encapsulating structure, shields electromagnetic interference to device for no reason at all
Influence, and the horizontal end of T-type sheet metal improve the system encapsulation radiating efficiency.Meanwhile IC chip is set by metal ball upside-down mounting
It sets on substrate, forms most short circuit, lower resistance.Two MOSFET chips are stacked using superposition mould process to be arranged in substrate
On, reduce the size of system encapsulation.
Embodiment two
Fig. 4 A is the top view of one of embodiment of the present invention two novel system encapsulating structure, and the present embodiment is in embodiment
On the basis of system seal structure described in one, T-type sheet metal is replaced with into L-type sheet metal and rectangular metal plate.System envelope
Dress be applicable to DC-to-dc converter, the system encapsulation include: substrate 1, high-end MOSFET chip 2, the first metal end 3,
Low side MOSFET chip 6, L-type sheet metal 12, rectangular metal plate 13, IC chip 10 and at least one passive device 8.
Wherein, L-type sheet metal 12 is to have type conductive metal, the ground terminal of conductive metal one end connecting substrate circuit, separately
One end connects 6 top low side source electrode of low side MOSFET chip.The conductive metal can be any broken line shape, preferably L-type,
The shorter one end of middle L-type the first metal end can be connect by conducting resinl 5 with the ground terminal of substrate circuit, and longer one end can
To be electrically connected by the top low side source electrode of conducting resinl 5 and low side MOSFET chip 6.
It is influenced to protect passive device 8 not by electromagnetic interference, increases rectangular metal plate 13 and cover on the upper of the passive device 8
Side, for shielding the influence of electromagnetic interference.
The technical solution of the present embodiment shields electromagnetic interference by the way that rectangular metal plate to be covered on to the top of passive device
Influence to device for no reason at all, and the horizontal end of L-type sheet metal improves the radiating efficiency of MOSFET chip in system encapsulation.Meanwhile
IC chip is disposed on the substrate by metal ball upside-down mounting, forms most short circuit, lowers resistance.Two MOSFET chips use superposition
Mould process stacking is disposed on the substrate, and reduces the size of system encapsulation.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention
It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also
It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (5)
1. a kind of system in package characterized by comprising
Substrate, for carrying the component in encapsulating structure；
High-end Metal Oxide Semiconductor Field Effect Transistor MOSFET chip is arranged in substrate surface, the high-end drain electrode in bottom
It is electrically connected by substrate wiring with Input voltage terminal；
The first metal end, one end of the first metal end are connected with substrate circuit, and the other end is arranged in high-end MOSFET
Chip surface, for connecting the high-end source electrode of high-end MOSFET chip；
Low side MOSFET chip is set to the first metal end sublist face, and the bottom of low side MOSFET chip is low side drain electrode, described
Low side drain electrode is contacted by the high-end source electrode at the top of the first metal end and high-end MOSFET chip；
Broken line type sheet metal, the horizontal end of the broken line type sheet metal include the second metal terminal, and the connection of the second metal terminal is low
Low side source electrode at the top of MOSFET chip is held, end is erected and is electrically connected with substrate ground terminal；
Wherein, the broken line type sheet metal is T-type sheet metal, has the function of the electromagnetic interference of protection passive device, and to entire
It is packaged with the function of heat dissipation；The horizontal end of T-type sheet metal covers the surface in the direction containing component of entire encapsulating structure；
IC chip is set to substrate surface, by substrate circuit respectively with high-end MOSFET chip and low side
The grid of MOSFET chip is connected, and is used for power control；
At least one passive device, for the corresponding of broken line type sheet metal two sides substrate circuit to be arranged according to the corresponding demand of circuit
Position constitutes complete DC-DC DC-DC power switching circuitry.
2. system according to claim 1 grade encapsulates, it is characterised in that:
The IC chip is connect using lead key closing process with substrate circuit.
3. system according to claim 1 grade encapsulates, it is characterised in that:
The IC chip is connect using controlled collapsible chip connec-tion with substrate circuit.
4. system in package according to claim 3, it is characterised in that:
The IC chip is connect with substrate circuit by metal ball.
5. system according to claim 1 grade encapsulates, it is characterised in that:
The MOSFET chip is disposed on the substrate using superposition mould process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510633468.9A CN105355606B (en) | 2015-09-28 | 2015-09-28 | A kind of novel system grade encapsulation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510633468.9A CN105355606B (en) | 2015-09-28 | 2015-09-28 | A kind of novel system grade encapsulation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105355606A CN105355606A (en) | 2016-02-24 |
| CN105355606B true CN105355606B (en) | 2019-05-28 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510633468.9A Active CN105355606B (en) | 2015-09-28 | 2015-09-28 | A kind of novel system grade encapsulation |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101419964A (en) * | 2007-10-26 | 2009-04-29 | 英飞凌科技股份公司 | Device with a plurality of semiconductor chips |
| CN102468292A (en) * | 2010-10-29 | 2012-05-23 | 万国半导体股份有限公司 | Packaging body structure for direct current-direct current convertor |
| EP2525401A2 (en) * | 2011-05-19 | 2012-11-21 | International Rectifier Corporation | Common drain exposed conductive clip for high power semiconductor packages |
| CN103515370A (en) * | 2012-06-21 | 2014-01-15 | 尼克森微电子股份有限公司 | Power semiconductor package and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7618896B2 (en) * | 2006-04-24 | 2009-11-17 | Fairchild Semiconductor Corporation | Semiconductor die package including multiple dies and a common node structure |
-
2015
- 2015-09-28 CN CN201510633468.9A patent/CN105355606B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101419964A (en) * | 2007-10-26 | 2009-04-29 | 英飞凌科技股份公司 | Device with a plurality of semiconductor chips |
| CN102468292A (en) * | 2010-10-29 | 2012-05-23 | 万国半导体股份有限公司 | Packaging body structure for direct current-direct current convertor |
| EP2525401A2 (en) * | 2011-05-19 | 2012-11-21 | International Rectifier Corporation | Common drain exposed conductive clip for high power semiconductor packages |
| CN103515370A (en) * | 2012-06-21 | 2014-01-15 | 尼克森微电子股份有限公司 | Power semiconductor package and manufacturing method thereof |
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| Publication number | Publication date |
|---|---|
| CN105355606A (en) | 2016-02-24 |
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