CN105355574A - Preparation method of NiAu projection and NiAu projection assembly - Google Patents
Preparation method of NiAu projection and NiAu projection assembly Download PDFInfo
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- CN105355574A CN105355574A CN201510778810.4A CN201510778810A CN105355574A CN 105355574 A CN105355574 A CN 105355574A CN 201510778810 A CN201510778810 A CN 201510778810A CN 105355574 A CN105355574 A CN 105355574A
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- 238000002360 preparation method Methods 0.000 title abstract 2
- 229910052751 metal Inorganic materials 0.000 claims abstract description 164
- 239000002184 metal Substances 0.000 claims abstract description 164
- 239000000463 material Substances 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000001039 wet etching Methods 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 34
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 claims description 29
- 229910052759 nickel Inorganic materials 0.000 claims description 17
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 14
- 239000010931 gold Substances 0.000 claims description 14
- 229910052737 gold Inorganic materials 0.000 claims description 14
- 238000002161 passivation Methods 0.000 claims description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 10
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims description 10
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- 239000010936 titanium Substances 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 239000013043 chemical agent Substances 0.000 claims description 3
- 238000003384 imaging method Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000007747 plating Methods 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 30
- 230000006872 improvement Effects 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000003993 interaction Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- ZBTDWLVGWJNPQM-UHFFFAOYSA-N [Ni].[Cu].[Au] Chemical compound [Ni].[Cu].[Au] ZBTDWLVGWJNPQM-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000003223 protective agent Substances 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32131—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Die Bonding (AREA)
- ing And Chemical Polishing (AREA)
- Weting (AREA)
Abstract
The invention provides a preparation method of a NiAu projection. The method comprises that a Ti or TiW metal layer and an Au metal layer are formed between a wafer and the NiAu projection from top to bottom, the Au metal layer outside the projection is removed from top to bottom in a physical dry etching manner, the Ti or TiW metal layer is removed via a wet etching manner, and reaction of a galvanic cell and excessive etching of the Ni material of the projection caused by the wet etching manner are avoided. The invention also provides a NiAu projection assembly which comprises the projection, a seed metal layer and a substrate metal layer, wherein the projection comprises a reserved layer, the Au metal layer and a Ni metal layer are successively from top to bottom, the seed metal layer and the substrate metal layer are arranged at the bottom of the projection, the lateral side of the Au metal layer and the lateral side of the projection are leveled in the vertical direction, and relatively large combination area and combination force between the projection and the wafer are ensured.
Description
Technical field
The present invention relates to integrated circuit fields, particularly relate to a kind of nickel gold method for producing lug and nickel gold projection assembly.
Background technology
Projection is usually used in IC wafers encapsulation technology, along with increasing wafer needs to change original design and make to adapt to different encapsulation modes, need to make respective bump pattern to satisfy the demands on wafer thereupon, projection cube structure and materials demand are also got more and more simultaneously.
In the process making projection, need on wafer, form metal material substrate layer and Seed Layer, then generate projection on the seed layer needs to remove two layers of metal level unnecessary outside projection after producing lug completes.Current projection uses more material for gold, and copper and copper nickel gold etc., general gold bump is equipped with the Seed Layer of titanium tungsten+golden material, and the projection of other materials coordinates the Seed Layer of titanium or titanium tungsten+copper material.But the chip of some specific function, need special projection cube structure, as nickel gold material projection, but to coordinate conventional titanium tungsten+gold, titanium, or during titanium tungsten+copper material Seed Layer, when after projection generates, the Seed Layer unnecessary to projection bottom outside takes wet etching mode to remove, due to copper, the metal potential difference of nickel and gold, add the auxiliary of wet liquid, cause copper metal level generation galvanic interaction, accelerate the etching of Seed Layer, in addition, also the excessive undercutting of whole nickel matter projection can be caused, reduce the bonded area of projection and metal level, adhesion is caused to decline, and then produce the phenomenon that projection peels off wafer too early.
In view of this, be necessary to provide the manufacture method of a kind of nickel of improvement gold projection and nickel gold projection assembly to solve the problem.
Summary of the invention
The object of the present invention is to provide and a kind ofly prevent from the Seed Layer of underbump from excessive root occurring when etching cutting and nickel gold method for producing lug and the golden projection assembly of nickel thereof that can ensure the bonded area of projection and wafer and adhesion.
For achieving the above object, the invention provides the manufacture method of a kind of nickel gold projection, comprise the following steps:
One wafer is provided, described wafer is provided with backing metal;
Passivation protection layer is provided with, sputter the first metal layer on described passivation protection layer and the described backing metal of part above described wafer and described backing metal, and sputter second metal level on the first metal layer;
Described second metal level arranges photoresist layer;
Exposure imaging, described photoresist layer manufactures the pane of described projection, and described pane is right against the position of described backing metal;
Electronickelling matter metal level in described pane, and plating forms golden metal level on described nickel matter metal level, the side of described nickel matter metal level and golden metal level is fitted on the side of described pane;
Remove photoresist layer, remove the photoresist layer outside described pane with chemical agent;
The second metal level of described projection bottom outside is positioned at by the dry ecthing mode from up to down uniform etching removal of physical bombardment;
Wet etching mode is utilized to etch removal the first metal layer;
After high-temperature baking release stress, complete the making of described projection.
As a further improvement on the present invention, the thickness that the etch quantity parameter by setting etching machine is not less than described second metal level guarantees that described second metal level be positioned at outside described projection is possible to determine when the sample has been completely etched removal.
As a further improvement on the present invention, described golden metal level is also electroplate with reserved layer, by the mode of described dry ecthing, the etching of described projection thickness is lost to compensate.
As a further improvement on the present invention, the material of described the first metal layer is titanium or titanium tungsten.
As a further improvement on the present invention, the material of described second metal level is gold.
The present invention also provides a kind of nickel gold projection assembly, protrusion is formed at above semiconductor wafer assembly, described nickel gold projection assembly comprises the projection of lower end band protuberance, be bonded in the metal level between described projection and described wafer assembly, described projection comprises golden metal level, the reserved layer being arranged at the nickel matter metal level under described golden metal level and being arranged on described golden metal level, described projection and metal level have the upper surface being positioned at top and the lower surface being positioned at bottom respectively, described metal level comprises the seed metal layer being arranged on described underbump, and the substrate metal layer be arranged under described seed metal layer, described projection and seed metal layer have the first side and the second side that are positioned at surrounding respectively, first side of described projection is mutually concordant with the correspondence second side in the vertical direction of described seed metal layer.
As a further improvement on the present invention; described wafer assembly comprises wafer, the backing metal be arranged on described wafer; and the passivation protection layer be arranged on described backing metal and described wafer, described passivation protection layer has an inversed taper platform hole of matching with the protuberance of described projection.
As a further improvement on the present invention, the material of described reserved layer is gold.
As a further improvement on the present invention, the material of described substrate metal layer is titanium or titanium tungsten.
As a further improvement on the present invention, the material of described seed metal layer is gold.
The invention has the beneficial effects as follows: the present invention successively forms the first metal layer on wafer assembly, the projection of the second metal level and nickel gold material, described projection and described second metal level fit, the second metal level being positioned at described projection bottom outside is from up to down removed by using the dry ecthing mode of physical bombardment, the mode re-using wet etching removes the first metal layer, and the side of described seed metal layer is mutually concordant with the side in the vertical direction of projection, ensure that the bonded area between projection assembly and wafer assembly and adhesion, avoid because wet etching mode causes galvanic interaction, and the nickel material over etching bottom described projection, thus avoid the bonded area of projection and metal level and the reduction of adhesion.
Accompanying drawing explanation
Fig. 1 is the schematic diagram after nickel of the present invention gold projection generates.
Fig. 2 is that the metal level of the present invention to the nickel gold projection after generation takes the schematic diagram after wet etching.
Fig. 3 is that the metal level of the present invention to the nickel gold projection after generation takes the schematic diagram after dry ecthing.
Embodiment
Describing the present invention below with reference to each execution mode shown in the drawings, is below the present invention one better embodiment.
Refer to Fig. 1, Fig. 3, the present invention relates to the projection assembly 100 of a kind of nickel gold material, protrude and be formed on semiconductor wafer assembly 200.Described projection assembly 100 comprise lower end with protuberance 110 nickel gold material projection 10, to be bonded between described projection 10 and described wafer assembly 200 metal level 20 that its upper and lower surface i.e. fits with the bottom of described projection 10 and the top of wafer assembly 200 respectively.
Described projection 10 comprises golden metal level 11, be arranged at described golden metal level 11 under nickel matter metal level 12 and the reserved layer 13 that is arranged on described golden metal level 11.Described metal level 20 comprises the seed metal layer 221 of sputter in described projection 10 bottom and the sputter substrate metal layer 211 at described seed metal layer 221 lower surface.The material of described substrate metal layer 211 is titanium or titanium tungsten, and the material of described seed metal layer 221 is gold, and the material of described reserved layer 13 is also gold.
Described projection 10 and seed metal layer 221 have the first side 14 and the second side 222 being positioned at surrounding respectively, and the first side 14 of described projection 10 is mutually concordant with the second side 222 in the vertical direction of described seed metal layer 221 correspondence.Described substrate metal layer 211 also has the 3rd side 212 being positioned at surrounding, and described 3rd side 212 is positioned at the inner side of described second side 222.
Described first side 14 is mutually concordant with described second side 222 in the vertical direction, can ensure that described seed metal layer 221 and described substrate metal layer 211 have larger lower surface area, thus ensure bonded area and both adhesions of projection assembly 100 bottom and described wafer assembly 200.
Described wafer assembly 200 comprises wafer 210, the backing metal 220 be formed on described wafer 210, and is formed in the passivation protection layer 230 of described backing metal 220 and described wafer 210 upper surface.Described passivation protection layer 230 has an inversed taper platform hole 240 of matching with described protuberance 110; inversed taper platform hole 240 has a hole sidewall 241; described hole sidewall 241 is extended on the upper surface of described backing metal 220 from top to bottom, and the area that sidewall 241 bottom, described hole is formed is less than the area of described backing metal 220 upper surface.The lower surface of described substrate metal layer 211 is fitted in the upper surface of described passivation protection layer 230 and the described backing metal 220 of part.
The present invention also provides the method making described nickel gold material projection 10, comprises the following steps:
Described wafer 210 is provided, described wafer 210 is provided with backing metal 220, and the portion of upper surface of backing metal 220 is provided with passivation protection layer 230 described in described wafer 210 and peripheral portion.
The first metal layer 21 described in the upper surface sputter of described passivation protection layer 230 and the described backing metal 220 of part; and at upper surface sputter second metal level 22 of the first metal layer 21, with the upper surface making described the first metal layer 21 and the second metal level 22 be formed in described passivation protection layer 230 and the described backing metal 220 of part.
At the upper surface of described second metal level 22, photoresist layer 30 is set.
Exposure imaging, described photoresist layer 30 manufactures the pane 40 of described projection 10, and described pane 40 is just corresponding to the position of described backing metal 220.Set up light shield (not shown) outside photoresist layer 30 above described backing metal 220, described light shield is positioned at directly over described backing metal 220.By UV-irradiation, photoresist layer 30 produces the pane 40 being right against described backing metal 220.Described pane 40 has the side being positioned at surrounding, the roof of described side and described backing metal 220 is perpendicular or be from up to down outwards obliquely installed with the roof of described backing metal 220, to make the projection of formation tapered shape, the bottom of described projection 10 is avoided to be etched excessively and to cause reducing with the contact area of described metal level 20.
Using electro-plating method electroplate described nickel matter metal level 12 described pane 40 in, and electroplate the golden metal level 11 of formation at the upper surface of described nickel matter metal level 12, fits the side of described pane 40 in the side of described nickel matter metal level 12 and golden metal level 11.Reserved layer 13 is electroplate with in advance, for compensating the thickness loss causing described golden metal level 11 after the dry ecthing of physical bombardment at the upper surface of described golden metal level 11.
Remove photoresist layer 30, remove the described photoresist layer 30 outside described pane 40 with chemical agent.
The thickness of described second metal level 22 is not less than by the etch quantity parameter setting dry etcher, the second metal level 22 removed and be positioned at described projection 10 bottom outside is from up to down etched with the etching mode of physical bombardment, thus guarantee that described second metal level 22 of described projection 10 bottom outside is possible to determine when the sample has been completely etched removal, the second side 222 in the vertical direction making the first side 14 of described projection 10 and residue be fitted in the second metal level 22 of described projection 10 lower surface is mutually concordant, ensure follow-up when described the first metal layer 21 is etched, the first metal layer 21 of larger area can be had, and then ensure bonded area and both adhesions of described projection assembly 100 and wafer assembly 200.Now remain the second metal level 22 being fitted in described projection 10 lower surface and be described seed metal layer 221.
Recycling wet etching mode removes the first metal layer 21, adds side direction protective agent, to avoid causing the excessive root of described the first metal layer 21 to cut when etching described the first metal layer 21 in chemical etchant.Now remain the first metal layer 21 being fitted in described second metal level 22 lower surface and be described substrate metal layer 211.
After high-temperature baking release stress, complete the making of described projection 10.
See Fig. 2, when described the first metal layer 21 being etched according to use wet etching mode, described reserved layer 13 can be caused, and the described projection 10 of nickel gold material can by irregular etched, and then cause described projection 10 to reduce with the bonded area of metal level 20, and then described projection 10 is caused to decline with the adhesion of described metal level 20.
In sum, the present invention successively forms the projection 10 of titanium or the first metal layer 21 of titanium tungsten material, golden second metal level 22 and nickel gold material on described wafer 200, described projection 10 fits with described second metal level 22, described second metal level 22 removed and be positioned at outside described projection 10 is from up to down etched by using the dry ecthing mode of physical bombardment, avoid because wet etching mode causes galvanic interaction, and the nickel material over etching bottom described projection 10, thus avoid described projection 10 and the bonded area of metal level 20 and the reduction of adhesion.
Be to be understood that, although this specification is described according to execution mode, but not each execution mode only comprises an independently technical scheme, this narrating mode of specification is only for clarity sake, those skilled in the art should by specification integrally, technical scheme in each execution mode also through appropriately combined, can form other execution modes that it will be appreciated by those skilled in the art that.
A series of detailed description listed is above only illustrating for feasibility execution mode of the present invention; they are also not used to limit the scope of the invention, all do not depart from the skill of the present invention equivalent implementations done of spirit or change all should be included within protection scope of the present invention.
Claims (10)
1. a manufacture method for nickel gold projection, is characterized in that, comprise the following steps:
One wafer is provided, described wafer is provided with backing metal;
Passivation protection layer is provided with, sputter the first metal layer on described passivation protection layer and the described backing metal of part above described wafer and described backing metal, and sputter second metal level on the first metal layer;
Described second metal level arranges photoresist layer;
Exposure imaging, described photoresist layer manufactures the pane of described projection, and described pane is right against the position of described backing metal;
Electronickelling matter metal level in described pane, and plating forms golden metal level on described nickel matter metal level, the side of described nickel matter metal level and golden metal level is fitted on the side of described pane;
Remove photoresist layer, remove the photoresist layer outside described pane with chemical agent;
The second metal level of described projection bottom outside is positioned at by the dry ecthing mode from up to down uniform etching removal of physical bombardment;
Wet etching mode is utilized to etch removal the first metal layer;
After high-temperature baking release stress, complete the making of described projection.
2. nickel gold method for producing lug according to claim 1, is characterized in that: the thickness being not less than described second metal level by the etch quantity parameter setting etching machine guarantees that described second metal level be positioned at outside described projection is possible to determine when the sample has been completely etched removal.
3. nickel gold method for producing lug according to claim 1, be is characterized in that: described golden metal level is also electroplate with reserved layer, is lost to compensate by the mode of described dry ecthing to the etching of described projection thickness.
4. nickel gold method for producing lug according to claim 1, is characterized in that: the material of described the first metal layer is titanium or titanium tungsten.
5. nickel gold method for producing lug according to claim 1, is characterized in that: the material of described second metal level is gold.
6. a nickel gold projection assembly, protrusion is formed at above semiconductor wafer assembly, it is characterized in that: described nickel gold projection assembly comprises the projection of lower end band protuberance, be bonded in the metal level between described projection and described wafer assembly, described projection comprises golden metal level, the reserved layer being arranged at the nickel matter metal level under described golden metal level and being arranged on described golden metal level, described projection and metal level have the upper surface being positioned at top and the lower surface being positioned at bottom respectively, described metal level comprises the seed metal layer being arranged on described underbump, and the substrate metal layer be arranged under described seed metal layer, described projection and seed metal layer have the first side and the second side that are positioned at surrounding respectively, first side of described projection is mutually concordant with the correspondence second side in the vertical direction of described seed metal layer.
7. nickel gold projection assembly according to claim 6; it is characterized in that: described wafer assembly comprises wafer, the backing metal be arranged on described wafer; and the passivation protection layer be arranged on described backing metal and described wafer, described passivation protection layer has an inversed taper platform hole of matching with the protuberance of described projection.
8. nickel gold projection assembly according to claim 6, is characterized in that: the material of described reserved layer is gold.
9. nickel gold projection assembly according to claim 6, is characterized in that: the material of described substrate metal layer is titanium or titanium tungsten.
10. nickel gold projection assembly according to claim 6, is characterized in that: the material of described seed metal layer is gold.
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|---|---|---|---|
| CN201510778810.4A CN105355574B (en) | 2015-11-13 | 2015-11-13 | The production method and nickel gold convex block component of nickel gold convex block |
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| CN201510778810.4A CN105355574B (en) | 2015-11-13 | 2015-11-13 | The production method and nickel gold convex block component of nickel gold convex block |
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| CN105355574A true CN105355574A (en) | 2016-02-24 |
| CN105355574B CN105355574B (en) | 2018-12-11 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108511338A (en) * | 2017-02-27 | 2018-09-07 | Imec 非营利协会 | A method of limiting the pattern for conductive path in the dielectric layer |
| EP3644352A1 (en) * | 2018-10-25 | 2020-04-29 | SPTS Technologies Limited | A method of fabricating integrated circuits |
| CN112687647A (en) * | 2020-12-28 | 2021-04-20 | 颀中科技（苏州）有限公司 | Flip chip structure and preparation method thereof |
| WO2022095764A1 (en) * | 2020-11-04 | 2022-05-12 | International Business Machines Corporation | Pillar bump with noble metal seed layer for advanced heterogeneous integration |
Citations (5)
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| CN108511338A (en) * | 2017-02-27 | 2018-09-07 | Imec 非营利协会 | A method of limiting the pattern for conductive path in the dielectric layer |
| CN108511338B (en) * | 2017-02-27 | 2020-11-10 | Imec 非营利协会 | Method for defining pattern for conductive path in dielectric layer |
| EP3644352A1 (en) * | 2018-10-25 | 2020-04-29 | SPTS Technologies Limited | A method of fabricating integrated circuits |
| KR20200047406A (en) * | 2018-10-25 | 2020-05-07 | 에스피티에스 테크놀러지스 리미티드 | A method of fabricating integrated circuits |
| US11361975B2 (en) | 2018-10-25 | 2022-06-14 | Spts Technologies Limited | Method of fabricating integrated circuits |
| KR102542747B1 (en) | 2018-10-25 | 2023-06-12 | 에스피티에스 테크놀러지스 리미티드 | A method of fabricating integrated circuits |
| WO2022095764A1 (en) * | 2020-11-04 | 2022-05-12 | International Business Machines Corporation | Pillar bump with noble metal seed layer for advanced heterogeneous integration |
| US11380641B2 (en) | 2020-11-04 | 2022-07-05 | International Business Machines Corporation | Pillar bump with noble metal seed layer for advanced heterogeneous integration |
| GB2615681A (en) * | 2020-11-04 | 2023-08-16 | Ibm | Pillar bump with noble metal seed layer for advanced heterogeneous integration |
| CN112687647A (en) * | 2020-12-28 | 2021-04-20 | 颀中科技（苏州）有限公司 | Flip chip structure and preparation method thereof |
| WO2022142865A1 (en) * | 2020-12-28 | 2022-07-07 | 颀中科技（苏州）有限公司 | Flip chip structure and method for preparation thereof |
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