CN105353688A - Intelligent ammeter strain control system based on anti-interference analog time-base circuit - Google Patents
Intelligent ammeter strain control system based on anti-interference analog time-base circuit Download PDFInfo
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- CN105353688A CN105353688A CN201510849013.0A CN201510849013A CN105353688A CN 105353688 A CN105353688 A CN 105353688A CN 201510849013 A CN201510849013 A CN 201510849013A CN 105353688 A CN105353688 A CN 105353688A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/21—Pc I-O input output
- G05B2219/21164—Resistors between transmitter and receiver, against disturbances
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Abstract
The invention discloses an intelligent ammeter strain control system based on an anti-interference analog time-base circuit. The intelligent ammeter strain control system mainly comprises a processor, an information acquisition unit, an analysis unit and a signal classification unit that are both connected to the processor, a signal confirmation unit connected to the signal classification unit, a protection unit and a selection unit that are both connected to the signal confirmation unit, and a display unit connected to the selection unit. The intelligent ammeter strain control system is characterized in that an anti-interference analog time-base circuit is in series connection between the signal confirmation unit and the selection unit, and a digital strain circuit is in series connection between the information acquisition unit and the processor. The anti-interference analog time-base circuit can effectively prevent high-frequency interference signals among signals output from the signal confirmation unit from entering the selection unit through a signal transmission channel. Therefore, the accuracy of operation of the selection unit is improved, and private information of a client is prevented from leaking.
Description
Technical field
The present invention relates to electrical equipment technical field, specifically refer to a kind of intelligent electric meter strain controlling system based on anti-interference simulation time base circuit.
Background technology
At present, the development built along with China's intelligent grid, people are also increasing substantially to the demand of intelligent electric meter.But existing intelligent electric meter, because of the imperfection of its control system, easily cause the details of user to be revealed to Utilities Electric Co. inadvertently, and the leakage of these information may bring serious consequence to consumer.Therefore, provide a kind of and can guarantee that the privacy of user is not then seemed excellent in important by the control system of the intelligent electric meter revealed.
Summary of the invention
The object of the invention is to overcome ammeter in prior art and easily reveal the defect of privacy of user, the invention provides a kind of intelligent electric meter strain controlling system based on anti-interference simulation time base circuit.
The present invention is achieved through the following technical solutions: a kind of intelligent electric meter strain controlling system based on anti-interference simulation time base circuit, primarily of processor, information acquisition unit, the analytic unit be all connected with processor and signal sort out unit, the signal confirmation unit that unit is connected is sorted out with signal, the protected location be all connected with signal confirmation unit and selection unit, the display unit be connected with selection unit, be serially connected in the anti-interference simulation time base circuit between signal confirmation unit and selection unit, and the digital strain circuit composition be serially connected between information acquisition unit and processor.
Described anti-interference simulation time base circuit by time base chip U2, triode VT3, triode VT4, field effect transistor Q1, negative pole is connected with the emitter of triode VT3 after resistance R18, the polar capacitor C9 that positive pole is connected with the collector of triode VT4 after resistance R15, positive pole is connected with the negative pole of polar capacitor C9 after resistance R17 through diode D7 in turn, the polar capacitor C7 of negative pole ground connection after resistance R13, N pole is connected with the negative pole of polar capacitor C9, the diode D11 that P pole is connected with the base stage of triode VT4 after resistance R19, N pole with time base chip U2 TR pin be connected, the diode D8 that P pole is connected with the positive pole of polar capacitor C9 after resistance R16, N pole with time base chip U2 R pin be connected, P pole is in turn through diode D9 that resistance R14 is connected with the collector of triode VT4 after polar capacitor C8, positive pole is connected with the collector of triode VT3, negative pole with time base chip U2 the polar capacitor C10 that is connected of Q pin, one end with time base chip U2 THR pin be connected, the resistance R20 that the other end is connected with the grid of field effect transistor Q1, P pole is connected with the source electrode of field effect transistor Q1, the diode D10 that N pole is connected with the drain electrode of field effect transistor Q1 after resistance R21, and positive pole is connected the N pole of diode D10 after resistance R22, the polar capacitor C11 of negative pole and ground connection forms, time described, the CV pin of base chip U2 is connected with the emitter of triode VT4 respectively with DIS pin, its VC pin is connected with the base stage of triode VT3, its GND pin ground connection, the negative pole of described polar capacitor C7 as anti-interference simulation time base circuit input end and be connected with signal confirmation unit, the positive pole of described polar capacitor C11 as anti-interference simulation time base circuit output terminal and be connected with selection unit.
Described digital strain circuit is by process chip U1, amplifier P1, triode VT1, triode VT2, negative pole is connected with the base stage of triode VT2, positive pole is in turn through polar capacitor C5 that resistance R2 is connected with the VDD pin of process chip U1 after diode D1 and resistance R8, one end is connected with the base stage of triode VT2, the resistance R5 that the other end is connected with the EOC pin of process chip U1, input end as digital strain circuit while one end is connected with the positive pole of polar capacitor C5 is connected with information acquisition circuit, the resistance R3 that the other end is connected with the REF pin of process chip U1, minus earth, the polar capacitor C1 that positive pole is connected with the VDD pin of process chip U1 after resistance R4, N pole is connected with the emitter of triode VT2 after resistance R6, P pole is in turn through diode D3 that resistance R7 is connected with the OUT pin of process chip U1 after diode D4 and resistance R10, positive pole is connected with the collector of triode VT2, the polar capacitor C2 that negative pole is connected with the P pole of diode D3 after resistance R1, positive pole is connected with the IN pin of process chip U1, the polar capacitor C6 of minus earth, N pole is connected with the VDD pin of process chip U1 after inductance L, the diode D2 that P pole is connected with the DIN pin of process chip U1, positive pole is connected with the N pole of diode D2 after resistance R9, the polar capacitor C3 that negative pole is connected with the base stage of triode VT1, positive pole is connected with the emitter of triode VT1, the polar capacitor C4 that negative pole is connected with the CS pin of process chip U1 after diode D5, and P pole is connected with the collector of triode VT1 after resistance R11, the diode D6 that N pole is connected with the output terminal of amplifier P1 after resistance R12 forms, the negative pole of described amplifier P1 is connected with the OUT pin of process chip U1, its positive pole is connected with the negative pole of polar capacitor C4, its output terminal then as digital strain circuit output terminal and be connected with processor, the IN pin of described process chip U1 is connected with the N pole of diode D3, its GND pin ground connection.
Further, described signal confirmation unit is also connected with SIM unit; Described selection unit is also connected with encrypted tunnel; For guaranteeing best result of use of the present invention, described process chip U1 is MAX1494 integrated chip; Time described, base chip U2 is KA555 integrated chip.
The present invention compared with prior art has the following advantages and beneficial effect:
(1) anti-interference simulation time base circuit of the present invention can scurry into selection unit by signal transmission passage by high-frequency interferencing signal in the signal that exports of effective anti-stop signal confirmation unit, thus improve the accuracy of selection unit work, ensure that the privacy information of user side is not revealed.
(2) the different load data message of current through meter can be converted to different signal codes by digital strain circuit of the present invention, thus effectively ensure that the privacy information of user side is not revealed.
(3) signal of the present invention sorts out the signal wave information decomposition generated after processor can be changed by unit is privacy information and general information, thus improve intelligent electric meter control system of the present invention to the accuracy of user profile Classification Management, ensure that the privacy information of user side is not revealed simultaneously.
Accompanying drawing explanation
Fig. 1 is one-piece construction block diagram of the present invention.
Fig. 2 is the electrical block diagram of digital strain circuit of the present invention.
Fig. 3 is the electrical block diagram of anti-interference simulation time base circuit of the present invention.
Embodiment
Below in conjunction with embodiment, the present invention is described in further detail, but embodiments of the present invention are not limited thereto.
As shown in Figure 1, the present invention is primarily of information acquisition unit, processor, the analytic unit be all connected with processor and signal sort out unit, the signal confirmation unit that unit is connected is sorted out with signal, the protected location be all connected with signal confirmation unit and SIM unit and selection unit, the display unit be all connected with selection unit and encrypted tunnel, input end is connected with signal confirmation unit, the anti-interference simulation time base circuit that its output terminal is connected with selection unit, and input end is connected with information acquisition unit, the digital strain circuit that its output terminal is connected with processor forms.
During enforcement, the different load data message of the current through meter that information acquisition unit gathers by digital strain circuit of the present invention is converted to different signal codes, described analytic unit measures load parameter by analyzing this signal code, to draw the information such as electrical equipment kind and electricity of electricity consumption.System thresholds is provided with in this described analytic unit; private data and general data is drawn by comparing with threshold data; this analytic unit analysis is transferred to two groups that draw different information datas is simultaneously transferred to signal again after processor carries out information processing and sorts out unit; this signal is sorted out unit and is then reaffirmed being sent to information confirmation unit after privacy information and general information classification packing, and is left in protected location by privacy information.
Due to, being separated privacy signal is very important systems engineering, so be also provided with anti-interference simulation time base circuit in the present invention, this anti-interference simulation time base circuit has stronger anti-interference, can scurry into selection unit by signal transmission passage by high-frequency interferencing signal in effective anti-stop signal confirmation unit output signal, interference selection unit is to the separation of signal.
Meanwhile, the information of output can be carried out classification and be exported by described selection unit.Electric quantity data information is sent to display unit by this selection unit, and this display unit is for showing the electricity of ammeter.Described selection unit transfers out after then sending to encrypted tunnel to be encrypted other electric charge parameter information, and this just effectively avoids the private data sent in data and is revealed.
In order to better implement the present invention, described SIM unit is arranged in confirmation unit, is also provided with signal receiver and signal projector in this SIM unit.When user allows, user can send and allow code to SIM unit, and this SIM unit just can send and allow access instruction and confirm that password is to signal confirmation unit, and the data in described protected location can send through encrypted tunnel.Arranging of SIM unit can also facilitate the metering situation of user's real-time query ammeter and arrange payment reminding service simultaneously.
As shown in Figure 2, described digital strain circuit by process chip U1, amplifier P1, triode VT1, triode VT2, resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, resistance R8, resistance R9, resistance R10, resistance R11, resistance R12, polar capacitor C1, polar capacitor C2, polar capacitor C3, polar capacitor C4, polar capacitor C5, polar capacitor C6, diode D1, diode D2, diode D3, diode D4, diode D5, and diode D6 forms.
During connection, the negative pole of polar capacitor C5 is connected with the base stage of triode VT2, its positive pole is connected with the P pole of diode D1 after resistance R2, and the N pole of described diode D1 is connected with the VDD pin of process chip U1 after resistance R8.One end of resistance R5 is connected with the base stage of triode VT2, the other end is connected with the EOC pin of process chip U1.Input end as digital strain circuit while one end of resistance R3 is connected with the positive pole of polar capacitor C5 is connected with information acquisition circuit, the other end is connected with the REF pin of process chip U1.
Wherein, the minus earth of polar capacitor C1, positive pole are connected with the VDD pin of process chip U1 after resistance R4.The N pole of diode D3 is connected with the emitter of triode VT2 after resistance R6, P pole is connected with the OUT pin of process chip U1 after diode D4 and resistance R10 through resistance R7 in turn.Wherein one end of described resistance R7 is connected with the P pole of diode D4, its other end is connected with the P pole of diode D3, the N pole of described diode D4 is then connected with wherein one end of resistance R10, and the other end of described resistance R10 is then connected with the OUT pin of process chip U1.The positive pole of polar capacitor C2 is connected with the collector of triode VT2, negative pole is connected with the P pole of diode D3 after resistance R1.The positive pole of polar capacitor C6 is connected with the IN pin of process chip U1, minus earth.
Meanwhile, the N pole of diode D2 is connected with the VDD pin of process chip U1 after inductance L, P pole is connected with the DIN pin of process chip U1.The positive pole of polar capacitor C3 is connected with the N pole of diode D2 after resistance R9, negative pole is connected with the base stage of triode VT1.The positive pole of polar capacitor C4 is connected with the emitter of triode VT1, its negative pole is connected with the N pole of diode D5, and the P pole of described diode D5 is then connected with the CS pin of process chip U1.The P pole of diode D6 is connected with the collector of triode VT1 after resistance R11, N pole is connected with the output terminal of amplifier P1 after resistance R12.
The negative pole of described amplifier P1 is connected with the OUT pin of process chip U1, its positive pole is connected with the negative pole of polar capacitor C4, its output terminal then as digital strain circuit output terminal and be connected with processor; The IN pin of described process chip U1 is connected with the N pole of diode D3, its GND pin ground connection.
Different load data message is converted to different signal codes to better realize by digital strain circuit of the present invention, and the process chip U1 in the present invention have employed the MAX1494 integrated chip of 8.Resistance R3 and diode D1 and inductance L are wherein connected in series between the REF pin of MAX1494 integrated chip and DIN pin to realize the gain of different pieces of information signal, EOC pin and resistance R5 and the element such as triode VT2 and diode D3 form input bridge, and this input bridge is used for the difference of detection signal.The different signal code generated after the conversion of MAX1494 integrated chip amplifies output channel by the signal formed by amplifier P1 and the element such as diode D5 and polar capacitor C4 after CS pin and OUT pin and exports.
As shown in Figure 3, described anti-interference simulation time base circuit by time base chip U2, triode VT3, triode VT4, field effect transistor Q1, resistance R13, resistance R14, resistance R15, resistance R16, resistance R17, resistance R18, resistance R19, resistance R20, resistance R21, resistance R22, polar capacitor C7, polar capacitor C8, polar capacitor C9, polar capacitor C10, polar capacitor C11, diode D7, diode D8, diode D9, diode D10, and diode D11 forms.
During connection, the negative pole of polar capacitor C9 is connected with the emitter of triode VT3 after resistance R18, positive pole is connected with the collector of triode VT4 after resistance R15.Negative pole ground connection, its positive pole after resistance R13 of polar capacitor C7 are connected with the P pole of diode D7, and the N pole of described diode D7 is connected with the negative pole of polar capacitor C9 after resistance R17.The N pole of diode D11 is connected with the negative pole of polar capacitor C9, P pole is connected with the base stage of triode VT4 after resistance R19.
Wherein, diode D8 N pole with time base chip U2 TR pin is connected, P pole is connected with the positive pole of polar capacitor C9 after resistance R16.The N pole of diode D9 with time base chip U2 R pin is connected, its P pole is connected with the negative pole of polar capacitor C8 through resistance R14, the positive pole of described polar capacitor C8 is connected with the collector of triode VT4.The positive pole of polar capacitor C10 is connected with the collector of triode VT3, negative pole with time base chip U2 Q pin be connected.One end of resistance R20 with time base chip U2 THR pin is connected, the other end is connected with the grid of field effect transistor Q1.The P pole of diode D10 is connected with the source electrode of field effect transistor Q1, N pole is connected with the drain electrode of field effect transistor Q1 after resistance R21.Positive pole N pole of diode D10 after resistance R22 of polar capacitor C11 is connected, negative pole and ground connection.
Time described, the CV pin of base chip U2 is connected with the emitter of triode VT4 respectively with DIS pin, its VC pin is connected with the base stage of triode VT3, its GND pin ground connection; The negative pole of described polar capacitor C7 as anti-interference simulation time base circuit input end and be connected with signal confirmation unit; The positive pole of described polar capacitor C11 as anti-interference simulation time base circuit output terminal and be connected with selection unit.
For improving effect of the invention process, time described, base chip U2 is KA555 integrated chip, this KA555 integrated chip has low, the easy use of cost, it is wide to adapt to, drive current greatly and the advantage such as stronger load capacity.
As mentioned above, just the present invention can well be realized.
Claims (6)
1. the intelligent electric meter strain controlling system based on anti-interference simulation time base circuit, primarily of processor, information acquisition unit, the analytic unit be all connected with processor and signal sort out unit, the signal confirmation unit that unit is connected is sorted out with signal, the protected location be all connected with signal confirmation unit and selection unit, and the display unit be connected with selection unit forms; It is characterized in that: between signal confirmation unit and selection unit, be also serially connected with anti-interference simulation time base circuit, between information acquisition unit and processor, be also serially connected with digital strain circuit.
2. a kind of intelligent electric meter strain controlling system based on anti-interference simulation time base circuit according to claim 1, it is characterized in that, described anti-interference simulation time base circuit by time base chip U2, triode VT3, triode VT4, field effect transistor Q1, negative pole is connected with the emitter of triode VT3 after resistance R18, the polar capacitor C9 that positive pole is connected with the collector of triode VT4 after resistance R15, positive pole is connected with the negative pole of polar capacitor C9 after resistance R17 through diode D7 in turn, the polar capacitor C7 of negative pole ground connection after resistance R13, N pole is connected with the negative pole of polar capacitor C9, the diode D11 that P pole is connected with the base stage of triode VT4 after resistance R19, N pole with time base chip U2 TR pin be connected, the diode D8 that P pole is connected with the positive pole of polar capacitor C9 after resistance R16, N pole with time base chip U2 R pin be connected, P pole is in turn through diode D9 that resistance R14 is connected with the collector of triode VT4 after polar capacitor C8, positive pole is connected with the collector of triode VT3, negative pole with time base chip U2 the polar capacitor C10 that is connected of Q pin, one end with time base chip U2 THR pin be connected, the resistance R20 that the other end is connected with the grid of field effect transistor Q1, P pole is connected with the source electrode of field effect transistor Q1, the diode D10 that N pole is connected with the drain electrode of field effect transistor Q1 after resistance R21, and positive pole is connected the N pole of diode D10 after resistance R22, the polar capacitor C11 of negative pole and ground connection forms, time described, the CV pin of base chip U2 is connected with the emitter of triode VT4 respectively with DIS pin, its VC pin is connected with the base stage of triode VT3, its GND pin ground connection, the negative pole of described polar capacitor C7 as anti-interference simulation time base circuit input end and be connected with signal confirmation unit, the positive pole of described polar capacitor C11 as anti-interference simulation time base circuit output terminal and be connected with selection unit.
3. a kind of intelligent electric meter strain controlling system based on anti-interference simulation time base circuit according to claim 2, it is characterized in that, described digital strain circuit is by process chip U1, amplifier P1, triode VT1, triode VT2, negative pole is connected with the base stage of triode VT2, positive pole is in turn through polar capacitor C5 that resistance R2 is connected with the VDD pin of process chip U1 after diode D1 and resistance R8, one end is connected with the base stage of triode VT2, the resistance R5 that the other end is connected with the EOC pin of process chip U1, input end as digital strain circuit while one end is connected with the positive pole of polar capacitor C5 is connected with information acquisition circuit, the resistance R3 that the other end is connected with the REF pin of process chip U1, minus earth, the polar capacitor C1 that positive pole is connected with the VDD pin of process chip U1 after resistance R4, N pole is connected with the emitter of triode VT2 after resistance R6, P pole is in turn through diode D3 that resistance R7 is connected with the OUT pin of process chip U1 after diode D4 and resistance R10, positive pole is connected with the collector of triode VT2, the polar capacitor C2 that negative pole is connected with the P pole of diode D3 after resistance R1, positive pole is connected with the IN pin of process chip U1, the polar capacitor C6 of minus earth, N pole is connected with the VDD pin of process chip U1 after inductance L, the diode D2 that P pole is connected with the DIN pin of process chip U1, positive pole is connected with the N pole of diode D2 after resistance R9, the polar capacitor C3 that negative pole is connected with the base stage of triode VT1, positive pole is connected with the emitter of triode VT1, the polar capacitor C4 that negative pole is connected with the CS pin of process chip U1 after diode D5, and P pole is connected with the collector of triode VT1 after resistance R11, the diode D6 that N pole is connected with the output terminal of amplifier P1 after resistance R12 forms, the negative pole of described amplifier P1 is connected with the OUT pin of process chip U1, its positive pole is connected with the negative pole of polar capacitor C4, its output terminal then as digital strain circuit output terminal and be connected with processor, the IN pin of described process chip U1 is connected with the N pole of diode D3, its GND pin ground connection.
4. a kind of intelligent electric meter strain controlling system based on anti-interference simulation time base circuit according to claim 3, is characterized in that, described selection unit is also connected with encrypted tunnel.
5. a kind of intelligent electric meter strain controlling system based on anti-interference simulation time base circuit according to claim 4, it is characterized in that, described signal confirmation unit is also connected with SIM unit.
6. a kind of intelligent electric meter strain controlling system based on anti-interference simulation time base circuit according to claim 5, it is characterized in that, described process chip U1 is MAX1494 integrated chip; Time described, base chip U2 is KA555 integrated chip.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510849013.0A CN105353688A (en) | 2015-11-27 | 2015-11-27 | Intelligent ammeter strain control system based on anti-interference analog time-base circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510849013.0A CN105353688A (en) | 2015-11-27 | 2015-11-27 | Intelligent ammeter strain control system based on anti-interference analog time-base circuit |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US6445239B1 (en) * | 1996-07-04 | 2002-09-03 | Siemens Aktiengesellschaft | Bus coupling with amplitude-controlled transmission circuit |
| CN202276369U (en) * | 2011-10-31 | 2012-06-13 | 深圳市腾邦物流股份有限公司 | Weight acquisition device for internet of things |
| CN104502693A (en) * | 2014-12-25 | 2015-04-08 | 芜湖市晨韵自动化科技有限公司 | Intelligent electric meter |
| CN104936347A (en) * | 2014-11-27 | 2015-09-23 | 成都雷克尔科技有限公司 | Composite protective logic amplification grid driving system based on bootstrap circuit |
-
2015
- 2015-11-27 CN CN201510849013.0A patent/CN105353688A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6445239B1 (en) * | 1996-07-04 | 2002-09-03 | Siemens Aktiengesellschaft | Bus coupling with amplitude-controlled transmission circuit |
| CN202276369U (en) * | 2011-10-31 | 2012-06-13 | 深圳市腾邦物流股份有限公司 | Weight acquisition device for internet of things |
| CN104936347A (en) * | 2014-11-27 | 2015-09-23 | 成都雷克尔科技有限公司 | Composite protective logic amplification grid driving system based on bootstrap circuit |
| CN104502693A (en) * | 2014-12-25 | 2015-04-08 | 芜湖市晨韵自动化科技有限公司 | Intelligent electric meter |
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