CN105336698A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
- Publication number
- CN105336698A CN105336698A CN201410328482.3A CN201410328482A CN105336698A CN 105336698 A CN105336698 A CN 105336698A CN 201410328482 A CN201410328482 A CN 201410328482A CN 105336698 A CN105336698 A CN 105336698A
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- CN
- China
- Prior art keywords
- filler
- protective layer
- semiconductor device
- polysilicon layer
- hole
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- Drying Of Semiconductors (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention provides a manufacturing method of a semiconductor device, The method comprises the following steps of firstly, forming a protection layer covering a selection grid, a control grid and a polysilicon layer on a substrate; then, carrying out photoetching and etching on the protection layer on the polysilicon layer and exposing parts of the polysilicon layer; at this time, depositing a filler possessing fluidity on a substrate surface so as to cover the protection layer, the polysilicon layer and a hole between the selection grid and the control grid, and then removing the filler on the protection layer and the polysilicon layer and only retaining the filler in the hole; after the above steps are completed, etching the polysilicon layer so as to form a logic grid. By using the manufacturing method of the semiconductor device, during etching, the hole is protected by the filler so that a problem that a material below the hole is damaged by etching can be solved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of manufacture method of semiconductor device.
Background technology
EEPROM (Electrically Erasable Programmable Read Only Memo) (Electrically-ErasableProgrammableRead-OnlyMemory, EEPROM) is a kind of semiconductor memory apparatus repeatedly can made carbon copies by electronics mode.Compare Erarable Programmable Read only Memory (ErasableProgrammableRead-OnlyMemory, EPROM), EEPROM does not need with Ultraviolet radiation, do not need to take off yet, just can use specific voltage, the information of erasing on chip, to write new data.
Usually will form logic area and controlled area when EEPROM manufactures, its order is in substrate, first form the controlled area comprising and select grid and control gate, then in all the other formation logic areas, region of substrate.Between selection grid and control gate, there is narrow hole, especially in high-precision EEPROM, the size of this hole is particularly narrow.Need to carry out etching polysilicon in the process forming logic area; during etching, described controlled area needs to utilize protective layer to carry out covering protection; after this hole exists, cannot ensure that described protective layer covers described hole completely when carrying out the deposition of protective layer before.Thus, in the process of carrying out etching polysilicon, the substrate below described hole can suffer damage because of etching, and then causes the performance of device to be affected.
Therefore, propose a kind of manufacture method of semiconductor device to manufacture EEPROM (Electrically Erasable Programmable Read Only Memo), the material below bottleneck pore can be protected when etching, becoming problem demanding prompt solution in prior art.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of manufacture method can protecting the semiconductor device of bottleneck pore underlying materials when etching, and comprises the following steps:
There is provided a substrate, described substrate comprises Part I and Part II, described Part I is formed and selects grid and control gate, described Part II is formed with polysilicon layer;
Form protective layer and cover described selection grid, control gate and described polysilicon layer;
Photoetching and etching technics are carried out to the protective layer on described polysilicon layer, polysilicon layer described in exposed portion;
Deposition has the filler of mobility, covers described protective layer, polysilicon layer and the hole between described selection grid and control gate;
Remove the described filler on described protective layer and polysilicon layer, only retain the filler in described hole;
Etch described polysilicon layer to form logic gate on described Part II; And
Remove the filler in described hole and described protective layer.
Optionally, described filler is bottom antireflective coating.
Optionally, described protective layer is insulation antireflecting coating.
Optionally, the thickness of described protective layer is
Optionally, the mode of employing dry etching removes the filler on described protective layer and polysilicon layer.
Optionally, the step of the filler removed in described hole comprises:
Substrate described in ashing and wet-cleaned is carried out to the filler in described hole.
Optionally, H is adopted
2sO
4and H
2o
2mixed solution wet-cleaned described in substrate, the time is 3 ~ 10 minutes.
Optionally, first remove the filler in described hole, then remove described protective layer.
Optionally, H is adopted
3pO
4protective layer described in solution removal.
Optionally, H is adopted
3pO
4the time of protective layer described in solution removal is 10 ~ 15 minutes.
Compared to prior art, first the manufacture method of semiconductor device provided by the invention forms protective layer and covers suprabasil selection grid, control gate and polysilicon layer; Again photoetching and etching technics are carried out to the protective layer on described polysilicon layer, polysilicon layer described in exposed portion; Now there is in substrate surface deposition the filler of mobility, it is made to cover described protective layer, polysilicon layer and the hole between described selection grid and control gate, remove the described filler on described protective layer and polysilicon layer again, only retain the filler in described hole; Described polysilicon layer is etched again to form logic gate after completing above-mentioned steps.The manufacture method of this kind of semiconductor device, when etching, has filler protection in hole, can solve hole underlying materials well because etching the problem be damaged.
Accompanying drawing explanation
Fig. 1 is the flow chart of the manufacture method of semiconductor device described in one embodiment of the invention;
The schematic diagram of each step of manufacture method that Fig. 2 to Fig. 8 is semiconductor device described in one embodiment of the invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
As shown in Figure 1, the manufacture method of described semiconductor device comprises the steps:
S1 a: substrate 100 is provided, described substrate 100 comprises Part I 101 and Part II 102, described Part I 101 is formed and selects grid 200a and control gate 200b, described Part II 102 is formed with polysilicon layer 200;
As shown in Figure 2, be formed on the surface of the Part I 101 of substrate 100 and select grid 200a and control gate 200b, be formed with polysilicon layer 200 on the surface of Part II 102.Between described selection grid 200a and control gate 200b, have narrow and small hole 10, especially in high-precision EEPROM, the size of this hole is particularly narrow.The steps such as known deposition, exposure, development, etching can be adopted to form described selection grid 200a, control gate 200b and polysilicon layer 200, repeat no more herein.
S2: form protective layer 300 in described substrate 100, described protective layer 300 covers described selection grid 200a, control gate 200b and described polysilicon layer 200, but exposes the substrate surface between described selection grid 200a and control gate 200b;
As shown in Figure 3; there is certain height and the two spacing is very little owing to selecting grid 200a and control gate 200b; that is select the hole 10 between grid 200a and control gate 200b very narrow and small; be difficult to cover this narrow zone in protective layer 300 filling process; in actual process; select the hole 10 between grid 200a and control gate 200b not fill by protective layer 300, the part of substrate 100 is exposed.In the present embodiment, protective layer 300 is insulation antireflecting coating (DARC), as its effect of bottom antireflective coating of protective layer 300 except protective layer, also has the antireflection effect to photoetching under ordinary meaning.The thickness of protective layer 300 is preferably
S3: photoetching and etching technics are carried out to the protective layer 300 on described polysilicon layer 200, polysilicon layer 200 described in exposed portion;
As shown in Figure 4; described protective layer 300 forms photoresist layer; the photoresist layer that exposure imaging forms patterning is carried out to described photoresist layer; the photoresist layer of described patterning exposes the specific region of the polysilicon layer 200 on the Part II 102 of described substrate 100; then with the photoresist layer of described patterning for mask; etch described protective layer 300, polysilicon layer 200 described in exposed portion.
S4: form filler 400 in described substrate 100, the substrate surface between described filler 400 protective mulch 300, polysilicon layer 200 and selection grid 200a and control gate 200b;
As shown in Figure 5, described filler 400 has mobility, can cover all regions of described substrate completely, can fill the hole 10 between described selection grid 200a and control gate 200b.In the present embodiment, described filler 400 is bottom antireflective coating (BARC), its more flowability, therefore, it is possible to the hole 10 of filling between described selection grid 200a and control gate 200b.
S5: remove the filler 400 on described protective layer 300 and polysilicon layer 200, only retains the filler in described hole 10;
As shown in Figure 6, dry etching is carried out to filler 400, because hole 10 is very narrow and small, filler in it is difficult to be etched into, by controlling etch technological condition as etch period, can ensure that most of filler 400 is etched away, the filler 400 only in remaining hole 10.Above-mentioned etch technological condition depends on material and the thickness of described filler 400, and those skilled in the art are known by limited number of time experiment, will not limit at this.
S6: etch described polysilicon layer 200 to form logic gate 200c on the Part II 102 of described substrate;
As shown in Figure 7; due to select grid 200a and control gate 200b all by protective layer 300 and filler 400 cover; protective layer 300 and filler 400 can play the effect of mask; therefore without the need to forming mask layer; directly substrate entirety is etched; the polysilicon layer 200 that on the Part II 102 etching away described substrate 100, non-protected seam covers; the Part II 102 of substrate 100 forms logic gate 200c; the bottom of hole 10 is owing to having the protection of filler 400 simultaneously, and the Part I 101 of substrate 100 is not suffered damage because of etching.
S7: remove the filler 400 in described hole 10 and described protective layer 300;
As shown in Figure 8, first remove the filler 400 in described hole 10, in the present embodiment, the method removing the filler 400 in described hole 10 is, the mode of ashing can be adopted to remove filler 400 in described hole 10.Preferably, after cineration technics, adopt H
2sO
4and H
2o
2mixed solution wet-cleaned described in substrate, scavenging period is 3 ~ 10 minutes.
Then, wet method removes described protective layer 300, such as, adopts H
3pO
4protective layer 300 described in solution removal, scavenging period is 10 ~ 15 minutes.
Compared to prior art, first the manufacture method of semiconductor device provided by the invention forms protective layer and covers suprabasil selection grid, control gate and polysilicon layer; Again photoetching and etching technics are carried out to the protective layer on described polysilicon layer, polysilicon layer described in exposed portion; Now there is in substrate surface deposition the filler of mobility, it is made to cover described protective layer, polysilicon layer and the hole between described selection grid and control gate, remove the described filler on described protective layer and polysilicon layer again, only retain the filler in described hole; Described polysilicon layer is etched again to form logic gate after completing above-mentioned steps.The manufacture method of this kind of semiconductor device, when etching, has filler protection in hole, can solve hole underlying materials well because etching the problem be damaged.
Obviously, those skilled in the art can carry out various change and modification to invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. a manufacture method for semiconductor device, is characterized in that, comprises the following steps:
There is provided a substrate, described substrate comprises Part I and Part II, described Part I is formed and selects grid and control gate, described Part II is formed with polysilicon layer;
Form protective layer and cover described selection grid, control gate and described polysilicon layer;
Photoetching and etching technics are carried out to the protective layer on described polysilicon layer, polysilicon layer described in exposed portion;
Deposition has the filler of mobility, covers described protective layer, polysilicon layer and the hole between described selection grid and control gate;
Remove the described filler on described protective layer and polysilicon layer, only retain the filler in described hole;
Etch described polysilicon layer to form logic gate on described Part II; And
Remove the filler in described hole and described protective layer.
2. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that: described filler is bottom antireflective coating.
3. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that: described protective layer is insulation antireflecting coating.
4. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that: the thickness of described protective layer is
5. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that: the mode of employing dry etching removes the filler on described protective layer and polysilicon layer.
6. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that: the step removing the filler in described hole comprises:
Ashing is carried out to the filler in described hole; And
Substrate described in wet-cleaned.
7. the manufacture method of semiconductor device as claimed in claim 6, is characterized in that: adopt H
2sO
4and H
2o
2mixed solution wet-cleaned described in substrate, the time is 3 ~ 10 minutes.
8. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that: first remove the filler in described hole, then removes described protective layer.
9. the manufacture method of semiconductor device as claimed in claim 8, is characterized in that: adopt H
3pO
4protective layer described in solution removal.
10. the manufacture method of semiconductor device as claimed in claim 9, is characterized in that: adopt H
3pO
4the time of protective layer described in solution removal is 10 ~ 15 minutes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410328482.3A CN105336698B (en) | 2014-07-10 | 2014-07-10 | The manufacturing method of semiconductor devices |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410328482.3A CN105336698B (en) | 2014-07-10 | 2014-07-10 | The manufacturing method of semiconductor devices |
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|---|---|
| CN105336698A true CN105336698A (en) | 2016-02-17 |
| CN105336698B CN105336698B (en) | 2018-11-16 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050142755A1 (en) * | 2003-12-24 | 2005-06-30 | Magnachip Semiconductor, Ltd. | Method for manufacturing a non-volatile memory device |
| US20080061358A1 (en) * | 2006-03-02 | 2008-03-13 | Embedded Memory, Inc. | Method of reducing memory cell size for non-volatile memory device |
| CN100403521C (en) * | 2005-04-26 | 2008-07-16 | 美格纳半导体有限会社 | Method for manufacturing a semiconductor device |
| CN101252133A (en) * | 2007-02-22 | 2008-08-27 | 富士通株式会社 | Semiconductor device and method for manufacturing the same |
| CN101842899A (en) * | 2007-10-29 | 2010-09-22 | 飞思卡尔半导体公司 | Method for integrating NVM circuitry with logic circuitry |
-
2014
- 2014-07-10 CN CN201410328482.3A patent/CN105336698B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050142755A1 (en) * | 2003-12-24 | 2005-06-30 | Magnachip Semiconductor, Ltd. | Method for manufacturing a non-volatile memory device |
| CN100403521C (en) * | 2005-04-26 | 2008-07-16 | 美格纳半导体有限会社 | Method for manufacturing a semiconductor device |
| US20080061358A1 (en) * | 2006-03-02 | 2008-03-13 | Embedded Memory, Inc. | Method of reducing memory cell size for non-volatile memory device |
| CN101252133A (en) * | 2007-02-22 | 2008-08-27 | 富士通株式会社 | Semiconductor device and method for manufacturing the same |
| CN101842899A (en) * | 2007-10-29 | 2010-09-22 | 飞思卡尔半导体公司 | Method for integrating NVM circuitry with logic circuitry |
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|---|---|
| CN105336698B (en) | 2018-11-16 |
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