CN105336692A - Method for adjusting work function layer in under metal gate - Google Patents
Method for adjusting work function layer in under metal gate Download PDFInfo
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- CN105336692A CN105336692A CN201510608987.XA CN201510608987A CN105336692A CN 105336692 A CN105336692 A CN 105336692A CN 201510608987 A CN201510608987 A CN 201510608987A CN 105336692 A CN105336692 A CN 105336692A
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- groove
- function layer
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- work function
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- 238000000034 method Methods 0.000 title claims abstract description 51
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 28
- 239000002184 metal Substances 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 229910010037 TiAlN Inorganic materials 0.000 claims abstract description 8
- 230000008021 deposition Effects 0.000 claims abstract description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract 2
- 238000000137 annealing Methods 0.000 claims description 13
- 238000005468 ion implantation Methods 0.000 claims description 11
- 230000007704 transition Effects 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 6
- REDXJYDRNCIFBQ-UHFFFAOYSA-N aluminium(3+) Chemical compound [Al+3] REDXJYDRNCIFBQ-UHFFFAOYSA-N 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 10
- 229910010038 TiAl Inorganic materials 0.000 abstract description 5
- 230000004888 barrier function Effects 0.000 abstract description 4
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- -1 aluminum ions Chemical class 0.000 abstract description 2
- 238000002513 implantation Methods 0.000 abstract description 2
- 238000005457 optimization Methods 0.000 abstract description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical group [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 10
- 238000012545 processing Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000009467 reduction Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention relates to the field of semiconductor device optimization and specifically to a method for adjusting a work function layer in under metal gate technology. In high-k under metal gate semiconductor technology, TiN is implanted by means of aluminum ions and is annealed so that TiAlN is formed. An individually-deposited TiAl layer is replaced so that a NMOS work function layer is formed. One-time metal film deposition achieves an N-type work function layer and a P-type work function layer and barrier layer and selectivity removing technology is eliminated in a common under metal gate process. Thus, the process is greatly simplified and it is easy to adjust the NMOS work function by controlling the implantation amount of the Al.
Description
Technical field
The present invention relates to semiconductor device piece optimization field, particularly relate to work-function layer control method in a kind of rear metal gates.
Background technology
Along with developing rapidly of very large scale integration technology, the size of MOSFET element, in continuous reduction, generally includes the reduction of MOSFET element channel length, and the thinning grade of gate oxide thickness is to obtain device speed faster.But when being developed to sub-micro level, particularly when 45 nanometers and following technology node, cannot bear the height electric leakage continuing reduction gate oxide thickness and bring.Industry introduces the design of high k and metal gate in 45 nanometers and following technique.And industry more and more turns to rear metal gate process at present.
So need work-function layer control method in a kind of novel rear metal gates badly.
Summary of the invention
In view of the above problems, the invention provides work-function layer control method in a kind of rear metal gates.
Work-function layer control method in metal gates after a kind of, is characterized in that, comprising:
One is provided to have the NMOS area of the first groove and have the semiconductor device of PMOS area of the second groove;
Uniform first work-function layer of deposit one thickness in the interior surface of described first groove and described second groove;
Deposition DUO is to the top planes of described first groove and described second groove;
Etching removes the described DUO in described first groove;
Ion implantation is carried out to described semiconductor device;
Remove the described DUO in described second groove;
Annealing, to form the second work-function layer of rear metal gates in described NMOS area.
Above-mentioned method, wherein, the material of described first work-function layer is TiN.
Above-mentioned method, wherein, described ion is aluminium ion.
Above-mentioned method, wherein, described Al ion implantation energy is 0.1-10keV.
Above-mentioned method, wherein, described Al ion implantation amount is 1E15-1E19.
Above-mentioned method, wherein, annealing temperature is 50 DEG C-1250 DEG C.
Above-mentioned method, wherein, annealing time is 0.1-1000s.
Above-mentioned method, wherein, described first work-function layer is P type work-function layer.
Above-mentioned method, wherein, described first groove and described second bottom portion of groove surface are provided with transition zone, and surperficial, described first groove of described transition zone and described second recess sidewall deposit high-k dielectric layer.
The method stated, wherein, the material of described second work-function layer is TiAlN.
In sum, the present invention proposes a kind of method regulating work-function layer in rear metal gate process, by in metal gate semiconductor technology after high k, utilize Al ion implantation TiN and annealing formation TiAlN, the TiAl layer substituting independent deposit realizes NMOS work-function layer.Only just achieve N-type and P type two kinds of work-function layer with a metal film deposition, also eliminate the barrier layer in general rear metal gate processing procedure and selective removal technique, significantly simplify processing procedure, also more easily realized the adjustment of NMOS work function simultaneously by the injection rate of control Al.
Accompanying drawing explanation
With reference to appended accompanying drawing, to describe embodiments of the invention more fully.But, appended accompanying drawing only for illustration of and elaboration, do not form limitation of the scope of the invention.
Fig. 1-Fig. 7 is structural profile schematic diagram of the present invention.
Embodiment
In order to make technical scheme of the present invention and advantage easy to understand more, be described in further detail below in conjunction with accompanying drawing.Should illustrate, specific embodiment described herein only in order to explain the present invention, is not intended to limit the present invention.
After high k in metal gate semiconductor technology, usually select TiN as the work-function layer of PMOS, and TiAl is as the work-function layer of NMOS, this dimorphism work-function layer technique not only needs barrier layer and selectivity to remove technique, also can introduce extra device fluctuating factor because of the fluctuation of these processing procedures itself.
As shown in Fig. 1-Fig. 7, the present invention designs work-function layer control method in a kind of rear metal gates, and the method comprises:
First semiconductor device is provided, this semiconductor device includes NOMS region and PMOS area, the first groove 11 and the second groove 22 is formed respectively in NMOS area and PMOS area, and the pattern of the first groove 1 and the second groove 2 is identical, bottom portion of groove is the upper surface of silicon substrate, then in the groove that silicon substrate is bottom, one deck transition zone is deposited, this transition zone can be silica, then deposits one deck high-k dielectric layer at the upper surface of the first groove 1 being the end with this transition zone and the second groove 2 madial wall and transition zone.The dielectric layer of to be one deck with SiN the be material that the silicon substrate of this semiconductor device deposits, then etches a groove respectively in the PMOS area of this dielectric layer and NMOS area.
Then in deposited on silicon one deck first work-function layer 3 of the high-k dielectric layer of the first groove 1 and the second groove 2, this first work-function layer 3 is P type work-function layer, this P type work-function layer is that disposable deposition is formed, and the thickness of deposition is determined according to PMOS demand, concrete will calculate according to the functional requirement of semiconductor device.After having deposited one deck P type work-function layer, in the first groove 1 and the second groove 2, deposit DUO4, and this DUO4 is whole fills up the first groove 1 and the second groove 2, and to the top planes of the first groove 1 and the second groove 2.
After having deposited DUO4, but remove the DUO4 of NMOS area, the TiN in the second groove 2 is come out completely, then Al ion implantation is carried out to this semiconductor device, time concrete in injection process, aluminum ions Implantation Energy is 0.1 ~ 10keV, and injection rate is 1E15 ~ 1E19.Remove the DUO of the second groove 2 in PMOS area after having injected aluminium ion, in the first groove 1 of NMOS area, form one deck Al layer 5 like this, then carry out annealing process, the annealing temperature of this annealing process is 50 ~ 1250 DEG C, and the time is 0.1 ~ 1000s.
After above-mentioned step, in the first groove 1 of NMOS area, define the second work-function layer 6 that one deck TiAlN is material.Finally the first groove 1 and the second groove 2 are carried out to the filling of metal, to form rear metal gates.
Be described below in conjunction with specific embodiment
Embodiment
After high k in metal gate semiconductor technology, the present invention utilizes Al ion implantation TiN and annealing forms TiAlN, and the TiAl layer substituting independent deposit realizes NMOS work-function layer.This method only just achieves N-type and P type two kinds of work-function layer with a metal film deposition, also eliminate the barrier layer in general rear metal gate processing procedure and selective removal technique, significantly simplify processing procedure, also more easily realized the adjustment of NMOS work function simultaneously by the injection rate of control Al.Concrete grammar is as follows:
Step 1 on wafer according to before P type work-function layer titanium nitride (TiN) deposit above the paramount k dielectric layer of normal process flow;
Step 2 according to PMOS demand determination thickness, individual layer disposable deposit P type work-function layer TiN;
Step 3 carries out normal DUO filling;
Step 4 removes the DUO of NMOS area by photoetching and etching, exposes TiN;
Step 5 aluminium (Al) ion implantation;
Step 6 removes remaining photoresistance and DUO on wafer;
Step 7 makes fully to spread to form TiAlN in the TiN layer of Al on NMOS by annealing process, becomes the work-function layer of NMOS;
Step 8 follow-up normal metal gate electrode fill process.
By the explanation of above-described embodiment, the present invention is after high k in metal gate semiconductor technology, and utilize Al ion implantation TiN and annealing formation TiAlN, the TiAl layer substituting independent deposit realizes NMOS work-function layer.Method is simple, easy to operate.
By illustrating and accompanying drawing, giving the exemplary embodiments of the ad hoc structure of embodiment, based on the present invention's spirit, also can do other conversion.Although foregoing invention proposes existing preferred embodiment, but these contents are not as limitation.
For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present invention and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.
Claims (10)
1. a work-function layer control method in metal gates after, is characterized in that, comprising:
There is provided one have the NMOS area of the first groove and have the semiconductor device of PMOS area of the second groove, and described NMOS area is provided with the first groove, described PMOS area region is provided with the second groove;
Uniform first work-function layer of deposit one thickness in the interior surface of described first groove and described second groove;
Deposition DUO is to the top planes of described first groove and described second groove;
Etching removes the described DUO in described first groove;
Ion implantation is carried out to described semiconductor device;
Remove the described DUO in described second groove;
Annealing, to form the second work-function layer of rear metal gates in described NMOS area.
2. method according to claim 1, is characterized in that: the material of described first work-function layer is TiN.
3. method according to claim 1, is characterized in that, described ion is aluminium ion.
4. method according to claim 3, is characterized in that, described Al ion implantation energy is 0.1-10keV.
5. method according to claim 3, is characterized in that, described Al ion implantation amount is 1E15-1E19.
6. method according to claim 1, is characterized in that, annealing temperature is 50 DEG C-1250 DEG C.
7. method according to claim 1, is characterized in that, annealing time is 0.1-1000s.
8. method according to claim 1, is characterized in that, described first work-function layer is P type work-function layer.
9. method according to claim 1, is characterized in that, described first groove and described second bottom portion of groove surface are provided with transition zone, and surperficial, described first groove of described transition zone and described second recess sidewall deposit high-k dielectric layer.
10. method according to claim 1, is characterized in that, the material of described second work-function layer is TiAlN.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510608987.XA CN105336692A (en) | 2015-09-22 | 2015-09-22 | Method for adjusting work function layer in under metal gate |
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|---|---|---|---|
| CN201510608987.XA CN105336692A (en) | 2015-09-22 | 2015-09-22 | Method for adjusting work function layer in under metal gate |
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| CN201510608987.XA Pending CN105336692A (en) | 2015-09-22 | 2015-09-22 | Method for adjusting work function layer in under metal gate |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106328510A (en) * | 2016-08-31 | 2017-01-11 | 上海华力微电子有限公司 | Metal gate forming method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6586288B2 (en) * | 2000-11-16 | 2003-07-01 | Hynix Semiconductor Inc. | Method of forming dual-metal gates in semiconductor device |
| CN101095223A (en) * | 2004-09-08 | 2007-12-26 | 英特尔公司 | A method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode |
| CN104064452A (en) * | 2013-03-21 | 2014-09-24 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor device |
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- 2015-09-22 CN CN201510608987.XA patent/CN105336692A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6586288B2 (en) * | 2000-11-16 | 2003-07-01 | Hynix Semiconductor Inc. | Method of forming dual-metal gates in semiconductor device |
| CN101095223A (en) * | 2004-09-08 | 2007-12-26 | 英特尔公司 | A method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode |
| CN104064452A (en) * | 2013-03-21 | 2014-09-24 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106328510A (en) * | 2016-08-31 | 2017-01-11 | 上海华力微电子有限公司 | Metal gate forming method |
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Application publication date: 20160217 |